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Searched refs:FADD (Results 1 – 25 of 71) sorted by relevance

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/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
Dassembler-cases.txt7 01 02 00 00 00 c0 a4 00 FADD.f32 r0, r1, r2
8 01 02 00 00 20 c0 a4 00 FADD.f32 r0, r1, r2.abs
9 01 02 00 00 10 c0 a4 00 FADD.f32 r0, r1, r2.neg
10 01 02 00 00 30 c0 a4 00 FADD.f32 r0, r1, r2.neg.abs
11 01 02 00 00 32 c0 a4 00 FADD.f32.clamp_m1_1 r0, r1, r2.neg.abs
13 01 d0 00 00 00 c0 a4 00 FADD.f32 r0, r1, 0x3F800000
14 01 d0 00 00 10 c0 a4 00 FADD.f32 r0, r1, 0x3F800000.neg
15 01 c0 00 00 00 c0 a4 00 FADD.f32 r0, r1, 0x0
16 01 c0 00 00 10 c0 a4 00 FADD.f32 r0, r1, 0x0.neg
18 01 00 00 08 00 c0 a4 00 FADD.f32 r0, r1, r0.h1
[all …]
Dnegative-cases.txt1 FADD.f32 r0, r1
9 FADD.v2f16 r0, r1, r0.h0
16 FADD.f32 r0, u0, u4
17 FADD.f32 r0, u5, u3
18 FADD.f32 r0, u5, u6
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp208 { ISD::FADD, MVT::v2f64, 2 }, // addpd in getArithmeticInstrCost()
543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
837 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
DX86IntrinsicsInfo.h418 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
419 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
/third_party/mesa3d/docs/relnotes/
D21.3.7.rst43 - pan/bi: Avoid \*FADD.v2f16 hazard in optimizer
44 - pan/bi: Avoid \*FADD.v2f16 hazard in scheduler
/third_party/ltp/tools/sparse/sparse-src/
Dopcode.def18 OPCODE(ADD, BADOP, BADOP, BADOP, FADD, 2, OPF_TARGET|OPF_COMMU|OPF_ASSOC|OPF_BINOP)
30 OPCODE(FADD, BADOP, BADOP, BADOP, BADOP, 2, OPF_TARGET)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DConstrainedOps.def38 INSTRUCTION(FAdd, 2, 1, experimental_constrained_fadd, FADD)
/third_party/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.h194 A_ALU2(FADD)
Dvc4_qpu_emit.c258 A(FADD), in vc4_generate_code_block()
Dvc4_qir.h674 QIR_ALU2(FADD) in QIR_ALU1()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp4999 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5002 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5015 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5018 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5021 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5036 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5039 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5042 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5045 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
5048 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
[all …]
DLegalizeVectorOps.cpp377 case ISD::FADD: in LegalizeOp()
1405 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1426 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
DDAGCombiner.cpp1570 case ISD::FADD: return visitFADD(N); in visit()
12071 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
12142 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags); in visitFADD()
12146 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags); in visitFADD()
12181 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags); in visitFADD()
12187 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags); in visitFADD()
12213 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
12215 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1, Flags); in visitFADD()
12216 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC, Flags); in visitFADD()
12229 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), in visitFADD()
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DSelectionDAGBuilder.h695 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
DLegalizeFloatTypes.cpp73 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
1135 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
1620 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, in ExpandFloatRes_XINT_TO_FP()
2126 case ISD::FADD: in PromoteFloatResult()
DSelectionDAGDumper.cpp248 case ISD::FADD: return "fadd"; in getOperationName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp406 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
497 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
513 case ISD::FADD: in fnegFoldsIntoOp()
2061 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2194 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND_LegalFTRUNC()
2288 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2501 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3688 case ISD::FADD: { in performFNegCombine()
3706 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
[all …]
DAMDGPUTargetTransformInfo.cpp404 case ISD::FADD: in getArithmeticInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp520 setTargetDAGCombine(ISD::FADD); in NVPTXTargetLowering()
537 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering()
2116 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32()
2147 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64()
4391 if (User->getOpcode() != ISD::FADD) in PerformADDCombineWithOperands()
4762 case ISD::FADD: in PerformDAGCombine()
/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_target_gv100.cpp150 OPINFO(FADD , R , NA , RIC , NA , NONE, NONE);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
DAArch64SchedA57.td428 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
430 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
/third_party/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h1319 VIR_A_ALU2(FADD)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td34 defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,

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