1FADD.f32 r0, r1 2TEX.computed.2d.slot0 @r2, @r4:r5:r6:r7 3BRANCH 4BRANCH #0 5BRANCH #0, offset: 6BRANCH u0, offset:-123456789 7BRANCH u0, offset:123456789 8IADD_IMM.i32 r3, #12345 9FADD.v2f16 r0, r1, r0.h0 10MOV.i32.wait01.wait1 r0, r1 11MOV.i32.wait01.return r0, r1 12MOV.i32.reconverge.return r0, r1 13FROUND.f32.rtn.clamp_m1_1 r2, `r2.neg 14 15# An instruction may access no more than a single 64-bit uniform slot. 16FADD.f32 r0, u0, u4 17FADD.f32 r0, u5, u3 18FADD.f32 r0, u5, u6 19 20# An instruction may access no more than 64-bits of combined uniforms and constants. 21FMA.f32 r0, u0, u1, 0x0 22FMA.f32 r0, u0, 0x40490FDB, 0x0 23FMA.f32 r0, 0x3F317218, 0x40490FDB, 0x0 24 25# An instruction may access no more than a single special immediate (e.g. lane_id). 26IADD.u32 r0, lane_id, core_id 27IADD.u32 r0, lane_id, core_id 28IADD.u32 r0, tls_ptr, wls_ptr 29 30# If an instruction accesses multiple staging registers, they must be aligned 31# to a register pair. 32LOAD.i32.unsigned.slot0.wait0 @r1:r2, `r0, offset:0 33STORE.i32.slot0.reconverge @r3:r4:r5, `r2, offset:0 34STORE.i96.vary.slot0.return @r1:r2:r3:r4, `r4, offset:0 35