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Searched refs:GFX10 (Results 1 – 25 of 150) sorted by relevance

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/third_party/mesa3d/src/amd/compiler/tests/
Dtest_assembler.cpp29 for (unsigned i = GFX6; i <= GFX10; i++) {
44 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
63 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
92 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
124 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
151 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
179 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
204 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
230 for (unsigned i = GFX9; i <= GFX10; i++) {
248 for (unsigned i = GFX9; i <= GFX10; i++) {
[all …]
Dtest_regalloc.cpp65 if (!setup_cs("v1", GFX10))
84 if (!setup_cs("s2", GFX10))
103 if (!setup_cs("s2 s1", GFX10))
120 if (!setup_cs("s2 s1 s1", GFX10))
137 if (!setup_cs("s2 s1 s1", GFX10))
191 if (!setup_cs("", GFX10))
212 if (!setup_cs("", GFX10))
243 if (!setup_cs("", GFX10))
268 if (!setup_cs("", GFX10))
293 if (!setup_cs("", GFX10))
[all …]
Dtest_sdwa.cpp30 for (unsigned i = GFX8; i <= GFX10; i++) {
67 for (unsigned i = GFX8; i <= GFX10; i++) {
96 for (unsigned i = GFX8; i <= GFX10; i++) {
117 for (unsigned i = GFX8; i <= GFX10; i++) {
133 for (unsigned i = GFX8; i <= GFX10; i++) {
154 for (unsigned i = GFX7; i <= GFX10; i++) {
278 for (unsigned i = GFX8; i <= GFX10; i++) {
335 for (unsigned i = GFX8; i <= GFX10; i++) {
379 for (unsigned i = GFX8; i <= GFX10; i++) {
411 if (i >= GFX10) {
[all …]
Dtest_hard_clause.cpp99 if (!setup_cs(NULL, GFX10))
167 if (!setup_cs(NULL, GFX10))
206 for (unsigned i = GFX10; i <= GFX10_3; i++) {
239 if (!setup_cs(NULL, GFX10))
330 if (!setup_cs(NULL, GFX10))
Dtest_optimizer.cpp29 for (unsigned i = GFX9; i <= GFX10; i++) {
273 for (unsigned i = GFX9; i <= GFX10; i++) {
317 for (unsigned i = GFX8; i <= GFX10; i++) {
399 for (unsigned i = GFX8; i <= GFX10; i++) {
716 for (unsigned i = GFX9; i <= GFX10; i++) {
760 for (unsigned i = GFX8; i <= GFX10; i++) {
1053 if (!setup_cs("v1 s1", GFX10))
1163 for (unsigned i = GFX9; i <= GFX10; i++) {
1198 for (unsigned i = GFX9; i <= GFX10; i++) {
1251 for (unsigned i = GFX9; i <= GFX10; i++) {
[all …]
Dtest_insert_nops.cpp53 if (!setup_cs(NULL, GFX10))
117 if (!setup_cs(NULL, GFX10))
Dtest_isel.cpp85 for (unsigned i = GFX8; i <= GFX10; i++) {
114 for (unsigned i = GFX8; i <= GFX10; i++) {
/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c94 info->gfx_level = GFX10; in radv_null_winsys_query_info()
116 else if (info->gfx_level >= GFX10) in radv_null_winsys_query_info()
123 if (info->gfx_level >= GFX10) in radv_null_winsys_query_info()
130 info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256; in radv_null_winsys_query_info()
131 info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4; in radv_null_winsys_query_info()
132 info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024; in radv_null_winsys_query_info()
/third_party/mesa3d/src/amd/compiler/
Daco_print_asm.cpp143 case GFX10: in to_clrx_device_name()
278 if (gfx_level >= GFX10 && l == 8 && ((binary[pos] & 0xffff0000) == 0xd7610000) && in disasm_instr()
289 (gfx_level >= GFX10 && in disasm_instr()
293 (gfx_level >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ in disasm_instr()
296 bool has_literal = gfx_level >= GFX10 && (((binary[pos + 1] & 0x1ff) == 0xff) || in disasm_instr()
299 } else if (gfx_level >= GFX10 && l == 4 && ((binary[pos] & 0xfe0001ff) == 0x020000f9)) { in disasm_instr()
326 } else if (gfx_level >= GFX10 && (binary[pos] & 0xfc000000) == 0xf4000000 && in disasm_instr()
359 if (program->gfx_level >= GFX10 && program->wave_size == 64) { in print_asm_llvm()
Daco_assembler.cpp57 else if (gfx_level >= GFX10) in asm_context()
126 assert(ctx.gfx_level >= GFX10); in emit_instruction()
130 assert(ctx.gfx_level >= GFX10); in emit_instruction()
240 uint32_t soffset = ctx.gfx_level >= GFX10 in emit_instruction()
310 } else if (ctx.gfx_level >= GFX10) { in emit_instruction()
392 } else if (ctx.gfx_level >= GFX10) { in emit_instruction()
398 if (ctx.gfx_level <= GFX7 || ctx.gfx_level >= GFX10) { in emit_instruction()
417 assert(!mtbuf.dlc || ctx.gfx_level >= GFX10); in emit_instruction()
443 if (ctx.gfx_level >= GFX10) { in emit_instruction()
452 assert(!nsa_dwords || ctx.gfx_level >= GFX10); in emit_instruction()
[all …]
Daco_ir.cpp82 case GFX10: program->family = CHIP_NAVI10; break; in init_program()
102 if (gfx_level >= GFX10) { in init_program()
127 else if (program->gfx_level == GFX10) in init_program()
132 program->dev.simd_per_cu = program->gfx_level >= GFX10 ? 2 : 4; in init_program()
151 program->dev.has_mac_legacy32 = program->gfx_level <= GFX7 || program->gfx_level >= GFX10; in init_program()
153 program->dev.fused_mad_mix = program->gfx_level >= GFX10; in init_program()
161 } else if (program->gfx_level >= GFX10 || program->gfx_level == GFX8) { in init_program()
493 case aco_opcode::v_cos_f16: return gfx_level >= GFX10; in instr_is_16bit()
501 default: return gfx_level >= GFX10 && can_use_opsel(gfx_level, op, -1); in instr_is_16bit()
824 if (gfx_level >= GFX10) in wait_imm()
[all …]
Daco_insert_waitcnt.cpp197 max_lgkm_cnt(program_->gfx_level >= GFX10 ? 62 : 14), in wait_ctx()
198 max_vs_cnt(program_->gfx_level >= GFX10 ? 62 : 0), in wait_ctx()
199 unordered_events(event_smem | (program_->gfx_level < GFX10 ? event_flat : 0)) in wait_ctx()
353 if (ctx.gfx_level >= GFX10) { in force_waitcnt()
381 if (ctx.gfx_level >= GFX10 && instr->isSMEM()) { in kill()
562 assert(ctx.gfx_level < GFX10); in update_counters_for_flat_load()
648 if (ctx.gfx_level < GFX10 && !instr->definitions.empty()) in gen()
663 else if (ctx.gfx_level >= GFX10 && !smem.sync.can_reorder()) in gen()
690 !instr->definitions.empty() || ctx.gfx_level < GFX10 ? event_vmem : event_vmem_store; in gen()
719 assert(ctx.gfx_level >= GFX10); in emit_waitcnt()
DREADME-ISA.md177 Since GFX10+ these are fully independent of each other, A16 controls 16 bit addresses
206 ## RDNA / GFX10 hazards
213 This is not mentioned by LLVM among the other GFX10 bugs, but LLVM doesn't use
248 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
255 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
286 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
290 NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid
Daco_statistics.cpp115 if (program->gfx_level >= GFX10) { in get_perf_info()
268 unsigned max_lgkm_cnt = program->gfx_level >= GFX10 ? 62 : 14; in get_wait_imm()
309 } else if (program->gfx_level >= GFX10) { in get_dependency_cost()
318 if (program->gfx_level < GFX10) in get_dependency_cost()
360 bool dual_issue = program->gfx_level >= GFX10 && program->wave_size == 64 && in add()
369 cur_cycle += program->gfx_level >= GFX10 ? 1 : perf.latency; in add()
/third_party/mesa3d/src/amd/common/
Dac_surface_test_common.h99 info->gfx_level = GFX10; in init_navi10()
113 info->gfx_level = GFX10; in init_navi14()
207 case GFX10: in get_radeon_info()
216 info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1; in get_radeon_info()
Dac_gpu_info.c854 info->gfx_level = GFX10; in ac_query_gpu_info()
959 if (info->gfx_level >= GFX10) { in ac_query_gpu_info()
1029 info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024; in ac_query_gpu_info()
1054 info->gfx_level >= GFX10 || (info->gfx_level >= GFX8 && info->max_se >= 2); in ac_query_gpu_info()
1057 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->gfx_level >= GFX10; in ac_query_gpu_info()
1099 info->has_zero_index_buffer_bug = info->gfx_level == GFX10; in ac_query_gpu_info()
1111 info->has_two_planes_iterate256_bug = info->gfx_level == GFX10; in ac_query_gpu_info()
1114 info->has_vgt_flush_ngg_legacy_bug = info->gfx_level == GFX10 || in ac_query_gpu_info()
1132 info->has_32bit_predication = (info->gfx_level >= GFX10 && in ac_query_gpu_info()
1187 unsigned cu_group = info->gfx_level >= GFX10 ? 2 : 1; in ac_query_gpu_info()
[all …]
Dac_sqtt.c70 if (rad_info->gfx_level >= GFX10) { in ac_is_thread_trace_complete()
93 if (rad_info->gfx_level >= GFX10) { in ac_get_expected_buffer_size()
Dac_shader_util.c318 } else if (gfx_level >= GFX10) { in ac_get_tbuffer_format()
677 if (info->gfx_level >= GFX10) { in ac_compute_late_alloc()
687 if (info->gfx_level == GFX10 && ngg) in ac_compute_late_alloc()
695 *cu_mask &= info->gfx_level == GFX10 ? ~BITFIELD_RANGE(2, 2) : in ac_compute_late_alloc()
Dac_shadowed_regs.c1262 else if (gfx_level == GFX10) in ac_get_reg_ranges()
1272 else if (gfx_level == GFX10) in ac_get_reg_ranges()
1280 else if (gfx_level == GFX10_3 || gfx_level == GFX10) in ac_get_reg_ranges()
1290 else if (gfx_level == GFX10_3 || gfx_level == GFX10) in ac_get_reg_ranges()
1302 else if (gfx_level == GFX10) in ac_get_reg_ranges()
4038 } else if (info->gfx_level == GFX10) { in ac_emulate_clear_state()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h37 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_of…
266 if (sctx->gfx_level >= GFX10) \
334 if (gfx_level >= GFX10) { in si_get_user_data_base()
341 } else if (gfx_level >= GFX10) { in si_get_user_data_base()
363 if (gfx_level >= GFX10) { in si_get_user_data_base()
Dsi_sqtt.c106 if (sctx->gfx_level >= GFX10) { in si_emit_thread_trace_start()
252 case GFX10: in si_copy_thread_trace_info_regs()
326 if (sctx->gfx_level >= GFX10) { in si_emit_thread_trace_stop()
580 sctx->screen->info.gfx_level >= GFX10 ? (first_active_cu / 2) : first_active_cu; in si_get_thread_trace()
642 if (sctx->gfx_level >= GFX10) { in si_init_thread_trace()
703 if (sctx->gfx_level >= GFX10) in si_destroy_thread_trace()
756 if (sctx->gfx_level >= GFX10) in si_handle_thread_trace()
787 … radeon_set_uconfig_reg_seq(R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->gfx_level >= GFX10); in si_emit_thread_trace_userdata()
809 if (sctx->gfx_level >= GFX10) in si_emit_spi_config_cntl()
Dsi_state_shaders.cpp46 if (sscreen->info.gfx_level < GFX10) in si_determine_wave_size()
121 !(sscreen->info.gfx_level == GFX10 && shader && shader->key.ge.opt.ngg_culling)) in si_determine_wave_size()
504 if (shader->selector->screen->info.gfx_level < GFX10) in si_shader_mem_ordered()
591 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.gfx_level >= GFX10) in polaris_set_vgt_vertex_reuse()
649 if (sscreen->info.gfx_level >= GFX10) in si_get_vs_vgpr_comp_cnt()
725 if (sscreen->info.gfx_level >= GFX10) { in si_shader_hs()
736 if (sscreen->info.gfx_level >= GFX10) in si_shader_hs()
755 S_00B428_WGP_MODE(sscreen->info.gfx_level >= GFX10) | in si_shader_hs()
992 … (sctx->gfx_level >= GFX10 ? radeon_set_sh_reg_idx3_func : radeon_set_sh_reg_func)); in si_emit_shader_gs()
995 if (sctx->gfx_level >= GFX10) { in si_emit_shader_gs()
[all …]
Dsi_state_draw.cpp42 #define GFX(name) name##GFX10
232 if (GFX_VERSION >= GFX10) in si_update_shaders()
239 } else if (GFX_VERSION >= GFX10) { in si_update_shaders()
289 if (GFX_VERSION >= GFX10 && sctx->screen->use_ngg_culling) in si_update_shaders()
467 case GFX10: in si_cp_dma_prefetch()
468 si_cp_dma_prefetch_inline<GFX10>(sctx, buf, offset, size); in si_cp_dma_prefetch()
809 if (sctx->gfx_level >= GFX10) in si_emit_derived_tess_state()
1243 if (NGG || (GFX_VERSION >= GFX10 && GFX_VERSION <= GFX10_3)) in si_emit_vs_state()
1381 if (GFX_VERSION >= GFX10) in si_emit_draw_registers()
1393 if (GFX_VERSION >= GFX10) in si_emit_draw_registers()
[all …]
/third_party/mesa3d/src/amd/vulkan/
Dradv_sqtt.c100 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_emit_thread_trace_start()
230 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_copy_thread_trace_info_regs()
286 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_emit_thread_trace_stop()
356 if (device->physical_device->rad_info.gfx_level >= GFX10) in radv_emit_thread_trace_userdata()
375 if (device->physical_device->rad_info.gfx_level >= GFX10) in radv_emit_spi_config_cntl()
393 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_emit_inhibit_clockgating()
696 thread_trace_se.compute_unit = device->physical_device->rad_info.gfx_level >= GFX10 in radv_get_thread_trace()
Dradv_shader.c1632 return chip >= GFX10; in radv_should_use_wgp_mode()
1634 return chip == GFX10 || (chip >= GFX10_3 && !info->is_ngg); in radv_should_use_wgp_mode()
1637 return chip == GFX10 && info->is_ngg; in radv_should_use_wgp_mode()
1664 assert((pdevice->rad_info.gfx_level >= GFX10 && num_shared_vgprs % 8 == 0) || in radv_postprocess_config()
1665 (pdevice->rad_info.gfx_level < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config()
1694 if (pdevice->rad_info.gfx_level >= GFX10) { in radv_postprocess_config()
1706 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1717 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1728 if (pdevice->rad_info.gfx_level >= GFX10) { in radv_postprocess_config()
1745 S_00B428_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B428_WGP_MODE(wgp_mode); in radv_postprocess_config()
[all …]

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