Searched refs:INTEL_MASK (Results 1 – 11 of 11) sorted by relevance
| /third_party/mesa3d/src/intel/perf/ |
| D | intel_perf_regs.h | 27 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
32 #define GFX7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
34 #define GFX7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
38 #define GFX9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
40 #define GFX9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir.h | 190 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
192 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
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| D | brw_eu_defines.h | 43 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
55 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
56 fieldval & INTEL_MASK(high, low); \
59 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
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| D | brw_vec4_generator.cpp | 749 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in generate_tcs_get_instance_id()
1070 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); in generate_tcs_create_barrier_header()
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| D | brw_lower_logical_sends.cpp | 457 brw_imm_ud(~INTEL_MASK(14, 11))); in lower_fb_read_logical_send()
884 brw_imm_ud(INTEL_MASK(31, 5))); in lower_sampler_logical_send_gfx7()
905 brw_imm_ud(INTEL_MASK(31, 5))); in lower_sampler_logical_send_gfx7()
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| D | brw_fs_nir.cpp | 2886 brw_imm_ud(INTEL_MASK(30, 24))); in nir_emit_tcs_intrinsic()
2894 brw_imm_ud(INTEL_MASK(16, 13))); in nir_emit_tcs_intrinsic()
3848 brw_imm_ud(INTEL_MASK(7, 0))); in nir_emit_cs_intrinsic()
5875 bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(7, 7))); in nir_emit_intrinsic()
5877 bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(8, 8))); in nir_emit_intrinsic()
5880 bld.AND(tmp, raw_id, brw_imm_ud(INTEL_MASK(5, 4))); in nir_emit_intrinsic()
5887 bld.AND(raw_id, raw_id, brw_imm_ud(INTEL_MASK(2, 0))); in nir_emit_intrinsic()
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| D | brw_fs_reg_allocate.cpp | 1048 brw_imm_ud(INTEL_MASK(31, 10))); in spill_reg()
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| D | brw_fs_generator.cpp | 1497 brw_imm_ud(INTEL_MASK(3, 0))); in generate_scratch_header()
1506 brw_imm_ud(INTEL_MASK(31, 10))); in generate_scratch_header()
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| D | brw_fs.cpp | 1600 brw_imm_ud(INTEL_MASK(31, 6))); in assign_curb_setup()
6663 dg2_plus ? INTEL_MASK(7, 0) : in set_tcs_invocation_id()
6664 (devinfo->ver >= 11) ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in set_tcs_invocation_id()
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| D | brw_eu_emit.c | 2785 ((ex_desc.ud | ex_desc_imm) & INTEL_MASK(15, 12)) == 0)) { in brw_send_indirect_split_message()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.0.rst | 2732 - intel/fs: Use INTEL_MASK for pushish constant address masking
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