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Searched refs:ISL_TILING_64 (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/intel/isl/
Disl_genX_helpers.h85 if (surf->tiling == ISL_TILING_64) { in isl_get_image_alignment()
Disl_emit_cpb.c45 [ISL_TILING_64] = TILE64,
Disl_drm.c53 case ISL_TILING_64: in isl_tiling_to_i915_tiling()
Disl_gfx12.c115 if (tiling == ISL_TILING_64) { in isl_gfx125_choose_image_alignment_el()
Disl_emit_depth_stencil.c64 [ISL_TILING_64] = TILE64,
Disl.c439 case ISL_TILING_64: in isl_tiling_get_info()
673 CHOOSE(ISL_TILING_64); in isl_surf_choose_tiling()
1345 if (tile_info->tiling == ISL_TILING_64) { in isl_calc_phys_total_extent_el_gfx4_2d()
2236 surf->tiling != ISL_TILING_64) in isl_surf_supports_ccs()
2240 if (surf->samples == 1 && surf->tiling == ISL_TILING_64) in isl_surf_supports_ccs()
2498 info->surf->tiling == ISL_TILING_64); in isl_emit_cpb_control_s()
Disl.h581 ISL_TILING_64, /**< 64K tiling.*/ enumerator
599 #define ISL_TILING_64_BIT (1u << ISL_TILING_64)
Disl_surface_state.c49 [ISL_TILING_64] = TILE64,
/third_party/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h2332 case ISL_TILING_64: in xy_bcb_tiling()