1 /*
2 * Copyright 2020 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41
42 #if GFX_VERx10 >= 125
43 static const uint8_t isl_encode_tiling[] = {
44 [ISL_TILING_4] = TILE4,
45 [ISL_TILING_64] = TILE64,
46 };
47 #endif
48
49 void
isl_genX(emit_cpb_control_s)50 isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch,
51 const struct isl_cpb_emit_info *restrict info)
52 {
53 #if GFX_VERx10 >= 125
54 struct GENX(3DSTATE_CPSIZE_CONTROL_BUFFER) cpb = {
55 GENX(3DSTATE_CPSIZE_CONTROL_BUFFER_header),
56 };
57
58 if (info->surf) {
59 /* BSpec 46962 has a number of restriction on the fields of this packet
60 * like :
61 *
62 * "The Width specified by this field must be less than or equal to
63 * the surface pitch (specified in bytes via the Surface Pitch field).
64 * For cube maps, Width must be set equal to Height.
65 *
66 * 1. The Width ofthis buffer must be the same as the Width of the
67 * render target(s) (defined in SURFACE_STATE), unless Surface
68 * Type is SURFTYPE_1D or SURFTYPE_2D with Depth = 0 (non-array)
69 * and LOD = 0 (non-mip mapped).
70 *
71 * 2. Depth buffer (defined in 3DSTATE_DEPTH_BUFFER) unless either
72 * the depth buffer or this buffer surf_typeare SURFTYPE_NULL"
73 *
74 * Unfortunately APIs like Vulkan do not give guarantees that every
75 * framebuffer attachment will match in size (RT & CPB surfaces for
76 * example). But at least it gives a guarantee that all the attachments
77 * of a render pass will be at least be large enough to handle the
78 * rendered area. So here we use the CPB surface values, even if they
79 * don't strictly match the various BSpec restrictions.
80 */
81 cpb.Width = (info->surf->logical_level0_px.width * 8) - 1;
82 cpb.Height = (info->surf->logical_level0_px.height * 8) - 1;
83 cpb.Depth = info->view->array_len - 1;
84 cpb.RenderTargetViewExtent = cpb.Depth;
85
86 cpb.SurfLOD = info->view->base_level;
87 cpb.MinimumArrayElement = info->view->base_array_layer;
88 cpb.SurfaceType = SURFTYPE_2D;
89 cpb.SurfacePitch = info->surf->row_pitch_B - 1;
90 cpb.MOCS = info->mocs;
91 cpb.SurfaceQPitch = isl_surf_get_array_pitch_sa_rows(info->surf) >> 2;
92 cpb.TiledMode = isl_encode_tiling[info->surf->tiling];
93 cpb.SurfaceBaseAddress = info->address;
94
95 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
96 * Start LOD" to 15 to prevent the hardware from trying to use them.
97 */
98 cpb.MipTailStartLOD = 15;
99 /* TODO:
100 *
101 * cpb.CPCBCompressionEnable is this CCS compression? Currently disabled
102 * in isl_surf_supports_ccs() for CPB buffers.
103 */
104 } else {
105 cpb.SurfaceType = SURFTYPE_NULL;
106 cpb.TiledMode = TILE64;
107 }
108
109 /* Pack everything into the batch */
110 uint32_t *dw = batch;
111 GENX(3DSTATE_CPSIZE_CONTROL_BUFFER_pack)(NULL, dw, &cpb);
112 #else
113 unreachable("Coarse pixel shading not supported");
114 #endif
115 }
116