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Searched refs:amd_gfx_level (Results 1 – 25 of 79) sorted by relevance

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/third_party/mesa3d/src/amd/common/
Dac_debug.h59 const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset);
60 void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value,
63 unsigned trace_id_count, enum amd_gfx_level gfx_level,
66 … const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback,
69 bool ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp,
72 unsigned ac_get_wave_info(enum amd_gfx_level gfx_level,
Dac_shader_util.h98 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level);
100 unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt);
104 enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim,
107 enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim,
123 unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
128 unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
Dac_nir.h86 enum amd_gfx_level gfx_level,
104 enum amd_gfx_level gfx_level,
110 enum amd_gfx_level gfx_level,
115 enum amd_gfx_level gfx_level);
Dac_shadowed_regs.h57 void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family,
62 void ac_check_shadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family,
Dac_shader_util.c92 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level) in ac_vgt_gs_mode()
116 unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt) in ac_get_tbuffer_format()
424 enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim, in ac_get_sampler_dim()
451 enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim, in ac_get_image_dim()
731 unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, in ac_compute_lshs_workgroup_size()
754 unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size, in ac_compute_esgs_workgroup_size()
Dac_rtld.h60 enum amd_gfx_level gfx_level;
87 typedef bool (*ac_rtld_get_external_symbol_cb)(enum amd_gfx_level gfx_level, void *cb_data,
Dac_debug.c70 enum amd_gfx_level gfx_level;
112 static const struct si_reg *find_register(enum amd_gfx_level gfx_level, unsigned offset) in find_register()
157 const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset) in ac_get_register_name()
164 void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value, in ac_dump_reg()
612 unsigned trace_id_count, enum amd_gfx_level gfx_level, in ac_parse_ib_chunk()
659 … const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, in ac_parse_ib()
677 bool ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp, in ac_vm_fault_occured()
815 unsigned ac_get_wave_info(enum amd_gfx_level gfx_level, in ac_get_wave_info()
Dac_surface.h463 uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level,
466 uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level,
476 bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level,
Dac_nir_lower_esgs_io_to_mem.c45 enum amd_gfx_level gfx_level;
296 enum amd_gfx_level gfx_level, in ac_nir_lower_es_outputs_to_mem()
314 enum amd_gfx_level gfx_level, in ac_nir_lower_gs_inputs_to_mem()
Dac_gpu_info.h82 enum amd_gfx_level gfx_level;
248 int ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family);
/third_party/mesa3d/src/amd/compiler/tests/
Dtest_isel.cpp63 if (!set_variant((amd_gfx_level)i))
78 PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
86 if (!set_variant((amd_gfx_level)i))
103 PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
115 if (!set_variant((amd_gfx_level)i))
129 PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
141 if (!set_variant((amd_gfx_level)i))
182 PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
Dtest_assembler.cpp30 if (!setup_cs(NULL, (amd_gfx_level)i))
44 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
63 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
92 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
124 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
151 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
179 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
204 if (!setup_cs(NULL, (amd_gfx_level)GFX10))
231 if (!setup_cs(NULL, (amd_gfx_level)i))
249 if (!setup_cs(NULL, (amd_gfx_level)i))
[all …]
Dtest_sdwa.cpp32 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
53 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
69 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
98 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
119 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
135 if (!setup_cs("v1 v1 s2", (amd_gfx_level)i))
157 … if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i, CHIP_UNKNOWN, is_signed ? "_signed" : "_unsigned"))
280 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
337 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
381 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
[all …]
Dhelpers.h73 void create_program(enum amd_gfx_level gfx_level, aco::Stage stage,
75 bool setup_cs(const char *input_spec, enum amd_gfx_level gfx_level,
107 VkDevice get_vk_device(enum amd_gfx_level gfx_level);
Dtest_optimizer.cpp31 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i))
275 if (!setup_cs("v1 s1 s2", (amd_gfx_level)i))
319 if (!setup_cs("s1 v1", (amd_gfx_level)i))
401 if (!setup_cs("v1 s1", (amd_gfx_level)i))
718 if (!setup_cs("v1", (amd_gfx_level)i))
741 if (!setup_cs("v1 v1 v1", (amd_gfx_level)i))
762 if (!setup_cs("v1 v1 s1", (amd_gfx_level)i))
890 if (!setup_cs("v1 s2", (amd_gfx_level)i, CHIP_UNKNOWN, subvariant))
1165 if (!setup_cs("v1 v2b", (amd_gfx_level)i))
1200 if (!setup_cs("v1 v2b", (amd_gfx_level)i))
[all …]
Dtest_regalloc.cpp39 for (amd_gfx_level cc = GFX8; cc <= GFX10_3; cc = (amd_gfx_level)((unsigned)cc + 1)) {
44 if (!setup_cs("v1", (amd_gfx_level)cc, CHIP_UNKNOWN, subvariant))
Dtest_to_hw_instr.cpp47 if (!setup_cs(NULL, (amd_gfx_level)i))
226 for (amd_gfx_level lvl : {GFX8, GFX9, GFX11}) {
421 for (amd_gfx_level lvl : {GFX9, GFX10, GFX11}) {
604 for (amd_gfx_level lvl : {GFX7, GFX8, GFX9, GFX11}) {
703 for (amd_gfx_level lvl : {GFX7, GFX8, GFX9, GFX11}) {
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_nir_lower_alu.cpp76 LowerSinCos(amd_gfx_level gxf_level): m_gxf_level(gxf_level){} in LowerSinCos()
80 amd_gfx_level m_gxf_level;
132 bool r600_nir_lower_trigen(nir_shader *shader, amd_gfx_level gfx_level) in r600_nir_lower_trigen()
Dsfn_nir_lower_alu.h36 bool r600_nir_lower_trigen(nir_shader *shader, enum amd_gfx_level gfx_level);
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader_args.h87 void radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key,
92 void radv_declare_ps_epilog_args(enum amd_gfx_level gfx_level, const struct radv_ps_epilog_key *key,
Dradv_shader.h132 enum amd_gfx_level gfx_level;
545 void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level,
625 calculate_tess_lds_size(enum amd_gfx_level gfx_level, unsigned tcs_num_input_vertices, in calculate_tess_lds_size()
657 enum amd_gfx_level gfx_level, enum radeon_family family) in get_tcs_num_patches()
Dradv_debug.c154 radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) in radv_dump_buffer_descriptor()
162 radv_dump_image_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) in radv_dump_image_descriptor()
177 radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) in radv_dump_sampler_descriptor()
186 radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, in radv_dump_combined_image_sampler_descriptor()
197 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; in radv_dump_descriptor_set()
372 enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level; in radv_dump_annotated_shaders()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp110 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG>
408 template<amd_gfx_level GFX_VERSION>
483 template<amd_gfx_level GFX_VERSION>
500 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1067 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
1149 template<amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS_…
1201 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
1271 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS,
1310 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG> ALWAYS…
1368 template <amd_gfx_level GFX_VERSION, si_has_tess HAS_TESS, si_has_gs HAS_GS, si_has_ngg NGG,
[all …]
/third_party/mesa3d/src/amd/compiler/
Daco_ir.cpp69 enum amd_gfx_level gfx_level, enum radeon_family family, bool wgp_mode, in init_program()
203 can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra) in can_use_SDWA()
269 convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr) in convert_to_SDWA()
403 can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx) in can_use_opsel()
446 instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op) in instr_is_16bit()
815 wait_imm::wait_imm(enum amd_gfx_level gfx_level, uint16_t packed) : vs(unset_counter) in wait_imm()
829 wait_imm::pack(enum amd_gfx_level gfx_level) const in pack()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_asm.h257 enum amd_gfx_level gfx_level;
299 enum amd_gfx_level gfx_level,

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