| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_eu_validate.c | 109 const struct intel_device_info *devinfo = isa->devinfo; in inst_is_split_send() local
111 if (devinfo->ver >= 12) { in inst_is_split_send()
139 const struct intel_device_info *devinfo = isa->devinfo; in inst_dst_type() local
141 return (devinfo->ver < 12 || !inst_is_send(isa, inst)) ? in inst_dst_type()
142 brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D; in inst_dst_type()
148 const struct intel_device_info *devinfo = isa->devinfo; in inst_is_raw_move() local
151 unsigned src_type = signed_type(brw_inst_src0_type(devinfo, inst)); in inst_is_raw_move()
153 if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) { in inst_is_raw_move()
155 if (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_VF || in inst_is_raw_move()
156 brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UV || in inst_is_raw_move()
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| D | brw_disasm.c | 36 brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode) in brw_has_jip() argument
38 if (devinfo->ver < 6) in brw_has_jip()
51 brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode) in brw_has_uip() argument
53 if (devinfo->ver < 6) in brw_has_uip()
56 return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) || in brw_has_uip()
57 (devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) || in brw_has_uip()
64 has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode) in has_branch_ctrl() argument
66 if (devinfo->ver < 8) in has_branch_ctrl()
93 is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode) in is_split_send() argument
95 if (devinfo->ver >= 12) in is_split_send()
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| D | brw_eu_emit.c | 50 const struct intel_device_info *devinfo = p->devinfo; in gfx6_resolve_implied_move() local
51 if (devinfo->ver < 6) in gfx6_resolve_implied_move()
58 assert(devinfo->ver < 12); in gfx6_resolve_implied_move()
81 const struct intel_device_info *devinfo = p->devinfo; in gfx7_convert_mrf_to_grf() local
82 if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) { in gfx7_convert_mrf_to_grf()
91 const struct intel_device_info *devinfo = p->devinfo; in brw_set_dest() local
94 assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); in brw_set_dest()
112 if (devinfo->ver >= 12 && in brw_set_dest()
119 assert(brw_inst_exec_size(devinfo, inst) == BRW_EXECUTE_1 || in brw_set_dest()
123 brw_inst_set_dst_reg_file(devinfo, inst, dest.file); in brw_set_dest()
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| D | brw_inst.h | 59 brw_inst_set_##name(const struct intel_device_info *devinfo, \
63 if (devinfo->ver >= 12) \
69 brw_inst_##name(const struct intel_device_info *devinfo, \
73 if (devinfo->ver >= 12) \
87 if (devinfo->ver >= 12) { \
89 } else if (devinfo->ver >= 8) { \
91 } else if (devinfo->ver >= 7) { \
93 } else if (devinfo->ver >= 6) { \
95 } else if (devinfo->ver >= 5) { \
97 } else if (devinfo->verx10 >= 45) { \
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| D | brw_eu.h | 117 const struct intel_device_info *devinfo; member
165 void brw_inst_set_compression(const struct intel_device_info *devinfo,
168 void brw_inst_set_group(const struct intel_device_info *devinfo,
180 bool brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode);
181 bool brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode);
296 brw_message_desc(const struct intel_device_info *devinfo, in ALU2()
301 if (devinfo->ver >= 5) { in ALU2()
312 brw_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc) in brw_message_desc_mlen() argument
314 if (devinfo->ver >= 5) in brw_message_desc_mlen()
321 brw_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc) in brw_message_desc_rlen() argument
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| D | brw_eu_compact.c | 1083 const struct intel_device_info *devinfo = c->isa->devinfo; in set_control_index() local
1086 if (devinfo->ver >= 12) { in set_control_index()
1097 } else if (devinfo->ver >= 8) { in set_control_index()
1110 if (devinfo->ver == 7) in set_control_index()
1116 brw_compact_inst_set_control_index(devinfo, dst, i); in set_control_index()
1128 const struct intel_device_info *devinfo = c->isa->devinfo; in set_datatype_index() local
1131 if (devinfo->ver >= 12) { in set_datatype_index()
1148 } else if (devinfo->ver >= 8) { in set_datatype_index()
1159 brw_compact_inst_set_datatype_index(devinfo, dst, i); in set_datatype_index()
1171 const struct intel_device_info *devinfo = c->isa->devinfo; in set_subreg_index() local
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| D | test_eu_validate.cpp | 62 struct intel_device_info devinfo; member in validation_test
68 memset(&devinfo, 0, sizeof(devinfo)); in validation_test()
81 intel_get_device_info_from_pci_id(devid, &devinfo); in SetUp()
83 brw_init_isa_info(&isa, &devinfo); in SetUp()
158 if (devinfo.ver >= 6) { in TEST_P()
169 if (devinfo.ver >= 6) { in TEST_P()
188 if (devinfo.ver == 7) { in TEST_P()
215 brw_inst_set_exec_size(&devinfo, last_inst, test_case[i].exec_size); in TEST_P()
216 … brw_inst_set_src0_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); in TEST_P()
217 … brw_inst_set_dst_file_type(&devinfo, last_inst, BRW_GENERAL_REGISTER_FILE, BRW_REGISTER_TYPE_W); in TEST_P()
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| D | brw_ir_performance.cpp | 124 isa(isa), devinfo(isa->devinfo), op(inst->opcode), in instruction_info()
155 isa(isa), devinfo(isa->devinfo), op(inst->opcode), in instruction_info()
179 const struct intel_device_info *devinfo; member
295 const struct intel_device_info *devinfo = info.devinfo; in instruction_desc() local
363 if (devinfo->ver >= 11) { in instruction_desc()
366 } else if (devinfo->ver >= 8) { in instruction_desc()
373 } else if (devinfo->verx10 >= 75) { in instruction_desc()
388 if (devinfo->ver >= 11) { in instruction_desc()
391 } else if (devinfo->ver >= 8) { in instruction_desc()
398 } else if (devinfo->verx10 >= 75) { in instruction_desc()
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| D | brw_fs_generator.cpp | 58 brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, in brw_reg_from_fs_reg() argument
65 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); in brw_reg_from_fs_reg()
108 if (devinfo->verx10 == 70) { in brw_reg_from_fs_reg()
175 if (devinfo->verx10 == 70 && in brw_reg_from_fs_reg()
194 devinfo(compiler->devinfo), in fs_generator()
231 int scale = brw_jump_scale(p->devinfo); in patch_halt_jumps()
233 if (devinfo->ver >= 6) { in patch_halt_jumps()
246 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale); in patch_halt_jumps()
247 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale); in patch_halt_jumps()
256 if (devinfo->ver >= 6) { in patch_halt_jumps()
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| D | brw_compiler.c | 105 brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo) in brw_compiler_create() argument
109 compiler->devinfo = devinfo; in brw_compiler_create()
111 brw_init_isa_info(&compiler->isa, devinfo); in brw_compiler_create()
114 if (devinfo->ver < 8) in brw_compiler_create()
120 devinfo->ver >= 12 || in brw_compiler_create()
121 (devinfo->ver >= 9 && INTEL_DEBUG(DEBUG_TCS_EIGHT_PATCH)); in brw_compiler_create()
128 compiler->scalar_stage[i] = devinfo->ver >= 8 || in brw_compiler_create()
153 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64)) in brw_compiler_create()
155 if (!devinfo->has_64bit_int) in brw_compiler_create()
162 if (devinfo->ver < 8 || devinfo->ver > 9) in brw_compiler_create()
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| D | brw_vec4_generator.cpp | 117 const struct intel_device_info *devinfo = p->devinfo; in generate_tex() local
120 if (devinfo->ver >= 5) { in generate_tex()
133 assert(devinfo->verx10 == 75); in generate_tex()
143 if (devinfo->ver >= 7) in generate_tex()
149 assert(devinfo->ver >= 7); in generate_tex()
214 if (devinfo->ver < 6 && !inst->offset) { in generate_tex()
322 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) | in generate_tex()
323 brw_sampler_desc(devinfo, in generate_tex()
433 assert(p->devinfo->ver >= 7 && in generate_gs_set_write_offset()
733 const struct intel_device_info *devinfo = p->devinfo; in generate_tcs_get_instance_id() local
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| D | brw_fs_lower_regioning.cpp | 127 required_exec_type(const intel_device_info *devinfo, const fs_inst *inst) in required_exec_type() argument
131 devinfo->has_64bit_float : devinfo->has_64bit_int; in required_exec_type()
148 if ((!has_64bit || devinfo->verx10 == 70 || in required_exec_type()
149 devinfo->platform == INTEL_PLATFORM_CHV || in required_exec_type()
150 intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4) in required_exec_type()
152 else if (has_dst_aligned_region_restriction(devinfo, inst)) in required_exec_type()
164 if (has_dst_aligned_region_restriction(devinfo, inst)) in required_exec_type()
179 if ((!has_64bit || devinfo->platform == INTEL_PLATFORM_CHV || in required_exec_type()
180 intel_device_info_is_9lp(devinfo)) && type_sz(t) > 4) in required_exec_type()
187 if (((devinfo->verx10 == 70 || in required_exec_type()
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| /third_party/mesa3d/src/intel/dev/ |
| D | intel_device_info.c | 1097 reset_masks(struct intel_device_info *devinfo) in reset_masks() argument
1099 devinfo->subslice_slice_stride = 0; in reset_masks()
1100 devinfo->eu_subslice_stride = 0; in reset_masks()
1101 devinfo->eu_slice_stride = 0; in reset_masks()
1103 devinfo->num_slices = 0; in reset_masks()
1104 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices)); in reset_masks()
1106 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks)); in reset_masks()
1107 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks)); in reset_masks()
1108 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks)); in reset_masks()
1109 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices)); in reset_masks()
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| D | intel_dev_info.c | 52 print_regions_info(const struct intel_device_info *devinfo) in print_regions_info() argument
54 if (devinfo->mem.sram.mappable.size > 0 || in print_regions_info()
55 devinfo->mem.sram.unmappable.size > 0) { in print_regions_info()
57 if (devinfo->mem.use_class_instance) { in print_regions_info()
59 devinfo->mem.sram.mem_class, devinfo->mem.sram.mem_instance); in print_regions_info()
62 devinfo->mem.sram.mappable.size); in print_regions_info()
64 devinfo->mem.sram.mappable.free); in print_regions_info()
65 if (devinfo->mem.sram.unmappable.size > 0) { in print_regions_info()
67 devinfo->mem.sram.unmappable.size); in print_regions_info()
69 devinfo->mem.sram.unmappable.free); in print_regions_info()
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| D | intel_device_info_test.h | 8 verify_device_info(const struct intel_device_info *devinfo) in verify_device_info() argument
10 assert(devinfo->ver != 0); in verify_device_info()
11 assert((devinfo->verx10 / 10) == devinfo->ver); in verify_device_info()
12 assert(devinfo->max_eus_per_subslice != 0); in verify_device_info()
13 assert(devinfo->num_thread_per_eu != 0); in verify_device_info()
14 assert(devinfo->timestamp_frequency != 0); in verify_device_info()
15 assert(devinfo->cs_prefetch_size > 0); in verify_device_info()
17 assert(devinfo->ver < 7 || devinfo->max_constant_urb_size_kb > 0); in verify_device_info()
18 assert(devinfo->ver < 8 || devinfo->max_threads_per_psd > 0); in verify_device_info()
20 assert(devinfo->platform >= 1); in verify_device_info()
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| D | intel_device_info.h | 86 #define intel_device_info_is_dg2(devinfo) \ argument
87 intel_platform_in_range((devinfo)->platform, DG2)
424 #define intel_device_info_is_9lp(devinfo) \ argument
425 (GFX_VER == 9 && ((devinfo)->platform == INTEL_PLATFORM_BXT || \
426 (devinfo)->platform == INTEL_PLATFORM_GLK))
430 #define intel_device_info_is_9lp(devinfo) \ argument
431 ((devinfo)->platform == INTEL_PLATFORM_BXT || \
432 (devinfo)->platform == INTEL_PLATFORM_GLK)
437 intel_device_info_slice_available(const struct intel_device_info *devinfo, in intel_device_info_slice_available() argument
441 return (devinfo->slice_masks & (1U << slice)) != 0; in intel_device_info_slice_available()
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| /third_party/mesa3d/src/gallium/drivers/crocus/ |
| D | crocus_screen.c | 60 #define genX_call(devinfo, func, ...) \ argument
61 switch ((devinfo)->verx10) { \
104 intel_uuid_compute_device_id((uint8_t *)uuid, &screen->devinfo, PIPE_UUID_SIZE); in crocus_get_device_uuid()
111 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_get_driver_uuid() local
113 intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE); in crocus_get_driver_uuid()
120 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_get_name() local
123 snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name); in crocus_get_name()
139 const struct intel_device_info *devinfo = &screen->devinfo; in crocus_get_param() local
205 return devinfo->ver == 8; in crocus_get_param()
207 return devinfo->ver <= 5; in crocus_get_param()
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| D | crocus_pipe_control.c | 62 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_pipe_control_flush() local
64 if (devinfo->ver >= 6 && in crocus_emit_pipe_control_flush()
118 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_depth_stall_flushes() local
120 assert(devinfo->ver >= 6); in crocus_emit_depth_stall_flushes()
127 if (devinfo->ver >= 8) in crocus_emit_depth_stall_flushes()
161 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_end_of_pipe_sync() local
163 if (devinfo->ver >= 6) { in crocus_emit_end_of_pipe_sync()
192 if (batch->screen->devinfo.platform == INTEL_PLATFORM_HSW) { in crocus_emit_end_of_pipe_sync()
213 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_mi_flush() local
215 if (devinfo->ver >= 6) { in crocus_emit_mi_flush()
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| /third_party/mesa3d/src/intel/common/ |
| D | intel_l3_config.c | 163 get_l3_list(const struct intel_device_info *devinfo) in get_l3_list() argument
165 switch (devinfo->ver) { in get_l3_list()
167 return (devinfo->platform == INTEL_PLATFORM_BYT ? &vlv_l3_list : &ivb_l3_list); in get_l3_list()
170 return (devinfo->platform == INTEL_PLATFORM_CHV ? &chv_l3_list : &bdw_l3_list); in get_l3_list()
173 if (devinfo->l3_banks == 1) in get_l3_list()
181 if (devinfo->platform == INTEL_PLATFORM_DG1 || in get_l3_list()
182 intel_device_info_is_dg2(devinfo)) in get_l3_list()
260 intel_get_default_l3_weights(const struct intel_device_info *devinfo, in intel_get_default_l3_weights() argument
265 w.w[INTEL_L3P_SLM] = devinfo->ver < 11 && needs_slm; in intel_get_default_l3_weights()
268 if (devinfo->ver >= 8) { in intel_get_default_l3_weights()
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| D | intel_uuid.c | 30 const struct intel_device_info *devinfo, in intel_uuid_compute_device_id() argument
44 _mesa_sha1_update(&sha1_ctx, &devinfo->pci_domain, in intel_uuid_compute_device_id()
45 sizeof(devinfo->pci_domain)); in intel_uuid_compute_device_id()
46 _mesa_sha1_update(&sha1_ctx, &devinfo->pci_bus, in intel_uuid_compute_device_id()
47 sizeof(devinfo->pci_bus)); in intel_uuid_compute_device_id()
48 _mesa_sha1_update(&sha1_ctx, &devinfo->pci_dev, in intel_uuid_compute_device_id()
49 sizeof(devinfo->pci_dev)); in intel_uuid_compute_device_id()
50 _mesa_sha1_update(&sha1_ctx, &devinfo->pci_func, in intel_uuid_compute_device_id()
51 sizeof(devinfo->pci_func)); in intel_uuid_compute_device_id()
53 _mesa_sha1_update(&sha1_ctx, &devinfo->pci_device_id, in intel_uuid_compute_device_id()
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| /third_party/mesa3d/src/gallium/drivers/v3d/ |
| D | v3d_formats.c | 45 get_format(const struct v3d_device_info *devinfo, enum pipe_format f) in get_format() argument
47 if (devinfo->ver >= 41) in get_format()
54 v3d_rt_format_supported(const struct v3d_device_info *devinfo, in v3d_rt_format_supported() argument
57 const struct v3d_format *vf = get_format(devinfo, f); in v3d_rt_format_supported()
66 v3d_get_rt_format(const struct v3d_device_info *devinfo, enum pipe_format f) in v3d_get_rt_format() argument
68 const struct v3d_format *vf = get_format(devinfo, f); in v3d_get_rt_format()
77 v3d_tex_format_supported(const struct v3d_device_info *devinfo, in v3d_tex_format_supported() argument
80 const struct v3d_format *vf = get_format(devinfo, f); in v3d_tex_format_supported()
86 v3d_get_tex_format(const struct v3d_device_info *devinfo, enum pipe_format f) in v3d_get_tex_format() argument
88 const struct v3d_format *vf = get_format(devinfo, f); in v3d_get_tex_format()
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 291 brw_inst_set_access_mode(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
293 brw_inst_set_mask_control(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
295 brw_inst_set_thread_control(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
297 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
299 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
301 brw_inst_set_debug_control(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
303 if (p->devinfo->ver >= 6) in i965_asm_set_instruction_options()
304 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
306 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst, in i965_asm_set_instruction_options()
315 if (p->devinfo->ver <= 6) { in i965_asm_set_dst_nr()
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| D | i965_asm.c | 107 struct intel_device_info *devinfo; in i965_disasm_init() local
109 devinfo = malloc(sizeof *devinfo); in i965_disasm_init()
110 if (devinfo == NULL) in i965_disasm_init()
113 if (!intel_get_device_info_from_pci_id(pci_id, devinfo)) { in i965_disasm_init()
116 free(devinfo); in i965_disasm_init()
120 return devinfo; in i965_disasm_init()
126 if (p->devinfo->ver < 6) { in i965_postprocess_labels()
135 const unsigned to_bytes_scale = brw_jump_scale(p->devinfo); in i965_postprocess_labels()
153 if (p->devinfo->ver >= 7) { in i965_postprocess_labels()
154 brw_inst_set_jip(p->devinfo, inst, relative_offset); in i965_postprocess_labels()
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| /third_party/mesa3d/src/intel/isl/ |
| D | isl_storage_image.c | 79 isl_lower_storage_image_format(const struct intel_device_info *devinfo, in isl_lower_storage_image_format() argument
110 return (devinfo->ver >= 9 ? format : in isl_lower_storage_image_format()
111 devinfo->verx10 >= 75 ? in isl_lower_storage_image_format()
127 return (devinfo->ver >= 9 ? format : in isl_lower_storage_image_format()
128 devinfo->verx10 >= 75 ? in isl_lower_storage_image_format()
134 return (devinfo->ver >= 9 ? format : in isl_lower_storage_image_format()
135 devinfo->verx10 >= 75 ? in isl_lower_storage_image_format()
140 return (devinfo->ver >= 9 ? format : in isl_lower_storage_image_format()
141 devinfo->verx10 >= 75 ? in isl_lower_storage_image_format()
147 return (devinfo->ver >= 9 ? format : ISL_FORMAT_R16_UINT); in isl_lower_storage_image_format()
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| /third_party/mesa3d/src/intel/perf/ |
| D | intel_perf.c | 175 const struct intel_device_info *devinfo, in register_oa_config() argument
190 const struct intel_device_info *devinfo) in enumerate_sysfs_metrics() argument
225 register_oa_config(perf, devinfo, in enumerate_sysfs_metrics()
236 const struct intel_device_info *devinfo) in add_all_metrics() argument
240 register_oa_config(perf, devinfo, query, 0); in add_all_metrics()
323 const struct intel_device_info *devinfo) in init_oa_configs() argument
331 register_oa_config(perf, devinfo, query, config_id); in init_oa_configs()
342 register_oa_config(perf, devinfo, query, ret); in init_oa_configs()
350 const struct intel_device_info *devinfo = &perf->devinfo; in compute_topology_builtins() local
352 perf->sys_vars.slice_mask = devinfo->slice_masks; in compute_topology_builtins()
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