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Searched refs:hevc_deblock (Results 1 – 8 of 8) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dradeon_vcn_enc_2_0.c181 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && in radeon_enc_slice_header_hevc()
182 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled || in radeon_enc_slice_header_hevc()
195 … radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_slice_header_hevc()
220 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_loop_filter_hevc()
221 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_loop_filter_hevc()
222 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_loop_filter_hevc()
223 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_loop_filter_hevc()
224 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_loop_filter_hevc()
225 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_loop_filter_hevc()
361 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
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Dradeon_vcn_enc_3_0.c140 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
141 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
147 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
150 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
152 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
153 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
154 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
Dradeon_uvd_enc_1_1.c358 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = in radeon_uvd_enc_deblocking_filter_hevc()
360 enc->enc_pic.hevc_deblock.deblocking_filter_disabled = in radeon_uvd_enc_deblocking_filter_hevc()
362 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_uvd_enc_deblocking_filter_hevc()
363 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; in radeon_uvd_enc_deblocking_filter_hevc()
364 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; in radeon_uvd_enc_deblocking_filter_hevc()
365 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; in radeon_uvd_enc_deblocking_filter_hevc()
368 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_uvd_enc_deblocking_filter_hevc()
369 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_uvd_enc_deblocking_filter_hevc()
370 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_uvd_enc_deblocking_filter_hevc()
371 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_uvd_enc_deblocking_filter_hevc()
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Dradeon_vcn_enc_1_2.c242 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_deblocking_filter_hevc()
243 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_deblocking_filter_hevc()
244 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_hevc()
245 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_deblocking_filter_hevc()
246 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_hevc()
247 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_hevc()
671 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
672 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
678 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
681 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
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Dradeon_vcn_enc.c173 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = in radeon_vcn_enc_get_param()
175 enc->enc_pic.hevc_deblock.deblocking_filter_disabled = in radeon_vcn_enc_get_param()
177 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_vcn_enc_get_param()
178 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2; in radeon_vcn_enc_get_param()
179 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset; in radeon_vcn_enc_get_param()
180 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset; in radeon_vcn_enc_get_param()
Dradeon_uvd_enc.h377 ruvd_enc_hevc_deblocking_filter_t hevc_deblock; member
Dradeon_vcn_enc.h491 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; member
/third_party/ffmpeg/libavcodec/x86/
DMakefile170 x86/hevc_deblock.o \