1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "radeon_temporal.h"
32 #include "si_pipe.h"
33 #include "util/u_video.h"
34
35 #include <stdio.h>
36
37 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
38 #define RENCODE_FW_INTERFACE_MINOR_VERSION 9
39
40 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
41 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
42 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
43 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
44 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
45 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
46 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
47 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
48 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
49 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
50 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
51 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
52 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
53 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
54 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
55 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
56
57 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
58 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
59 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
60
61 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
62 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
63 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
64 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
65
radeon_enc_session_info(struct radeon_encoder * enc)66 static void radeon_enc_session_info(struct radeon_encoder *enc)
67 {
68 RADEON_ENC_BEGIN(enc->cmd.session_info);
69 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
70 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
71 RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
72 RADEON_ENC_END();
73 }
74
radeon_enc_task_info(struct radeon_encoder * enc,bool need_feedback)75 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
76 {
77 enc->enc_pic.task_info.task_id++;
78
79 if (need_feedback)
80 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
81 else
82 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
83
84 RADEON_ENC_BEGIN(enc->cmd.task_info);
85 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
86 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
87 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
88 RADEON_ENC_END();
89 }
90
radeon_enc_session_init(struct radeon_encoder * enc)91 static void radeon_enc_session_init(struct radeon_encoder *enc)
92 {
93 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
94 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
95 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
96 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
97 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
98 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
99 }
100 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
101 enc->enc_pic.session_init.padding_width =
102 enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
103 enc->enc_pic.session_init.padding_height =
104 enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
105 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
106 enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
107 enc->enc_pic.session_init.display_remote = 0;
108
109 RADEON_ENC_BEGIN(enc->cmd.session_init);
110 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
111 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
112 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
113 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
114 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
115 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
116 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
117 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
118 RADEON_ENC_END();
119 }
120
radeon_enc_layer_control(struct radeon_encoder * enc)121 static void radeon_enc_layer_control(struct radeon_encoder *enc)
122 {
123 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers;
124 enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers;
125
126 RADEON_ENC_BEGIN(enc->cmd.layer_control);
127 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
128 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
129 RADEON_ENC_END();
130 }
131
radeon_enc_layer_select(struct radeon_encoder * enc)132 static void radeon_enc_layer_select(struct radeon_encoder *enc)
133 {
134 enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id;
135
136 RADEON_ENC_BEGIN(enc->cmd.layer_select);
137 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
138 RADEON_ENC_END();
139 }
140
radeon_enc_slice_control(struct radeon_encoder * enc)141 static void radeon_enc_slice_control(struct radeon_encoder *enc)
142 {
143 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
144 enc->enc_pic.slice_ctrl.num_mbs_per_slice =
145 align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
146
147 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
148 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
149 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
150 RADEON_ENC_END();
151 }
152
radeon_enc_slice_control_hevc(struct radeon_encoder * enc)153 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
154 {
155 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
156 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
157 align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
158 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
159 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
160
161 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
162 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
163 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
164 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
165 RADEON_ENC_END();
166 }
167
radeon_enc_spec_misc(struct radeon_encoder * enc)168 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
169 {
170 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
171 enc->enc_pic.spec_misc.half_pel_enabled = 1;
172 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
173 enc->enc_pic.spec_misc.level_idc = enc->base.level;
174
175 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
176 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
177 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
178 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
179 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
180 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
181 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
182 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
183 RADEON_ENC_END();
184 }
185
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)186 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
187 {
188 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
189 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
190 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
191 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
192 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
193 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
194 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
195 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
196 RADEON_ENC_END();
197 }
198
radeon_enc_rc_session_init(struct radeon_encoder * enc)199 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
200 {
201 RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
202 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
203 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
204 RADEON_ENC_END();
205 }
206
radeon_enc_rc_layer_init(struct radeon_encoder * enc)207 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
208 {
209 unsigned int i = enc->enc_pic.temporal_id;
210 RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
211 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate);
212 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate);
213 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num);
214 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den);
215 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size);
216 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture);
217 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer);
218 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional);
219 RADEON_ENC_END();
220 }
221
radeon_enc_deblocking_filter_h264(struct radeon_encoder * enc)222 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
223 {
224 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
225 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
226 enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
227 enc->enc_pic.h264_deblock.cb_qp_offset = 0;
228 enc->enc_pic.h264_deblock.cr_qp_offset = 0;
229
230 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
231 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
232 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
233 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
234 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
235 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
236 RADEON_ENC_END();
237 }
238
radeon_enc_deblocking_filter_hevc(struct radeon_encoder * enc)239 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
240 {
241 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
242 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
243 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
244 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
245 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
246 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
247 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
248 RADEON_ENC_END();
249 }
250
radeon_enc_quality_params(struct radeon_encoder * enc)251 static void radeon_enc_quality_params(struct radeon_encoder *enc)
252 {
253 enc->enc_pic.quality_params.vbaq_mode = 0;
254 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
255 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
256 enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
257
258 RADEON_ENC_BEGIN(enc->cmd.quality_params);
259 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
260 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
261 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
262 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
263 RADEON_ENC_END();
264 }
265
radeon_enc_nalu_sps(struct radeon_encoder * enc)266 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
267 {
268 RADEON_ENC_BEGIN(enc->cmd.nalu);
269 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
270 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
271 radeon_enc_reset(enc);
272 radeon_enc_set_emulation_prevention(enc, false);
273 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
274 radeon_enc_code_fixed_bits(enc, 0x67, 8);
275 radeon_enc_byte_align(enc);
276 radeon_enc_set_emulation_prevention(enc, true);
277 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
278 radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
279 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
280 radeon_enc_code_ue(enc, 0x0);
281
282 if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
283 enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
284 enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 ||
285 enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 ||
286 enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
287 radeon_enc_code_ue(enc, 0x1);
288 radeon_enc_code_ue(enc, 0x0);
289 radeon_enc_code_ue(enc, 0x0);
290 radeon_enc_code_fixed_bits(enc, 0x0, 2);
291 }
292
293 radeon_enc_code_ue(enc, 1);
294 radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
295
296 if (enc->enc_pic.pic_order_cnt_type == 0)
297 radeon_enc_code_ue(enc, 1);
298
299 radeon_enc_code_ue(enc, enc->base.max_references);
300 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
301 1);
302 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
303 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
304 bool progressive_only = true;
305 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
306
307 if (!progressive_only)
308 radeon_enc_code_fixed_bits(enc, 0x0, 1);
309
310 radeon_enc_code_fixed_bits(enc, 0x1, 1);
311
312 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
313 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
314 radeon_enc_code_fixed_bits(enc, 0x1, 1);
315 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
316 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
317 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
318 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
319 } else
320 radeon_enc_code_fixed_bits(enc, 0x0, 1);
321
322 radeon_enc_code_fixed_bits(enc, 0x1, 1);
323 radeon_enc_code_fixed_bits(enc, 0x0, 1);
324 radeon_enc_code_fixed_bits(enc, 0x0, 1);
325 radeon_enc_code_fixed_bits(enc, 0x0, 1);
326 radeon_enc_code_fixed_bits(enc, 0x0, 1);
327 radeon_enc_code_fixed_bits(enc, 0x0, 1);
328 radeon_enc_code_fixed_bits(enc, 0x0, 1);
329 radeon_enc_code_fixed_bits(enc, 0x0, 1);
330 radeon_enc_code_fixed_bits(enc, 0x0, 1);
331 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* bitstream_restriction_flag */
332 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
333 radeon_enc_code_ue(enc, 0x0);
334 radeon_enc_code_ue(enc, 0x0);
335 radeon_enc_code_ue(enc, 16);
336 radeon_enc_code_ue(enc, 16);
337 radeon_enc_code_ue(enc, 0x0);
338 radeon_enc_code_ue(enc, enc->base.max_references); /* max_dec_frame_buffering */
339
340 radeon_enc_code_fixed_bits(enc, 0x1, 1);
341
342 radeon_enc_byte_align(enc);
343 radeon_enc_flush_headers(enc);
344 *size_in_bytes = (enc->bits_output + 7) / 8;
345 RADEON_ENC_END();
346 }
347
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)348 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
349 {
350 RADEON_ENC_BEGIN(enc->cmd.nalu);
351 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
352 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
353 int i;
354
355 radeon_enc_reset(enc);
356 radeon_enc_set_emulation_prevention(enc, false);
357 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
358 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
359 radeon_enc_byte_align(enc);
360 radeon_enc_set_emulation_prevention(enc, true);
361 radeon_enc_code_fixed_bits(enc, 0x0, 4);
362 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
363 radeon_enc_code_fixed_bits(enc, 0x1, 1);
364 radeon_enc_code_fixed_bits(enc, 0x0, 2);
365 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
366 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
367 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
368 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
369 radeon_enc_code_fixed_bits(enc, 0x0, 16);
370 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
371
372 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
373 radeon_enc_code_fixed_bits(enc, 0x0, 2);
374
375 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
376 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
377 radeon_enc_code_fixed_bits(enc, 0x0, 2);
378 }
379
380 radeon_enc_code_ue(enc, 0x0);
381 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
382 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
383 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
384
385 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) ||
386 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) {
387 radeon_enc_code_fixed_bits(enc, 0x1, 1);
388 radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
389 radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
390 radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
391 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
392 } else if (enc->enc_pic.session_init.padding_width != 0 ||
393 enc->enc_pic.session_init.padding_height != 0) {
394 radeon_enc_code_fixed_bits(enc, 0x1, 1);
395 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
396 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
397 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
398 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
399 } else
400 radeon_enc_code_fixed_bits(enc, 0x0, 1);
401
402 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
403 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
404 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
405 radeon_enc_code_fixed_bits(enc, 0x0, 1);
406 radeon_enc_code_ue(enc, 1);
407 radeon_enc_code_ue(enc, 0x0);
408 radeon_enc_code_ue(enc, 0x0);
409 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
410 // Only support CTBSize 64
411 radeon_enc_code_ue(enc,
412 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
413 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
414 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
415 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
416 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
417
418 radeon_enc_code_fixed_bits(enc, 0x0, 1);
419 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
420 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
421 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
422
423 radeon_enc_code_ue(enc, 1);
424 radeon_enc_code_ue(enc, 1);
425 radeon_enc_code_ue(enc, 0);
426 radeon_enc_code_ue(enc, 0);
427 radeon_enc_code_fixed_bits(enc, 0x1, 1);
428
429 radeon_enc_code_fixed_bits(enc, 0x0, 1);
430
431 radeon_enc_code_fixed_bits(enc, 0, 1);
432 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
433
434 radeon_enc_code_fixed_bits(enc, 0x0, 1);
435
436 radeon_enc_code_fixed_bits(enc, 0x0, 1);
437
438 radeon_enc_code_fixed_bits(enc, 0x1, 1);
439
440 radeon_enc_byte_align(enc);
441 radeon_enc_flush_headers(enc);
442 *size_in_bytes = (enc->bits_output + 7) / 8;
443 RADEON_ENC_END();
444 }
445
radeon_enc_nalu_prefix(struct radeon_encoder * enc)446 static void radeon_enc_nalu_prefix(struct radeon_encoder *enc)
447 {
448 uint nalRefIdc = enc->enc_pic.is_idr ? 3 : 0;
449
450 rvcn_temporal_layer_pattern_table_t table_info;
451 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers];
452
453 if (enc->enc_pic.pic_order_cnt == 0)
454 enc->enc_pic.temporal_layer_pattern_index = 0;
455 else if(enc->enc_pic.temporal_layer_pattern_index == (table_info.pattern_size - 1))
456 enc->enc_pic.temporal_layer_pattern_index = 1;
457 else
458 enc->enc_pic.temporal_layer_pattern_index++;
459
460 rvcn_temporal_layer_pattern_entry_t pattern =
461 table_info.pattern_table[enc->enc_pic.temporal_layer_pattern_index];
462
463 RADEON_ENC_BEGIN(enc->cmd.nalu);
464 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX);
465 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
466 radeon_enc_reset(enc);
467 radeon_enc_set_emulation_prevention(enc, false);
468 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
469 radeon_enc_code_fixed_bits(enc, 0x0, 1);
470 radeon_enc_code_fixed_bits(enc, nalRefIdc, 2);
471 radeon_enc_code_fixed_bits(enc, 14, 5);
472 radeon_enc_byte_align(enc);
473 radeon_enc_set_emulation_prevention(enc, true);
474 radeon_enc_code_fixed_bits(enc, 0x1, 1);
475 radeon_enc_code_fixed_bits(enc, enc->enc_pic.is_idr ? 0x1 : 0x0, 1);
476 radeon_enc_code_fixed_bits(enc, 0x0, 6);
477 radeon_enc_code_fixed_bits(enc, 0x1, 1);
478 radeon_enc_code_fixed_bits(enc, 0x0, 3);
479 radeon_enc_code_fixed_bits(enc, 0x0, 4);
480 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
481 radeon_enc_code_fixed_bits(enc, 0x0, 1);
482 radeon_enc_code_fixed_bits(enc, 0x0, 1);
483 radeon_enc_code_fixed_bits(enc, 0x0, 1);
484 radeon_enc_code_fixed_bits(enc, 0x3, 2);
485
486 if(nalRefIdc != 0)
487 {
488 radeon_enc_code_fixed_bits(enc, 0x0, 1);
489 radeon_enc_code_fixed_bits(enc, 0x0, 1);
490 radeon_enc_code_fixed_bits(enc, 0x1, 1);
491 radeon_enc_byte_align(enc);
492 }
493
494 radeon_enc_flush_headers(enc);
495 *size_in_bytes = (enc->bits_output + 7) / 8;
496 RADEON_ENC_END();
497 }
498
radeon_enc_nalu_sei(struct radeon_encoder * enc)499 static void radeon_enc_nalu_sei(struct radeon_encoder *enc)
500 {
501 unsigned number_of_layers;
502
503 rvcn_temporal_layer_pattern_table_t table_info;
504 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers - 1];
505 number_of_layers = table_info.pattern_size;
506
507 RADEON_ENC_BEGIN(enc->cmd.nalu);
508 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI);
509 unsigned *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
510 radeon_enc_reset(enc);
511 radeon_enc_set_emulation_prevention(enc, false);
512
513 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
514 radeon_enc_code_fixed_bits(enc, 0x6, 8);
515 radeon_enc_byte_align(enc);
516
517 radeon_enc_set_emulation_prevention(enc, true);
518
519 /* save the current position for later */
520 unsigned position = enc->cs.current.cdw;
521 unsigned shifter = enc->shifter;
522 unsigned bits_in_shifter = enc->bits_in_shifter;
523 unsigned num_zeros = enc->num_zeros;
524 unsigned byte_index = enc->byte_index;
525 unsigned bits_output = enc->bits_output;
526 bool emulation_prevention = enc->emulation_prevention;
527
528 /* temporarily fill out the payload type and size */
529 radeon_enc_code_fixed_bits(enc, 24, 8);
530 radeon_enc_code_fixed_bits(enc, 0, 8);
531
532 unsigned svc_start_offset = enc->bits_size;
533
534 radeon_enc_code_fixed_bits(enc, 0x0, 1);
535 radeon_enc_code_fixed_bits(enc, 0x0, 1);
536 radeon_enc_code_fixed_bits(enc, 0x0, 1);
537 radeon_enc_code_ue(enc, number_of_layers - 1);
538
539 for(int i = 0; i < number_of_layers; i++ )
540 {
541 rvcn_temporal_layer_pattern_entry_t pattern = table_info.pattern_table[i];
542 radeon_enc_code_ue(enc, i);
543 radeon_enc_code_fixed_bits(enc, 0x0, 6);
544 radeon_enc_code_fixed_bits(enc, 0x0, 1);
545 radeon_enc_code_fixed_bits(enc, 0x0, 3);
546 radeon_enc_code_fixed_bits(enc, 0x0, 4);
547 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
548 radeon_enc_code_fixed_bits(enc, 0x0, 1);
549 radeon_enc_code_fixed_bits(enc, 0x0, 1);
550 radeon_enc_code_fixed_bits(enc, 0x0, 1);
551 radeon_enc_code_fixed_bits(enc, 0x0, 1);
552 radeon_enc_code_fixed_bits(enc, 0x0, 1);
553 radeon_enc_code_fixed_bits(enc, 0x0, 1);
554 radeon_enc_code_fixed_bits(enc, 0x0, 1);
555 radeon_enc_code_fixed_bits(enc, 0x0, 1);
556 radeon_enc_code_fixed_bits(enc, 0x0, 1);
557 radeon_enc_code_fixed_bits(enc, 0x0, 1);
558 radeon_enc_code_fixed_bits(enc, 0x0, 1);
559 radeon_enc_code_fixed_bits(enc, 0x0, 1);
560 radeon_enc_code_fixed_bits(enc, 0x0, 1);
561 radeon_enc_code_ue(enc, 0);
562 radeon_enc_code_ue(enc, 0);
563 }
564 unsigned svc_size = ((enc->bits_size - svc_start_offset) + 7) / 8;
565 unsigned aligned = (32 - enc->bits_in_shifter) % 8;
566 if (aligned > 0)
567 radeon_enc_code_fixed_bits(enc, 0x1, 1);
568 radeon_enc_byte_align(enc);
569
570 radeon_enc_code_fixed_bits(enc, 0x1, 1);
571 radeon_enc_byte_align(enc);
572
573 /* store our current state, and go to the beginning to write the size */
574 unsigned position2 = enc->cs.current.cdw;
575 unsigned shifter2 = enc->shifter;
576 unsigned bits_in_shifter2 = enc->bits_in_shifter;
577 unsigned num_zeros2 = enc->num_zeros;
578 unsigned byte_index2 = enc->byte_index;
579 unsigned bits_output2 = enc->bits_output;
580 bool emulation_prevention2 = enc->emulation_prevention;
581
582 enc->cs.current.cdw = position;
583 enc->shifter = shifter;
584 enc->bits_in_shifter = bits_in_shifter;
585 enc->num_zeros = num_zeros;
586 enc->byte_index = byte_index;
587 enc->bits_output = bits_output;
588 enc->emulation_prevention = emulation_prevention;
589
590 radeon_enc_output_one_byte(enc, 24);
591 radeon_enc_output_one_byte(enc, svc_size);
592
593 /* restore our state */
594 enc->cs.current.cdw = position2;
595 enc->shifter = shifter2;
596 enc->bits_in_shifter = bits_in_shifter2;
597 enc->num_zeros = num_zeros2;
598 enc->byte_index = byte_index2;
599 enc->bits_output = bits_output2;
600 enc->emulation_prevention = emulation_prevention2;
601
602 radeon_enc_flush_headers(enc);
603
604 *size_in_bytes = (enc->bits_output + 7) / 8;
605 RADEON_ENC_END();
606 }
607
radeon_enc_nalu_pps(struct radeon_encoder * enc)608 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
609 {
610 RADEON_ENC_BEGIN(enc->cmd.nalu);
611 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
612 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
613 radeon_enc_reset(enc);
614 radeon_enc_set_emulation_prevention(enc, false);
615 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
616 radeon_enc_code_fixed_bits(enc, 0x68, 8);
617 radeon_enc_byte_align(enc);
618 radeon_enc_set_emulation_prevention(enc, true);
619 radeon_enc_code_ue(enc, 0x0);
620 radeon_enc_code_ue(enc, 0x0);
621 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
622 radeon_enc_code_fixed_bits(enc, 0x0, 1);
623 radeon_enc_code_ue(enc, 0x0);
624 radeon_enc_code_ue(enc, 0x0);
625 radeon_enc_code_ue(enc, 0x0);
626 radeon_enc_code_fixed_bits(enc, 0x0, 1);
627 radeon_enc_code_fixed_bits(enc, 0x0, 2);
628 radeon_enc_code_se(enc, 0x0);
629 radeon_enc_code_se(enc, 0x0);
630 radeon_enc_code_se(enc, 0x0);
631 radeon_enc_code_fixed_bits(enc, 0x1, 1);
632 radeon_enc_code_fixed_bits(enc, 0x0, 1);
633 radeon_enc_code_fixed_bits(enc, 0x0, 1);
634
635 radeon_enc_code_fixed_bits(enc, 0x1, 1);
636
637 radeon_enc_byte_align(enc);
638 radeon_enc_flush_headers(enc);
639 *size_in_bytes = (enc->bits_output + 7) / 8;
640 RADEON_ENC_END();
641 }
642
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)643 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
644 {
645 RADEON_ENC_BEGIN(enc->cmd.nalu);
646 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
647 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
648 radeon_enc_reset(enc);
649 radeon_enc_set_emulation_prevention(enc, false);
650 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
651 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
652 radeon_enc_byte_align(enc);
653 radeon_enc_set_emulation_prevention(enc, true);
654 radeon_enc_code_ue(enc, 0x0);
655 radeon_enc_code_ue(enc, 0x0);
656 radeon_enc_code_fixed_bits(enc, 0x1, 1);
657 radeon_enc_code_fixed_bits(enc, 0x0, 4);
658 radeon_enc_code_fixed_bits(enc, 0x0, 1);
659 radeon_enc_code_fixed_bits(enc, 0x1, 1);
660 radeon_enc_code_ue(enc, 0x0);
661 radeon_enc_code_ue(enc, 0x0);
662 radeon_enc_code_se(enc, 0x0);
663 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
664 radeon_enc_code_fixed_bits(enc, 0x0, 1);
665 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
666 radeon_enc_code_fixed_bits(enc, 0x0, 1);
667 else {
668 radeon_enc_code_fixed_bits(enc, 0x1, 1);
669 radeon_enc_code_ue(enc, 0x0);
670 }
671 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
672 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
673 radeon_enc_code_fixed_bits(enc, 0x0, 1);
674 radeon_enc_code_fixed_bits(enc, 0x0, 2);
675 radeon_enc_code_fixed_bits(enc, 0x0, 1);
676 radeon_enc_code_fixed_bits(enc, 0x0, 1);
677 radeon_enc_code_fixed_bits(enc, 0x0, 1);
678 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
679 radeon_enc_code_fixed_bits(enc, 0x1, 1);
680 radeon_enc_code_fixed_bits(enc, 0x0, 1);
681 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
682
683 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
684 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
685 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
686 }
687
688 radeon_enc_code_fixed_bits(enc, 0x0, 1);
689 radeon_enc_code_fixed_bits(enc, 0x0, 1);
690 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
691 radeon_enc_code_fixed_bits(enc, 0x0, 2);
692
693 radeon_enc_code_fixed_bits(enc, 0x1, 1);
694
695 radeon_enc_byte_align(enc);
696 radeon_enc_flush_headers(enc);
697 *size_in_bytes = (enc->bits_output + 7) / 8;
698 RADEON_ENC_END();
699 }
700
radeon_enc_nalu_vps(struct radeon_encoder * enc)701 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
702 {
703 RADEON_ENC_BEGIN(enc->cmd.nalu);
704 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
705 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
706 int i;
707
708 radeon_enc_reset(enc);
709 radeon_enc_set_emulation_prevention(enc, false);
710 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
711 radeon_enc_code_fixed_bits(enc, 0x4001, 16);
712 radeon_enc_byte_align(enc);
713 radeon_enc_set_emulation_prevention(enc, true);
714
715 radeon_enc_code_fixed_bits(enc, 0x0, 4);
716 radeon_enc_code_fixed_bits(enc, 0x3, 2);
717 radeon_enc_code_fixed_bits(enc, 0x0, 6);
718 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
719 radeon_enc_code_fixed_bits(enc, 0x1, 1);
720 radeon_enc_code_fixed_bits(enc, 0xffff, 16);
721 radeon_enc_code_fixed_bits(enc, 0x0, 2);
722 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
723 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
724 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
725 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
726 radeon_enc_code_fixed_bits(enc, 0x0, 16);
727 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
728
729 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
730 radeon_enc_code_fixed_bits(enc, 0x0, 2);
731
732 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
733 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
734 radeon_enc_code_fixed_bits(enc, 0x0, 2);
735 }
736
737 radeon_enc_code_fixed_bits(enc, 0x0, 1);
738 radeon_enc_code_ue(enc, 0x1);
739 radeon_enc_code_ue(enc, 0x0);
740 radeon_enc_code_ue(enc, 0x0);
741
742 radeon_enc_code_fixed_bits(enc, 0x0, 6);
743 radeon_enc_code_ue(enc, 0x0);
744 radeon_enc_code_fixed_bits(enc, 0x0, 1);
745 radeon_enc_code_fixed_bits(enc, 0x0, 1);
746
747 radeon_enc_code_fixed_bits(enc, 0x1, 1);
748
749 radeon_enc_byte_align(enc);
750 radeon_enc_flush_headers(enc);
751 *size_in_bytes = (enc->bits_output + 7) / 8;
752 RADEON_ENC_END();
753 }
754
radeon_enc_nalu_aud_hevc(struct radeon_encoder * enc)755 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
756 {
757 RADEON_ENC_BEGIN(enc->cmd.nalu);
758 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
759 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
760 radeon_enc_reset(enc);
761 radeon_enc_set_emulation_prevention(enc, false);
762 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
763 radeon_enc_code_fixed_bits(enc, 0x0, 1);
764 radeon_enc_code_fixed_bits(enc, 35, 6);
765 radeon_enc_code_fixed_bits(enc, 0x0, 6);
766 radeon_enc_code_fixed_bits(enc, 0x1, 3);
767 radeon_enc_byte_align(enc);
768 radeon_enc_set_emulation_prevention(enc, true);
769 switch (enc->enc_pic.picture_type) {
770 case PIPE_H2645_ENC_PICTURE_TYPE_I:
771 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
772 radeon_enc_code_fixed_bits(enc, 0x00, 3);
773 break;
774 case PIPE_H2645_ENC_PICTURE_TYPE_P:
775 radeon_enc_code_fixed_bits(enc, 0x01, 3);
776 break;
777 case PIPE_H2645_ENC_PICTURE_TYPE_B:
778 radeon_enc_code_fixed_bits(enc, 0x02, 3);
779 break;
780 default:
781 radeon_enc_code_fixed_bits(enc, 0x02, 3);
782 }
783
784 radeon_enc_code_fixed_bits(enc, 0x1, 1);
785
786 radeon_enc_byte_align(enc);
787 radeon_enc_flush_headers(enc);
788 *size_in_bytes = (enc->bits_output + 7) / 8;
789 RADEON_ENC_END();
790 }
791
radeon_enc_slice_header(struct radeon_encoder * enc)792 static void radeon_enc_slice_header(struct radeon_encoder *enc)
793 {
794 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
795 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
796 unsigned int inst_index = 0;
797 unsigned int cdw_start = 0;
798 unsigned int cdw_filled = 0;
799 unsigned int bits_copied = 0;
800 RADEON_ENC_BEGIN(enc->cmd.slice_header);
801 radeon_enc_reset(enc);
802 radeon_enc_set_emulation_prevention(enc, false);
803
804 cdw_start = enc->cs.current.cdw;
805 if (enc->enc_pic.is_idr)
806 radeon_enc_code_fixed_bits(enc, 0x65, 8);
807 else if (enc->enc_pic.not_referenced)
808 radeon_enc_code_fixed_bits(enc, 0x01, 8);
809 else
810 radeon_enc_code_fixed_bits(enc, 0x41, 8);
811
812 radeon_enc_flush_headers(enc);
813 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
814 num_bits[inst_index] = enc->bits_output - bits_copied;
815 bits_copied = enc->bits_output;
816 inst_index++;
817
818 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
819 inst_index++;
820
821 switch (enc->enc_pic.picture_type) {
822 case PIPE_H2645_ENC_PICTURE_TYPE_I:
823 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
824 radeon_enc_code_fixed_bits(enc, 0x08, 7);
825 break;
826 case PIPE_H2645_ENC_PICTURE_TYPE_P:
827 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
828 radeon_enc_code_fixed_bits(enc, 0x06, 5);
829 break;
830 case PIPE_H2645_ENC_PICTURE_TYPE_B:
831 radeon_enc_code_fixed_bits(enc, 0x07, 5);
832 break;
833 default:
834 radeon_enc_code_fixed_bits(enc, 0x08, 7);
835 }
836
837 radeon_enc_code_ue(enc, 0x0);
838 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
839
840 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
841 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
842 radeon_enc_code_fixed_bits(enc, 0x1, 1);
843 radeon_enc_code_fixed_bits(enc,
844 enc->enc_pic.h264_enc_params.input_picture_structure ==
845 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
846 ? 1
847 : 0,
848 1);
849 }
850
851 if (enc->enc_pic.is_idr)
852 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
853
854 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
855
856 if (enc->enc_pic.pic_order_cnt_type == 0)
857 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
858
859 /* ref_pic_list_modification() */
860 if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
861 radeon_enc_code_fixed_bits(enc, 0x0, 1);
862
863 /* list_mod_diff_pic_minus1 != 0 */
864 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
865 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
866 radeon_enc_code_ue(enc, 0x0); /* modification_of_pic_nums_idc */
867 /* abs_diff_pic_num_minus1 */
868 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
869 radeon_enc_code_ue(enc, 0x3);
870 } else
871 radeon_enc_code_fixed_bits(enc, 0x0, 1);
872 }
873
874 if (enc->enc_pic.is_idr) {
875 radeon_enc_code_fixed_bits(enc, 0x0, 1);
876 radeon_enc_code_fixed_bits(enc, 0x0, 1);
877 } else if (!enc->enc_pic.not_referenced)
878 radeon_enc_code_fixed_bits(enc, 0x0, 1);
879
880 if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
881 (enc->enc_pic.spec_misc.cabac_enable))
882 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
883
884 radeon_enc_flush_headers(enc);
885 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
886 num_bits[inst_index] = enc->bits_output - bits_copied;
887 bits_copied = enc->bits_output;
888 inst_index++;
889
890 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
891 inst_index++;
892
893 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
894
895 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
896 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
897 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
898 }
899
900 radeon_enc_flush_headers(enc);
901 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
902 num_bits[inst_index] = enc->bits_output - bits_copied;
903 bits_copied = enc->bits_output;
904 inst_index++;
905
906 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
907
908 cdw_filled = enc->cs.current.cdw - cdw_start;
909 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
910 RADEON_ENC_CS(0x00000000);
911
912 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
913 RADEON_ENC_CS(instruction[j]);
914 RADEON_ENC_CS(num_bits[j]);
915 }
916
917 RADEON_ENC_END();
918 }
919
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)920 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
921 {
922 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
923 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
924 unsigned int inst_index = 0;
925 unsigned int cdw_start = 0;
926 unsigned int cdw_filled = 0;
927 unsigned int bits_copied = 0;
928 RADEON_ENC_BEGIN(enc->cmd.slice_header);
929 radeon_enc_reset(enc);
930 radeon_enc_set_emulation_prevention(enc, false);
931
932 cdw_start = enc->cs.current.cdw;
933 radeon_enc_code_fixed_bits(enc, 0x0, 1);
934 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
935 radeon_enc_code_fixed_bits(enc, 0x0, 6);
936 radeon_enc_code_fixed_bits(enc, 0x1, 3);
937
938 radeon_enc_flush_headers(enc);
939 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
940 num_bits[inst_index] = enc->bits_output - bits_copied;
941 bits_copied = enc->bits_output;
942 inst_index++;
943
944 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
945 inst_index++;
946
947 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
948 radeon_enc_code_fixed_bits(enc, 0x0, 1);
949
950 radeon_enc_code_ue(enc, 0x0);
951
952 radeon_enc_flush_headers(enc);
953 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
954 num_bits[inst_index] = enc->bits_output - bits_copied;
955 bits_copied = enc->bits_output;
956 inst_index++;
957
958 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
959 inst_index++;
960
961 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
962 inst_index++;
963
964 switch (enc->enc_pic.picture_type) {
965 case PIPE_H2645_ENC_PICTURE_TYPE_I:
966 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
967 radeon_enc_code_ue(enc, 0x2);
968 break;
969 case PIPE_H2645_ENC_PICTURE_TYPE_P:
970 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
971 radeon_enc_code_ue(enc, 0x1);
972 break;
973 case PIPE_H2645_ENC_PICTURE_TYPE_B:
974 radeon_enc_code_ue(enc, 0x0);
975 break;
976 default:
977 radeon_enc_code_ue(enc, 0x1);
978 }
979
980 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
981 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
982 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
983 radeon_enc_code_fixed_bits(enc, 0x1, 1);
984 else {
985 radeon_enc_code_fixed_bits(enc, 0x0, 1);
986 radeon_enc_code_fixed_bits(enc, 0x0, 1);
987 radeon_enc_code_ue(enc, 0x0);
988 radeon_enc_code_ue(enc, 0x0);
989 }
990 }
991
992 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
993 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
994 radeon_enc_code_fixed_bits(enc, 0x0, 1);
995 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
996 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
997 }
998
999 radeon_enc_flush_headers(enc);
1000 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1001 num_bits[inst_index] = enc->bits_output - bits_copied;
1002 bits_copied = enc->bits_output;
1003 inst_index++;
1004
1005 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1006 inst_index++;
1007
1008 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
1009 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
1010 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1011 1);
1012
1013 radeon_enc_flush_headers(enc);
1014 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1015 num_bits[inst_index] = enc->bits_output - bits_copied;
1016 bits_copied = enc->bits_output;
1017 inst_index++;
1018 }
1019
1020 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1021
1022 cdw_filled = enc->cs.current.cdw - cdw_start;
1023 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1024 RADEON_ENC_CS(0x00000000);
1025
1026 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1027 RADEON_ENC_CS(instruction[j]);
1028 RADEON_ENC_CS(num_bits[j]);
1029 }
1030
1031 RADEON_ENC_END();
1032 }
1033
radeon_enc_ctx(struct radeon_encoder * enc)1034 static void radeon_enc_ctx(struct radeon_encoder *enc)
1035 {
1036 enc->enc_pic.ctx_buf.swizzle_mode = 0;
1037 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
1038
1039 uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
1040 uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
1041
1042 enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
1043 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
1044
1045 int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
1046 if (enc->enc_pic.bit_depth_luma_minus8 == 2)
1047 luma_size *= 2;
1048 int chroma_size = align(luma_size / 2, enc->alignment);
1049 int offset = 0;
1050
1051 for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
1052 offset += luma_size;
1053 offset += chroma_size;
1054 }
1055
1056 assert(offset == enc->dpb_size);
1057
1058 RADEON_ENC_BEGIN(enc->cmd.ctx);
1059 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
1060 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1061 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1062 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1063 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1064
1065 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1066 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
1067 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
1068 }
1069
1070 // 2: 1 pre encode pitch * 2 (luma + chroma)
1071 // 68: 34 pre encode reconstructed pics * 2 (luma + chroma offsets)
1072 // 2: 1 pre encode input pic * 2 (luma + chroma)
1073 //----
1074 // 72
1075
1076 for (int i = 0; i < 72; i++)
1077 RADEON_ENC_CS(0x00000000);
1078
1079 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
1080 RADEON_ENC_END();
1081 }
1082
radeon_enc_bitstream(struct radeon_encoder * enc)1083 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1084 {
1085 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1086 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1087 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
1088
1089 RADEON_ENC_BEGIN(enc->cmd.bitstream);
1090 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1091 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1092 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1093 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1094 RADEON_ENC_END();
1095 }
1096
radeon_enc_feedback(struct radeon_encoder * enc)1097 static void radeon_enc_feedback(struct radeon_encoder *enc)
1098 {
1099 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1100 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1101 enc->enc_pic.fb_buf.feedback_data_size = 40;
1102
1103 RADEON_ENC_BEGIN(enc->cmd.feedback);
1104 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1105 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1106 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1107 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1108 RADEON_ENC_END();
1109 }
1110
radeon_enc_intra_refresh(struct radeon_encoder * enc)1111 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1112 {
1113 enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
1114 enc->enc_pic.intra_ref.offset = 0;
1115 enc->enc_pic.intra_ref.region_size = 0;
1116
1117 RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
1118 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
1119 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
1120 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
1121 RADEON_ENC_END();
1122 }
1123
radeon_enc_rc_per_pic(struct radeon_encoder * enc)1124 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
1125 {
1126 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
1127 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
1128 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
1129 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
1130 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
1131 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1132 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1133 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1134 RADEON_ENC_END();
1135 }
1136
radeon_enc_encode_params(struct radeon_encoder * enc)1137 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1138 {
1139 switch (enc->enc_pic.picture_type) {
1140 case PIPE_H2645_ENC_PICTURE_TYPE_I:
1141 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1142 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1143 break;
1144 case PIPE_H2645_ENC_PICTURE_TYPE_P:
1145 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1146 break;
1147 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1148 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1149 break;
1150 case PIPE_H2645_ENC_PICTURE_TYPE_B:
1151 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1152 break;
1153 default:
1154 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1155 }
1156
1157 if (enc->luma->meta_offset) {
1158 RVID_ERR("DCC surfaces not supported.\n");
1159 return;
1160 }
1161
1162 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1163 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1164 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1165 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1166
1167 RADEON_ENC_BEGIN(enc->cmd.enc_params);
1168 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1169 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1170 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1171 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1172 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1173 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1174 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1175 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1176 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1177 RADEON_ENC_END();
1178 }
1179
radeon_enc_encode_params_h264(struct radeon_encoder * enc)1180 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1181 {
1182 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1183 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1184 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1185 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1186
1187 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1188 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1189 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1190 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1191 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1192 RADEON_ENC_END();
1193 }
1194
radeon_enc_op_init(struct radeon_encoder * enc)1195 static void radeon_enc_op_init(struct radeon_encoder *enc)
1196 {
1197 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1198 RADEON_ENC_END();
1199 }
1200
radeon_enc_op_close(struct radeon_encoder * enc)1201 static void radeon_enc_op_close(struct radeon_encoder *enc)
1202 {
1203 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1204 RADEON_ENC_END();
1205 }
1206
radeon_enc_op_enc(struct radeon_encoder * enc)1207 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1208 {
1209 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1210 RADEON_ENC_END();
1211 }
1212
radeon_enc_op_init_rc(struct radeon_encoder * enc)1213 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1214 {
1215 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1216 RADEON_ENC_END();
1217 }
1218
radeon_enc_op_init_rc_vbv(struct radeon_encoder * enc)1219 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1220 {
1221 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1222 RADEON_ENC_END();
1223 }
1224
radeon_enc_op_speed(struct radeon_encoder * enc)1225 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1226 {
1227 RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1228 RADEON_ENC_END();
1229 }
1230
begin(struct radeon_encoder * enc)1231 static void begin(struct radeon_encoder *enc)
1232 {
1233 unsigned i;
1234
1235 enc->session_info(enc);
1236 enc->total_task_size = 0;
1237 enc->task_info(enc, enc->need_feedback);
1238 enc->op_init(enc);
1239
1240 enc->session_init(enc);
1241 enc->slice_control(enc);
1242 enc->spec_misc(enc);
1243 enc->deblocking_filter(enc);
1244
1245 enc->layer_control(enc);
1246 enc->rc_session_init(enc);
1247 enc->quality_params(enc);
1248
1249 i = 0;
1250 do {
1251 enc->enc_pic.temporal_id = i;
1252 enc->layer_select(enc);
1253 enc->rc_layer_init(enc);
1254 enc->layer_select(enc);
1255 enc->rc_per_pic(enc);
1256 } while (++i < enc->enc_pic.num_temporal_layers);
1257
1258 enc->op_init_rc(enc);
1259 enc->op_init_rc_vbv(enc);
1260 *enc->p_task_size = (enc->total_task_size);
1261 }
1262
radeon_enc_headers_h264(struct radeon_encoder * enc)1263 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1264 {
1265 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1266 enc->nalu_prefix(enc);
1267 if (enc->enc_pic.is_idr) {
1268 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1269 enc->nalu_sei(enc);
1270 enc->nalu_sps(enc);
1271 enc->nalu_pps(enc);
1272 }
1273 enc->slice_header(enc);
1274 enc->encode_params(enc);
1275 enc->encode_params_codec_spec(enc);
1276 }
1277
radeon_enc_headers_hevc(struct radeon_encoder * enc)1278 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1279 {
1280 enc->nalu_aud(enc);
1281 if (enc->enc_pic.is_idr) {
1282 enc->nalu_vps(enc);
1283 enc->nalu_pps(enc);
1284 enc->nalu_sps(enc);
1285 }
1286 enc->slice_header(enc);
1287 enc->encode_params(enc);
1288 }
1289
encode(struct radeon_encoder * enc)1290 static void encode(struct radeon_encoder *enc)
1291 {
1292 enc->before_encode(enc);
1293 enc->session_info(enc);
1294 enc->total_task_size = 0;
1295 enc->task_info(enc, enc->need_feedback);
1296
1297 enc->encode_headers(enc);
1298 enc->ctx(enc);
1299 enc->bitstream(enc);
1300 enc->feedback(enc);
1301 enc->intra_refresh(enc);
1302
1303 enc->op_preset(enc);
1304 enc->op_enc(enc);
1305 *enc->p_task_size = (enc->total_task_size);
1306 }
1307
destroy(struct radeon_encoder * enc)1308 static void destroy(struct radeon_encoder *enc)
1309 {
1310 enc->session_info(enc);
1311 enc->total_task_size = 0;
1312 enc->task_info(enc, enc->need_feedback);
1313 enc->op_close(enc);
1314 *enc->p_task_size = (enc->total_task_size);
1315 }
1316
find_short_ref_idx(struct radeon_encoder * enc,int frame_num)1317 static int find_short_ref_idx(struct radeon_encoder *enc, int frame_num)
1318 {
1319 for (int i = 0; i < enc->base.max_references + 1; i++)
1320 if (enc->dpb[i].frame_num == frame_num && enc->dpb[i].in_use)
1321 return i;
1322
1323 return -1;
1324 }
1325
get_picture_storage(struct radeon_encoder * enc)1326 static int get_picture_storage(struct radeon_encoder *enc)
1327 {
1328 for (int i = 0; i < enc->base.max_references + 1; i++) {
1329 if (!enc->dpb[i].in_use) {
1330 memset(&(enc->dpb[i]), 0, sizeof(rvcn_enc_picture_info_t));
1331 return i;
1332 }
1333 }
1334
1335 /* look for the oldest short term ref pic */
1336 unsigned int oldest_frame_num = 0xFFFFFFFF;
1337 int oldest_idx = -1;
1338 for (int i = 0; i < enc->base.max_references + 1; i++)
1339 if (enc->dpb[i].frame_num < oldest_frame_num) {
1340 oldest_frame_num = enc->dpb[i].frame_num;
1341 oldest_idx = i;
1342 }
1343
1344 if (oldest_idx >= 0)
1345 enc->dpb[oldest_idx].in_use = FALSE;
1346
1347 return oldest_idx;
1348 }
1349
manage_dpb_before_encode(struct radeon_encoder * enc)1350 static void manage_dpb_before_encode(struct radeon_encoder *enc)
1351 {
1352 int current_pic_idx = 0;
1353
1354 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
1355 /* clear reference frames */
1356 for (int i = 0; i < enc->base.max_references + 1; i++)
1357 memset(&(enc->dpb[i]), 0, sizeof(rvcn_enc_picture_info_t));
1358 }
1359
1360 current_pic_idx = get_picture_storage(enc);
1361 assert(current_pic_idx >= 0);
1362
1363 int ref0_idx = find_short_ref_idx(enc, enc->enc_pic.ref_idx_l0);
1364
1365 if (!enc->enc_pic.not_referenced)
1366 enc->dpb[current_pic_idx].in_use = TRUE;
1367
1368 enc->dpb[current_pic_idx].frame_num = enc->enc_pic.frame_num;
1369
1370 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
1371 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1372 else
1373 enc->enc_pic.enc_params.reference_picture_index = ref0_idx;
1374 enc->enc_pic.enc_params.reconstructed_picture_index = current_pic_idx;
1375 }
1376
radeon_enc_1_2_init(struct radeon_encoder * enc)1377 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1378 {
1379 enc->before_encode = manage_dpb_before_encode;
1380 enc->begin = begin;
1381 enc->encode = encode;
1382 enc->destroy = destroy;
1383 enc->session_info = radeon_enc_session_info;
1384 enc->task_info = radeon_enc_task_info;
1385 enc->layer_control = radeon_enc_layer_control;
1386 enc->layer_select = radeon_enc_layer_select;
1387 enc->rc_session_init = radeon_enc_rc_session_init;
1388 enc->rc_layer_init = radeon_enc_rc_layer_init;
1389 enc->quality_params = radeon_enc_quality_params;
1390 enc->ctx = radeon_enc_ctx;
1391 enc->bitstream = radeon_enc_bitstream;
1392 enc->feedback = radeon_enc_feedback;
1393 enc->intra_refresh = radeon_enc_intra_refresh;
1394 enc->rc_per_pic = radeon_enc_rc_per_pic;
1395 enc->encode_params = radeon_enc_encode_params;
1396 enc->op_init = radeon_enc_op_init;
1397 enc->op_close = radeon_enc_op_close;
1398 enc->op_enc = radeon_enc_op_enc;
1399 enc->op_init_rc = radeon_enc_op_init_rc;
1400 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1401 enc->op_preset = radeon_enc_op_speed;
1402 enc->encode_params = radeon_enc_encode_params;
1403 enc->session_init = radeon_enc_session_init;
1404
1405 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1406 enc->slice_control = radeon_enc_slice_control;
1407 enc->spec_misc = radeon_enc_spec_misc;
1408 enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1409 enc->nalu_sps = radeon_enc_nalu_sps;
1410 enc->nalu_pps = radeon_enc_nalu_pps;
1411 enc->slice_header = radeon_enc_slice_header;
1412 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1413 enc->encode_headers = radeon_enc_headers_h264;
1414 enc->nalu_prefix = radeon_enc_nalu_prefix;
1415 enc->nalu_sei = radeon_enc_nalu_sei;
1416 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1417 enc->slice_control = radeon_enc_slice_control_hevc;
1418 enc->spec_misc = radeon_enc_spec_misc_hevc;
1419 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1420 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1421 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1422 enc->nalu_vps = radeon_enc_nalu_vps;
1423 enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1424 enc->slice_header = radeon_enc_slice_header_hevc;
1425 enc->encode_headers = radeon_enc_headers_hevc;
1426 }
1427
1428 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1429 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1430 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1431 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1432 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1433 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1434 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1435 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1436 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1437 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1438 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1439 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1440 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1441 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1442 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1443 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1444 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1445 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1446 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1447 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1448 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1449 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1450 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1451
1452 enc->enc_pic.session_info.interface_version =
1453 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1454 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1455 }
1456