| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_tcs.cpp | 156 const src_reg &indirect_offset) in emit_input_urb_read() argument
165 indirect_offset); in emit_input_urb_read()
178 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
191 const src_reg &indirect_offset) in emit_output_urb_read() argument
198 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
218 const src_reg &indirect_offset) in emit_urb_write() argument
227 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
257 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
267 first_component, indirect_offset); in nir_emit_intrinsic()
275 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
[all …]
|
| D | brw_vec4_tcs.h | 61 const src_reg &indirect_offset);
65 const src_reg &indirect_offset);
68 unsigned base_offset, const src_reg &indirect_offset);
|
| D | brw_vec4_tes.cpp | 154 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
159 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
167 retype(indirect_offset, BRW_REGISTER_TYPE_UD), in nir_emit_intrinsic()
|
| D | brw_reg.h | 235 int indirect_offset:10; /* relative addressing offset */ member
434 reg.indirect_offset = 0; in brw_reg()
1144 reg.indirect_offset = offset; in brw_vec4_indirect()
1154 reg.indirect_offset = offset; in brw_vec1_indirect()
1165 reg.indirect_offset = offset; in brw_VxH_indirect()
|
| D | brw_ir.h | 77 using brw_reg::indirect_offset;
|
| D | brw_fs_nir.cpp | 2614 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load() local
2647 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; in emit_gs_input_load()
2914 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2932 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2951 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; in nir_emit_tcs_intrinsic()
2976 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2988 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2995 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
3029 srcs[URB_LOGICAL_SRC_PER_SLOT_OFFSETS] = indirect_offset; in nir_emit_tcs_intrinsic()
3057 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
[all …]
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_const.h | 584 unsigned indirect_offset; in ir3_emit_cs_consts() local
594 if (info->indirect_offset & 0xf) { in ir3_emit_cs_consts()
598 indirect_offset = 0; in ir3_emit_cs_consts()
601 info->indirect_offset, 3); in ir3_emit_cs_consts()
604 indirect_offset = info->indirect_offset; in ir3_emit_cs_consts()
607 emit_const_prsc(ring, v, offset * 4, indirect_offset, 16, indirect); in ir3_emit_cs_consts()
|
| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_draw.h | 94 GLsizeiptr indirect_offset,
|
| D | st_draw.c | 239 GLsizeiptr indirect_offset, in st_indirect_draw_vbo() argument
276 indirect.offset = indirect_offset; in st_indirect_draw_vbo()
|
| /third_party/mesa3d/src/panfrost/midgard/ |
| D | midgard_compile.c | 1198 nir_src *indirect_offset, in emit_ubo_read() argument
1229 if (indirect_offset) { in emit_ubo_read()
1230 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_ubo_read()
1242 if (indirect_offset && indirect_offset->is_ssa && !indirect_shift) in emit_ubo_read()
1243 mir_set_ubo_offset(&ins, indirect_offset, offset); in emit_ubo_read()
1422 nir_src *indirect_offset, nir_alu_type type, bool flat) in emit_varying_read() argument
1447 if (indirect_offset) { in emit_varying_read()
1448 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_varying_read()
1837 nir_src *indirect_offset = direct ? NULL : src_offset; in emit_intrinsic() local
1848 … emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, 0, nr_comp); in emit_intrinsic()
[all …]
|
| /third_party/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 1740 $$.indirect_offset = $3.indirect_offset;
1776 $$.indirect_offset = $2;
1808 $$.indirect_offset = $3.indirect_offset;
1827 $$.indirect_offset = $3.indirect_offset;
|
| /third_party/mesa3d/src/gallium/drivers/etnaviv/tests/ |
| D | lower_ubo_tests.cpp | 169 TEST_F(nir_lower_ubo_test, indirect_offset) in TEST_F() argument
|
| /third_party/mesa3d/src/gallium/drivers/svga/ |
| D | svga_pipe_cs.c | 213 info->indirect_offset)); in svga_launch_grid()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_compute.c | 177 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd5_launch_grid()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | fd4_compute.c | 192 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); in fd4_launch_grid()
|
| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_compute.c | 184 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd6_launch_grid()
|
| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nvc0_compute.c | 472 uint32_t offset = res->offset + info->indirect_offset; in nvc0_launch_grid()
512 uint32_t offset = res->offset + info->indirect_offset; in nvc0_compute_update_indirect_invocations()
|
| /third_party/mesa3d/src/gallium/drivers/softpipe/ |
| D | sp_compute.c | 151 info->indirect_offset, in fill_grid_size()
|
| /third_party/mesa3d/src/gallium/include/pipe/ |
| D | p_state.h | 992 unsigned indirect_offset; /**< must be 4 byte aligned */ member
|
| /third_party/mesa3d/src/gallium/drivers/d3d12/ |
| D | d3d12_draw.cpp | 1314 unsigned indirect_offset = info->indirect_offset; in d3d12_launch_grid() local
1315 …if (indirect && update_dispatch_indirect_with_sysvals(ctx, &indirect, &indirect_offset, &patched_i… in d3d12_launch_grid()
1367 indirect_arg_offset = indirect_offset + buf_offset; in d3d12_launch_grid()
|
| /third_party/mesa3d/src/mesa/main/ |
| D | compute.c | 370 info.indirect_offset = indirect; in dispatch_compute_indirect()
|
| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_program.c | 95 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
99 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0)); in indirect_uniform_load()
100 indirect_offset = qir_MIN_NOIMM(c, indirect_offset, in indirect_uniform_load()
104 indirect_offset, in indirect_uniform_load()
|
| /third_party/mesa3d/src/gallium/drivers/iris/ |
| D | iris_draw.c | 340 grid_ref->offset = grid->indirect_offset; in iris_update_grid_size_resource()
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_compute.c | 777 info->indirect_offset + 4 * i); in si_setup_nir_user_data()
870 radeon_emit(info->indirect_offset); in si_emit_dispatch_packets()
|
| /third_party/mesa3d/src/gallium/drivers/crocus/ |
| D | crocus_draw.c | 458 grid_ref->offset = grid->indirect_offset; in crocus_update_grid_size_resource()
|