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Searched refs:instrs (Results 1 – 25 of 75) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td400 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>;
401 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>;
435 def : InstRW<[WriteI], (instrs COPY)>;
483 (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>;
486 (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>;
526 // (instrs MADDWrrr, MSUBWrrr)>;
527 def : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>;
528 def : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>;
532 def : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>;
533 def : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>;
[all …]
DAArch64SchedA57.td129 def : InstRW<[WriteI], (instrs COPY)>;
135 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
136 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
152 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
158 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
159 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
557 def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
558 def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
564 def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
565 def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
[all …]
DAArch64SchedFalkorDetails.td582 def : InstRW<[FalkorWr_1XYZ_1cyc], (instrs COPY)>;
599 def : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTXNv1i64)>;
605 (instrs FMULX32)>;
610 (instrs FMULX64)>;
616 def : InstRW<[FalkorWr_2VXVY_2cyc], (instrs FCVTLv4i16, FCVTLv2i32)>;
619 def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVv2f32)>;
620 def : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTv2f32)>;
625 def : InstRW<[FalkorWr_2VXVY_4cyc], (instrs FCVTLv8i16, FCVTLv4i32)>;
634 def : InstRW<[FalkorWr_3VXVY_4cyc], (instrs FCVTNv4i16, FCVTNv2i32, FCVTXNv2f32)>;
635 def : InstRW<[FalkorWr_3VXVY_5cyc], (instrs FCVTNv8i16, FCVTNv4i32, FCVTXNv4f32)>;
[all …]
DAArch64SchedKryoDetails.td99 (instrs SADDLVv4i32v, UADDLVv4i32v)>;
105 (instrs SADDLVv8i16v, UADDLVv8i16v)>;
111 (instrs SADDLVv16i8v, UADDLVv16i8v)>;
117 (instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>;
123 (instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>;
195 (instrs SMULHrr, UMULHrr)>;
339 (instrs ABSv1i64)>;
369 (instrs ADDv1i64)>;
393 (instrs ADDPv2i64p)>;
405 (instrs ADDVv4i32v)>;
[all …]
DAArch64SchedExynosM5.td622 def : InstRW<[M5WriteB1], (instrs Bcc)>;
623 def : InstRW<[M5WriteAFX], (instrs BL)>;
624 def : InstRW<[M5WriteBX], (instrs BLR)>;
634 def : InstRW<[M5WriteAUW], (instrs ORRWrs)>;
635 def : InstRW<[M5WriteAUX], (instrs ORRXrs)>;
640 def : InstRW<[M5WriteAVW], (instrs ADDWri, ORRWri)>;
641 def : InstRW<[M5WriteAVX], (instrs ADDXri, ORRXri)>;
644 def : InstRW<[M5WriteA1W], (instrs CSELWr, CSINCWr, CSINVWr, CSNEGWr)>;
645 def : InstRW<[M5WriteA1X], (instrs CSELXr, CSINCXr, CSINVXr, CSNEGXr)>;
648 def : InstRW<[M5WriteCOPY], (instrs COPY)>;
[all …]
DAArch64SchedCyclone.td116 def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
127 def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>;
274 def : InstRW<[WriteST, WriteST], (instrs STPQi)>;
292 def : InstRW<[WriteI], (instrs ISB)>;
336 def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
352 def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;
433 def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>;
434 def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>;
441 def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32,
445 def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64,
[all …]
DAArch64SchedExynosM4.td587 def : InstRW<[M4WriteB1], (instrs Bcc)>;
588 def : InstRW<[M4WriteAF], (instrs BL)>;
589 def : InstRW<[M4WriteBX], (instrs BLR)>;
595 def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>;
598 def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>;
601 def : InstRW<[M4WriteCOPY], (instrs COPY)>;
602 def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>;
618 ReadAdrBase], (instrs PRFMroW)>;
620 ReadAdrBase], (instrs PRFMroX)>;
629 def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleGeneric.td47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
104 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MMR6, ADDIU_MMR6, ADDU16_MMR6,
119 def : InstRW<[GenericWriteALU], (instrs AND64, ANDi64, DEXT64_32, DSLL64_32,
124 def : InstRW<[GenericWriteALU], (instrs DADD, DADDi, DADDiu, DADDu, DCLO,
134 def : InstRW<[GenericWriteALU], (instrs DALIGN, DAHI, DATI, DAUI, DCLO_R6,
[all …]
DMipsScheduleP5600.td40 def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB,
67 def : InstRW<[P5600Nop], (instrs SSNOP, NOP)>;
71 def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL,
82 def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo,
85 def : InstRW<[P5600WriteJumpAndLink], (instrs JALX)> {
91 def : InstRW<[P5600COP0], (instrs TLBINV, TLBINVF, TLBP, TLBR, TLBWI, TLBWR,
96 def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> {
102 def : InstRW<[P5600COP0], (instrs HYPCALL, MFGC0, MFHGC0, MTGC0, MTHGC0,
134 def : InstRW<[P5600WriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, LWC2, LWC3,
139 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
[all …]
/third_party/mesa3d/src/freedreno/afuc/
Ddisasm.c289 disasm_instr(uint32_t *instrs, unsigned pc) in disasm_instr() argument
292 afuc_instr *instr = (void *)&instrs[pc]; in disasm_instr()
331 printf("\t%04x: %08x ", pc, instrs[pc]); in disasm_instr()
342 if (instrs[pc] != nop) { in disasm_instr()
343 printerr("[%08x]", instrs[pc]); in disasm_instr()
349 print_gpu_reg(instrs[pc]); in disasm_instr()
377 print_alu_name(opc, instrs[pc]); in disasm_instr()
453 printf("[%08x] ; ", instrs[pc]); in disasm_instr()
470 print_alu_name(instr->alu.alu, instrs[pc]); in disasm_instr()
665 printf("[%08x] ; ", instrs[pc]); in disasm_instr()
[all …]
/third_party/mesa3d/src/panfrost/bifrost/
Ddisassemble.c444 struct bifrost_alu_inst instrs[8] = {}; in dump_clause() local
482 instrs[idx + 1] = main_instr; in dump_clause()
483 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17); in dump_clause()
484 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
494 instrs[1] = main_instr; in dump_clause()
500 … instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
501 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
511 … instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
512 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
514 instrs[3] = main_instr; in dump_clause()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ScheduleAtom.td173 def : InstRW<[WriteMove], (instrs COPY)>;
500 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
512 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
519 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
527 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
541 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
549 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
561 def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
578 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
594 def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
[all …]
DX86SchedHaswell.td644 def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
688 def : InstRW<[HWWriteINTO], (instrs INTO)>;
704 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
720 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
727 def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
734 def : InstRW<[HWWriteP01], (instrs LD_Frr)>;
742 def : InstRW<[HWWriteFBLD], (instrs FBLDm)>;
755 def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>;
761 def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>;
767 def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
[all …]
DX86ScheduleBdVer2.td279 def : InstRW<[WriteMove], (instrs COPY)>;
306 def : InstRW<[PdWriteXLAT], (instrs XLAT)>;
338 def : InstRW<[PdWriteLXADD], (instrs LXADD8, LXADD16, LXADD32, LXADD64)>;
346 (instrs BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr,
358 (instrs BLCFILL32rm, BLCFILL64rm, BLCI32rm, BLCI64rm,
369 def : InstRW<[PdWriteADCSBB64ri32], (instrs ADC64ri32, SBB64ri32)>;
382 def : InstRW<[PdWriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
389 def : InstRW<[PdWriteCMPXCHG8rm], (instrs CMPXCHG8rm)>;
397 (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
404 def : InstRW<[PdWriteCMPXCHG8B], (instrs CMPXCHG8B)>;
[all …]
DX86SchedBroadwell.td172 defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs
175 defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
214 def : InstRW<[WriteMove], (instrs COPY)>;
607 // Remaining instrs.
630 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
644 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
651 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
672 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
683 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
691 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
[all …]
DX86ScheduleZnver1.td237 def : InstRW<[WriteMove], (instrs COPY)>;
526 def : InstRW<[WriteALULd, ReadAfterLd], (instrs MOV16rm)>;
540 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
548 def : InstRW<[ZnWritePop16r], (instrs POP16rmm)>;
571 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
660 def : InstRW<[ZnWriteMulX32], (instrs MULX32rr)>;
667 def : InstRW<[ZnWriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
673 def : InstRW<[ZnWriteMulX64], (instrs MULX64rr)>;
679 def : InstRW<[ZnWriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
685 def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
[all …]
DX86SchedSkylakeClient.td607 // Remaining instrs.
644 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
651 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
673 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
686 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
694 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
701 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
709 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
725 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
732 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
[all …]
DX86SchedSkylakeServer.td608 // Remaining instrs.
657 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
664 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
696 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
709 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
718 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
725 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
733 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
749 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
756 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
[all …]
DX86ScheduleZnver2.td225 def : InstRW<[WriteMove], (instrs COPY)>;
529 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
560 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
649 def : InstRW<[Zn2WriteMulX32], (instrs MULX32rr)>;
656 def : InstRW<[Zn2WriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>;
662 def : InstRW<[Zn2WriteMulX64], (instrs MULX64rr)>;
668 def : InstRW<[Zn2WriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>;
674 def : InstRW<[Zn2WriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
677 def : InstRW<[WriteMicrocoded], (instrs INTO)>;
681 def : InstRW<[Zn2WriteLOOP], (instrs LOOP)>;
[all …]
DX86SchedSandyBridge.td579 // Remaining SNB instrs.
586 def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
596 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
598 def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared …
599 def: InstRW<[SBWriteResGroup2], (instrs RETQ)>;
606 def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
613 def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
627 def: InstRW<[SBWriteResGroup11], (instrs SCASB,
644 def: InstRW<[SBWriteResGroup15], (instrs CWD,
652 def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
[all …]
DX86ScheduleBtVer2.td282 def : InstRW<[WriteMove], (instrs COPY)>;
376 ReadAfterLd, ReadAfterLd], (instrs LCMPXCHG8, LCMPXCHG16,
381 def : InstRW<[JWriteCMPXCHGVariant], (instrs CMPXCHG8rr, CMPXCHG16rr,
388 ReadAfterLd, ReadAfterLd, ReadAfterLd, ReadAfterLd], (instrs LCMPXCHG8B, LCMPXCHG16B,
401 def : InstRW<[JWriteLOCK_ALURMWVariant], (instrs INC8m, INC16m, INC32m, INC64m,
411 def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
489 (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm,
493 (instrs XCHG8rm, XCHG16rm, XCHG32rm, XCHG64rm)>;
794 def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
801 def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td37 (instrs
90 (instrs
106 (instrs
123 (instrs
178 (instrs
206 (instrs
291 (instrs
400 (instrs
408 (instrs
453 (instrs
[all …]
/third_party/mesa3d/src/amd/compiler/
Daco_form_hard_clauses.cpp42 emit_clause(Builder& bld, unsigned num_instrs, aco_ptr<Instruction>* instrs) in emit_clause() argument
47 for (; (start < num_instrs) && instrs[start]->definitions.empty(); start++) in emit_clause()
48 bld.insert(std::move(instrs[start])); in emit_clause()
51 for (; (end < num_instrs) && !instrs[end]->definitions.empty(); end++) in emit_clause()
59 bld.insert(std::move(instrs[i])); in emit_clause()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_nir_optim.c56 struct set *instrs = _mesa_set_create(NULL, _mesa_hash_pointer, in check_instr_depends_on_tex() local
60 _mesa_set_add(instrs, &store->instr); in check_instr_depends_on_tex()
65 if (_mesa_set_search(instrs, instr)) in check_instr_depends_on_tex()
68 _mesa_set_add(instrs, instr); in check_instr_depends_on_tex()
91 _mesa_set_destroy(instrs, NULL); in check_instr_depends_on_tex()
/third_party/mesa3d/src/freedreno/decode/
Dpgmdump.c542 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
562 instrs = &vs_hdr[n]; in dump_shaders_a3xx()
572 instrs = ptr; in dump_shaders_a3xx()
597 dump_hex(instrs, instrs_size); in dump_shaders_a3xx()
605 instrs += ALIGN(instrs_size, 8) - instrs_size; in dump_shaders_a3xx()
608 instrs += 32; in dump_shaders_a3xx()
612 disasm_a3xx((uint32_t *)instrs, instrs_size / 4, level + 1, stdout, in dump_shaders_a3xx()
614 dump_raw_shader((uint32_t *)instrs, instrs_size / 4, i, "vo3"); in dump_shaders_a3xx()
623 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
642 instrs = &fs_hdr[n]; in dump_shaders_a3xx()
[all …]

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