| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_radeon_winsys.h | 104 struct radeon_cmdbuf { struct
193 struct radeon_cmdbuf **cs_array;
194 struct radeon_cmdbuf *initial_preamble_cs;
195 struct radeon_cmdbuf *continue_preamble_cs;
274 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type);
276 void (*cs_destroy)(struct radeon_cmdbuf *cs);
278 void (*cs_reset)(struct radeon_cmdbuf *cs);
280 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
282 void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
289 void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
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| D | radv_cs.h | 35 radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed) in radeon_check_space()
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) in radeon_set_context_reg_idx()
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask) in radeon_set_context_reg_rmw()
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
115 radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, in radeon_set_sh_reg_idx()
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| D | radv_private.h | 758 struct radeon_cmdbuf *initial_preamble_cs;
759 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
760 struct radeon_cmdbuf *continue_preamble_cs;
939 struct radeon_cmdbuf **perf_counter_lock_cs;
1590 struct radeon_cmdbuf *cs;
1633 struct radeon_cmdbuf *cs;
1671 void si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs);
1672 void si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs);
1676 void si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors,
1683 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec,
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| D | radv_sqtt.c | 64 radv_emit_wait_for_idle(struct radv_device *device, struct radeon_cmdbuf *cs, int family) in radv_emit_wait_for_idle()
79 radv_emit_thread_trace_start(struct radv_device *device, struct radeon_cmdbuf *cs, in radv_emit_thread_trace_start()
225 radv_copy_thread_trace_info_regs(struct radv_device *device, struct radeon_cmdbuf *cs, in radv_copy_thread_trace_info_regs()
256 radv_emit_thread_trace_stop(struct radv_device *device, struct radeon_cmdbuf *cs, in radv_emit_thread_trace_stop()
342 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_emit_thread_trace_userdata()
368 radv_emit_spi_config_cntl(struct radv_device *device, struct radeon_cmdbuf *cs, bool enable) in radv_emit_spi_config_cntl()
388 radv_emit_inhibit_clockgating(struct radv_device *device, struct radeon_cmdbuf *cs, bool inhibit) in radv_emit_inhibit_clockgating()
534 struct radeon_cmdbuf *cs; in radv_begin_thread_trace()
603 struct radeon_cmdbuf *cs; in radv_end_thread_trace()
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| D | radv_perfcounter.c | 33 radv_perfcounter_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders) in radv_perfcounter_emit_shaders()
41 radv_emit_windowed_counters(struct radv_device *device, struct radeon_cmdbuf *cs, int family, in radv_emit_windowed_counters()
54 radv_perfcounter_emit_spm_reset(struct radeon_cmdbuf *cs) in radv_perfcounter_emit_spm_reset()
62 radv_perfcounter_emit_spm_start(struct radv_device *device, struct radeon_cmdbuf *cs, int family) in radv_perfcounter_emit_spm_start()
73 radv_perfcounter_emit_spm_stop(struct radv_device *device, struct radeon_cmdbuf *cs, int family) in radv_perfcounter_emit_spm_stop()
469 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_emit_instance()
492 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_emit_select()
517 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_pc_emit_block_instance_read()
560 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_pc_wait_idle()
582 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_pc_stop_and_sample()
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| D | si_cmd_buffer.c | 37 struct radeon_cmdbuf *cs, unsigned raster_config, in si_write_harvested_raster_configs()
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_compute()
176 si_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) in si_set_raster_config()
197 si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_graphics()
633 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, AMD_IP_GFX); in cik_create_gfx_config()
717 si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, in si_write_scissors()
927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, in si_cs_emit_write_event_eop()
1014 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask) in radv_cp_wait_mem()
1029 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in si_emit_acquire_mem()
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, in gfx10_cs_emit_cache_flush()
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| /third_party/mesa3d/src/gallium/include/winsys/ |
| D | radeon_winsys.h | 196 struct radeon_cmdbuf { struct
332 struct radeon_cmdbuf *cs, enum pipe_map_flags usage);
502 bool (*cs_create)(struct radeon_cmdbuf *cs,
518 void (*cs_set_preamble)(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
528 bool (*cs_setup_preemption)(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
536 void (*cs_destroy)(struct radeon_cmdbuf *cs);
547 unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
560 int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf);
570 bool (*cs_validate)(struct radeon_cmdbuf *cs);
580 bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw);
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 45 struct radeon_cmdbuf *cs, in radeon_cs_memory_below_limit()
118 struct radeon_cmdbuf *cs = &ring->cs; in r600_emit_reloc()
128 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
136 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
142 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
150 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
156 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, in radeon_set_context_reg_idx()
167 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
175 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
181 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
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| D | r600_viewport.c | 157 struct radeon_cmdbuf *cs, in r600_emit_one_scissor()
188 struct radeon_cmdbuf *cs = &rctx->gfx.cs; in r600_emit_guardband()
238 struct radeon_cmdbuf *cs = &rctx->gfx.cs; in r600_emit_scissors()
309 struct radeon_cmdbuf *cs = &rctx->gfx.cs; in r600_emit_one_viewport()
321 struct radeon_cmdbuf *cs = &rctx->gfx.cs; in r600_emit_viewports()
351 struct radeon_cmdbuf *cs = &rctx->gfx.cs; in r600_emit_depth_ranges()
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| D | r600_pipe.h | 622 static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs, in r600_emit_command_buffer()
812 struct radeon_cmdbuf *cs,
815 struct radeon_cmdbuf *cs,
988 static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsig… in radeon_compute_set_context_reg_seq()
995 static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_ctl_const_seq()
1003 static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned … in radeon_compute_set_context_reg()
1009 static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned val… in radeon_set_context_reg_flag()
1018 static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_ctl_const()
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| /third_party/mesa3d/src/amd/vulkan/winsys/null/ |
| D | radv_null_cs.c | 32 struct radeon_cmdbuf base;
37 radv_null_cs(struct radeon_cmdbuf *base) in radv_null_cs()
68 static struct radeon_cmdbuf *
88 radv_null_cs_finalize(struct radeon_cmdbuf *_cs) in radv_null_cs_finalize()
94 radv_null_cs_destroy(struct radeon_cmdbuf *rcs) in radv_null_cs_destroy()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_sqtt.c | 38 struct radeon_cmdbuf *cs, bool enable);
80 struct radeon_cmdbuf *cs, in si_emit_thread_trace_start()
245 struct radeon_cmdbuf *cs, in si_copy_thread_trace_info_regs()
286 struct radeon_cmdbuf *cs, in si_emit_thread_trace_stop()
379 si_thread_trace_start(struct si_context *sctx, int family, struct radeon_cmdbuf *cs) in si_thread_trace_start()
433 si_thread_trace_stop(struct si_context *sctx, int family, struct radeon_cmdbuf *cs) in si_thread_trace_stop()
491 sctx->thread_trace->start_cs[AMD_IP_GFX] = CALLOC_STRUCT(radeon_cmdbuf); in si_thread_trace_init_cs()
502 sctx->thread_trace->stop_cs[AMD_IP_GFX] = CALLOC_STRUCT(radeon_cmdbuf); in si_thread_trace_init_cs()
516 si_begin_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs) in si_begin_thread_trace()
518 struct radeon_cmdbuf *cs = sctx->thread_trace->start_cs[AMD_IP_GFX]; in si_begin_thread_trace()
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| D | si_pipe.h | 945 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */
946 struct radeon_cmdbuf *sdma_cs;
961 void (*emit_cache_flush)(struct si_context *ctx, struct radeon_cmdbuf *cs);
1442 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1443 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1454 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1462 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1477 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1482 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1500 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
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| D | si_perfcounter.c | 63 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_instance()
88 void si_pc_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders) in si_pc_emit_shaders()
101 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_select()
127 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_start()
146 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_stop()
170 void si_pc_emit_spm_start(struct radeon_cmdbuf *cs) in si_pc_emit_spm_start()
186 void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_counters, in si_pc_emit_spm_stop()
209 void si_pc_emit_spm_reset(struct radeon_cmdbuf *cs) in si_pc_emit_spm_reset()
223 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_pc_emit_read()
277 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit) in si_inhibit_clockgating()
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| D | radeon_vcn.h | 44 void rvcn_sq_header(struct radeon_cmdbuf *cs,
48 void rvcn_sq_tail(struct radeon_cmdbuf *cs,
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| D | si_state_msaa.c | 150 static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, in si_emit_max_4_sample_locs()
164 static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, in si_emit_max_16_sample_locs()
180 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) in si_emit_sample_locations()
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| D | radeon_vcn.c | 29 void rvcn_sq_header(struct radeon_cmdbuf *cs, in rvcn_sq_header()
49 void rvcn_sq_tail(struct radeon_cmdbuf *cs, in rvcn_sq_tail()
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| D | radeon_vcn_dec.h | 58 struct radeon_cmdbuf cs;
113 struct radeon_cmdbuf *jcs;
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| D | si_cp_dma.c | 57 static void si_emit_cp_dma(struct si_context *sctx, struct radeon_cmdbuf *cs, uint64_t dst_va, in si_emit_cp_dma()
134 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs) in si_cp_dma_wait_for_idle()
189 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs, in si_cp_dma_clear_buffer()
450 struct radeon_cmdbuf *cs = &sctx->gfx_cs; in si_cp_write_data()
470 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel, in si_cp_copy_data()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_shadowed_regs.h | 31 struct radeon_cmdbuf;
54 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num,
60 void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs,
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_cs.c | 69 static struct pipe_fence_handle *radeon_cs_create_fence(struct radeon_cmdbuf *rcs);
174 radeon_drm_cs_create(struct radeon_cmdbuf *rcs, in radeon_drm_cs_create()
219 static void radeon_drm_cs_set_preamble(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib, in radeon_drm_cs_set_preamble()
369 static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_add_buffer()
419 static int radeon_drm_cs_lookup_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_lookup_buffer()
427 static bool radeon_drm_cs_validate(struct radeon_cmdbuf *rcs) in radeon_drm_cs_validate()
466 static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) in radeon_drm_cs_check_space()
472 static unsigned radeon_drm_cs_get_buffer_list(struct radeon_cmdbuf *rcs, in radeon_drm_cs_get_buffer_list()
523 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs) in radeon_drm_cs_sync_flush()
582 static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, in radeon_drm_cs_flush()
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| D | radeon_drm_cs.h | 99 radeon_drm_cs(struct radeon_cmdbuf *rcs) in radeon_drm_cs()
138 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs);
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| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_cs.c | 55 struct radeon_cmdbuf base;
83 struct radeon_cmdbuf *old_cs_buffers;
110 radv_amdgpu_cs(struct radeon_cmdbuf *base) in radv_amdgpu_cs()
177 radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) in radv_amdgpu_cs_destroy()
223 static struct radeon_cmdbuf *
300 radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size) in radv_amdgpu_cs_grow()
318 struct radeon_cmdbuf *old_cs_buffers = in radv_amdgpu_cs_grow()
425 radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) in radv_amdgpu_cs_finalize()
460 radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs) in radv_amdgpu_cs_reset()
492 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; in radv_amdgpu_cs_reset()
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| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_cs.c | 252 amdgpu_cs_get_next_fence(struct radeon_cmdbuf *rcs) in amdgpu_cs_get_next_fence()
527 amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs_context *cs, in amdgpu_lookup_or_add_real_buffer()
549 static int amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs, in amdgpu_lookup_or_add_slab_buffer()
597 static int amdgpu_lookup_or_add_sparse_buffer(struct radeon_cmdbuf *rcs, in amdgpu_lookup_or_add_sparse_buffer()
653 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, in amdgpu_cs_add_buffer()
772 struct radeon_cmdbuf *rcs, in amdgpu_get_new_ib()
830 static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib) in amdgpu_set_ib_size()
840 static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs, in amdgpu_ib_finalize()
956 amdgpu_cs_create(struct radeon_cmdbuf *rcs, in amdgpu_cs_create()
1030 static void amdgpu_cs_set_preamble(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib, in amdgpu_cs_set_preamble()
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| D | amdgpu_cs.h | 64 struct radeon_cmdbuf *rcs; /* pointer to the driver-owned data */
221 amdgpu_cs(struct radeon_cmdbuf *rcs) in amdgpu_cs()
262 void amdgpu_cs_sync_flush(struct radeon_cmdbuf *rcs);
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