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1 /*
2  * Copyright © 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining
5  * a copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  */
25 
26 #include "radeon_vcn.h"
27 
28 /* vcn unified queue (sq) ib header */
rvcn_sq_header(struct radeon_cmdbuf * cs,struct rvcn_sq_var * sq,bool enc)29 void rvcn_sq_header(struct radeon_cmdbuf *cs,
30                     struct rvcn_sq_var *sq,
31                     bool enc)
32 {
33    /* vcn ib signature */
34    radeon_emit(cs, RADEON_VCN_SIGNATURE_SIZE);
35    radeon_emit(cs, RADEON_VCN_SIGNATURE);
36    sq->ib_checksum = &cs->current.buf[cs->current.cdw];
37    radeon_emit(cs, 0);
38    sq->ib_total_size_in_dw = &cs->current.buf[cs->current.cdw];
39    radeon_emit(cs, 0);
40 
41    /* vcn ib engine info */
42    radeon_emit(cs, RADEON_VCN_ENGINE_INFO_SIZE);
43    radeon_emit(cs, RADEON_VCN_ENGINE_INFO);
44    radeon_emit(cs, enc ? RADEON_VCN_ENGINE_TYPE_ENCODE
45                        : RADEON_VCN_ENGINE_TYPE_DECODE);
46    radeon_emit(cs, 0);
47 }
48 
rvcn_sq_tail(struct radeon_cmdbuf * cs,struct rvcn_sq_var * sq)49 void rvcn_sq_tail(struct radeon_cmdbuf *cs,
50                   struct rvcn_sq_var *sq)
51 {
52    uint32_t *end;
53    uint32_t size_in_dw;
54    uint32_t checksum = 0;
55 
56    if (sq->ib_checksum == NULL || sq->ib_total_size_in_dw == NULL)
57       return;
58 
59    end = &cs->current.buf[cs->current.cdw];
60    size_in_dw = end - sq->ib_total_size_in_dw - 1;
61    *sq->ib_total_size_in_dw = size_in_dw;
62    *(sq->ib_total_size_in_dw + 4) = size_in_dw * sizeof(uint32_t);
63 
64    for (int i = 0; i < size_in_dw; i++)
65       checksum += *(sq->ib_checksum + 2 + i);
66 
67    *sq->ib_checksum = checksum;
68 }
69