Searched refs:reg_info (Results 1 – 7 of 7) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| D | regalloc.c | 30 struct reg_info { struct
43 struct reg_info *registers; argument
153 struct reg_info *a = &ctx->registers[i]; in add_interference()
154 struct reg_info *b = &ctx->registers[j]; in add_interference()
240 struct reg_info *info = &ctx->registers[i]; in can_simplify()
249 struct reg_info *info = &ctx->registers[i]; in push_stack()
253 struct reg_info *conflict_info = &ctx->registers[*conflict]; in push_stack()
292 struct reg_info *info = &ctx->registers[reg]; in do_regalloc()
311 struct reg_info *reg = &ctx->registers[idx]; in do_regalloc()
319 struct reg_info *conflict = &ctx->registers[*conflict_idx]; in do_regalloc()
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| /third_party/vulkan-loader/tests/framework/shim/ |
| D | windows_shim.cpp | 82 auto *reg_info = reinterpret_cast<LoaderQueryRegistryInfo *>(query_info->private_data); in ShimQueryAdapterInfo() local
85 if (reg_info->value_name[6] == L'D') { // looking for drivers in ShimQueryAdapterInfo()
87 } else if (reg_info->value_name[6] == L'I') { // looking for implicit layers in ShimQueryAdapterInfo()
89 } else if (reg_info->value_name[6] == L'E') { // looking for explicit layers in ShimQueryAdapterInfo()
93 reg_info->status = LOADER_QUERY_REGISTRY_STATUS_SUCCESS; in ShimQueryAdapterInfo()
94 if (reg_info->output_value_size == 0) { in ShimQueryAdapterInfo()
98 reg_info->output_value_size = size; in ShimQueryAdapterInfo()
101 reg_info->status = LOADER_QUERY_REGISTRY_STATUS_BUFFER_OVERFLOW; in ShimQueryAdapterInfo()
103 } else if (reg_info->output_value_size > 2) { in ShimQueryAdapterInfo()
107 reg_info->output_string[index++] = w; in ShimQueryAdapterInfo()
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| /third_party/mesa3d/src/panfrost/midgard/ |
| D | disassemble.c | 794 midgard_reg_info *reg_info = (midgard_reg_info *)®_word; in print_vector_field() local
816 print_dest(ctx, fp, reg_info->out_reg); in print_vector_field()
850 if (reg_info->src1_reg == REGISTER_CONSTANT) in print_vector_field()
854 print_vector_src(ctx, fp, alu_field->src1, mode, reg_info->src1_reg, in print_vector_field()
860 if (reg_info->src2_imm) { in print_vector_field()
861 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2); in print_vector_field()
863 } else if (reg_info->src2_reg == REGISTER_CONSTANT) { in print_vector_field()
867 print_vector_src(ctx, fp, alu_field->src2, mode, reg_info->src2_reg, in print_vector_field()
911 midgard_reg_info *reg_info = (midgard_reg_info *)®_word; in print_scalar_field() local
931 print_dest(ctx, fp, reg_info->out_reg); in print_scalar_field()
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| /third_party/ltp/tools/sparse/sparse-src/ |
| D | compile-i386.c | 102 struct reg_info { struct
114 struct reg_info *reg; argument
216 static struct reg_info reg_info_table[] = {
269 static inline struct storage * reginfo_reg(struct reg_info *info) in reginfo_reg()
276 struct reg_info *info = reg->reg; in get_hardreg()
298 struct reg_info *info = reg->reg; in put_reg()
336 struct reg_info *info = reg_info_table + regno; in register_busy()
367 struct reg_info *info; in get_reg_value()
1202 struct reg_info *info = src->reg; in emit_move()
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| /third_party/mesa3d/src/imagination/vulkan/ |
| D | pvr_descriptor_set.c | 862 struct pvr_pipeline_layout_reg_info *const reg_info = in pvr_CreatePipelineLayout() local
865 *reg_info = (struct pvr_pipeline_layout_reg_info){ 0 }; in pvr_CreatePipelineLayout()
885 reg_info->primary_dynamic_size_in_dwords += in pvr_CreatePipelineLayout()
887 reg_info->secondary_dynamic_size_in_dwords += in pvr_CreatePipelineLayout()
927 next_free_reg[stage] = reg_info->primary_dynamic_size_in_dwords + in pvr_CreatePipelineLayout()
928 reg_info->secondary_dynamic_size_in_dwords; in pvr_CreatePipelineLayout()
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_device_generated_commands.c | 645 …nir_ssa_def *reg_info = nir_load_ssbo(&b, 3, 32, param_buf, nir_iadd(&b, param_offset, nir_imul_im… in build_dgc_prepare_shader() local
646 …nir_ssa_def *upload_sgpr = nir_ubfe(&b, nir_channel(&b, reg_info, 0), nir_imm_int(&b, 0), nir_imm_… in build_dgc_prepare_shader()
647 …nir_ssa_def *inline_sgpr = nir_ubfe(&b, nir_channel(&b, reg_info, 0), nir_imm_int(&b, 16), nir_imm… in build_dgc_prepare_shader()
648 nir_ssa_def *inline_mask = nir_pack_64_2x32(&b, nir_channels(&b, reg_info, 0x6)); in build_dgc_prepare_shader()
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| /third_party/libbpf/.github/actions/build-selftests/ |
| D | vmlinux.h | 35831 const struct bpf_iter_reg *reg_info; member
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