1 /* Author(s):
2 * Connor Abbott
3 * Alyssa Rosenzweig
4 *
5 * Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
6 * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
7 * Copyright (C) 2019-2020 Collabora, Ltd.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include <stdio.h>
29 #include <stdint.h>
30 #include <stdlib.h>
31 #include <assert.h>
32 #include <inttypes.h>
33 #include <ctype.h>
34 #include <string.h>
35 #include "midgard.h"
36 #include "midgard_ops.h"
37 #include "midgard_quirks.h"
38 #include "disassemble.h"
39 #include "helpers.h"
40 #include "util/bitscan.h"
41 #include "util/half_float.h"
42 #include "util/u_math.h"
43
44 #define DEFINE_CASE(define, str) case define: { fprintf(fp, str); break; }
45
46 /* These are not mapped to hardware values, they just represent the possible
47 * implicit arg modifiers that some midgard opcodes have, which can be decoded
48 * from the opcodes via midgard_{alu,ldst,tex}_special_arg_mod() */
49 typedef enum {
50 midgard_arg_mod_none = 0,
51 midgard_arg_mod_inv,
52 midgard_arg_mod_x2,
53 } midgard_special_arg_mod;
54
55 typedef struct {
56 unsigned *midg_tags;
57 struct midgard_disasm_stats midg_stats;
58
59 /* For static analysis to ensure all registers are written at least once before
60 * use along the source code path (TODO: does this break done for complex CF?)
61 */
62
63 uint16_t midg_ever_written;
64 } disassemble_context;
65
66 /* Transform an expanded writemask (duplicated 8-bit format) into its condensed
67 * form (one bit per component) */
68
69 static inline unsigned
condense_writemask(unsigned expanded_mask,unsigned bits_per_component)70 condense_writemask(unsigned expanded_mask,
71 unsigned bits_per_component)
72 {
73 if (bits_per_component == 8) {
74 /* Duplicate every bit to go from 8 to 16-channel wrmask */
75 unsigned omask = 0;
76
77 for (unsigned i = 0; i < 8; ++i) {
78 if (expanded_mask & (1 << i))
79 omask |= (3 << (2 * i));
80 }
81
82 return omask;
83 }
84
85 unsigned slots_per_component = bits_per_component / 16;
86 unsigned max_comp = (16 * 8) / bits_per_component;
87 unsigned condensed_mask = 0;
88
89 for (unsigned i = 0; i < max_comp; i++) {
90 if (expanded_mask & (1 << (i * slots_per_component)))
91 condensed_mask |= (1 << i);
92 }
93
94 return condensed_mask;
95 }
96
97 static bool
print_alu_opcode(FILE * fp,midgard_alu_op op)98 print_alu_opcode(FILE *fp, midgard_alu_op op)
99 {
100 if (alu_opcode_props[op].name)
101 fprintf(fp, "%s", alu_opcode_props[op].name);
102 else
103 fprintf(fp, "alu_op_%02X", op);
104
105 /* For constant analysis */
106 return midgard_is_integer_op(op);
107 }
108
109 static void
print_ld_st_opcode(FILE * fp,midgard_load_store_op op)110 print_ld_st_opcode(FILE *fp, midgard_load_store_op op)
111 {
112 if (load_store_opcode_props[op].name)
113 fprintf(fp, "%s", load_store_opcode_props[op].name);
114 else
115 fprintf(fp, "ldst_op_%02X", op);
116 }
117
118 static void
validate_sampler_type(enum mali_texture_op op,enum mali_sampler_type sampler_type)119 validate_sampler_type(enum mali_texture_op op, enum mali_sampler_type sampler_type)
120 {
121 if (op == midgard_tex_op_mov || op == midgard_tex_op_barrier)
122 assert(sampler_type == 0);
123 else
124 assert(sampler_type > 0);
125 }
126
127 static void
validate_expand_mode(midgard_src_expand_mode expand_mode,midgard_reg_mode reg_mode)128 validate_expand_mode(midgard_src_expand_mode expand_mode,
129 midgard_reg_mode reg_mode)
130 {
131 switch (expand_mode) {
132 case midgard_src_passthrough:
133 break;
134
135 case midgard_src_rep_low:
136 assert(reg_mode == midgard_reg_mode_8 ||
137 reg_mode == midgard_reg_mode_16);
138 break;
139
140 case midgard_src_rep_high:
141 assert(reg_mode == midgard_reg_mode_8 ||
142 reg_mode == midgard_reg_mode_16);
143 break;
144
145 case midgard_src_swap:
146 assert(reg_mode == midgard_reg_mode_8 ||
147 reg_mode == midgard_reg_mode_16);
148 break;
149
150 case midgard_src_expand_low:
151 assert(reg_mode != midgard_reg_mode_8);
152 break;
153
154 case midgard_src_expand_high:
155 assert(reg_mode != midgard_reg_mode_8);
156 break;
157
158 case midgard_src_expand_low_swap:
159 assert(reg_mode == midgard_reg_mode_16);
160 break;
161
162 case midgard_src_expand_high_swap:
163 assert(reg_mode == midgard_reg_mode_16);
164 break;
165
166 default:
167 unreachable("Invalid expand mode");
168 break;
169 }
170 }
171
172 static void
print_alu_reg(disassemble_context * ctx,FILE * fp,unsigned reg,bool is_write)173 print_alu_reg(disassemble_context *ctx, FILE *fp, unsigned reg, bool is_write)
174 {
175 unsigned uniform_reg = 23 - reg;
176 bool is_uniform = false;
177
178 /* For r8-r15, it could be a work or uniform. We distinguish based on
179 * the fact work registers are ALWAYS written before use, but uniform
180 * registers are NEVER written before use. */
181
182 if ((reg >= 8 && reg < 16) && !(ctx->midg_ever_written & (1 << reg)))
183 is_uniform = true;
184
185 /* r16-r23 are always uniform */
186
187 if (reg >= 16 && reg <= 23)
188 is_uniform = true;
189
190 /* Update the uniform count appropriately */
191
192 if (is_uniform)
193 ctx->midg_stats.uniform_count =
194 MAX2(uniform_reg + 1, ctx->midg_stats.uniform_count);
195
196 if (reg == REGISTER_UNUSED || reg == REGISTER_UNUSED + 1)
197 fprintf(fp, "TMP%u", reg - REGISTER_UNUSED);
198 else if (reg == REGISTER_TEXTURE_BASE || reg == REGISTER_TEXTURE_BASE + 1)
199 fprintf(fp, "%s%u", is_write ? "AT" : "TA", reg - REGISTER_TEXTURE_BASE);
200 else if (reg == REGISTER_LDST_BASE || reg == REGISTER_LDST_BASE + 1)
201 fprintf(fp, "AL%u", reg - REGISTER_LDST_BASE);
202 else if (is_uniform)
203 fprintf(fp, "U%u", uniform_reg);
204 else if (reg == 31 && !is_write)
205 fprintf(fp, "PC_SP");
206 else
207 fprintf(fp, "R%u", reg);
208 }
209
210 static void
print_ldst_write_reg(FILE * fp,unsigned reg)211 print_ldst_write_reg(FILE *fp, unsigned reg)
212 {
213 switch (reg) {
214 case 26:
215 case 27:
216 fprintf(fp, "AL%u", reg - REGISTER_LDST_BASE);
217 break;
218 case 28:
219 case 29:
220 fprintf(fp, "AT%u", reg - REGISTER_TEXTURE_BASE);
221 break;
222 case 31:
223 fprintf(fp, "PC_SP");
224 break;
225 default:
226 fprintf(fp, "R%d", reg);
227 break;
228 }
229 }
230
231 static void
print_ldst_read_reg(FILE * fp,unsigned reg)232 print_ldst_read_reg(FILE *fp, unsigned reg)
233 {
234 switch (reg) {
235 case 0:
236 case 1:
237 fprintf(fp, "AL%u", reg);
238 break;
239 case 2:
240 fprintf(fp, "PC_SP");
241 break;
242 case 3:
243 fprintf(fp, "LOCAL_STORAGE_PTR");
244 break;
245 case 4:
246 fprintf(fp, "LOCAL_THREAD_ID");
247 break;
248 case 5:
249 fprintf(fp, "GROUP_ID");
250 break;
251 case 6:
252 fprintf(fp, "GLOBAL_THREAD_ID");
253 break;
254 case 7:
255 fprintf(fp, "0");
256 break;
257 default:
258 unreachable("Invalid load/store register read");
259 }
260 }
261
262 static void
print_tex_reg(FILE * fp,unsigned reg,bool is_write)263 print_tex_reg(FILE *fp, unsigned reg, bool is_write)
264 {
265 char *str = is_write ? "TA" : "AT";
266 int select = reg & 1;
267
268 switch (reg) {
269 case 0:
270 case 1:
271 fprintf(fp, "R%d", select);
272 break;
273 case 26:
274 case 27:
275 fprintf(fp, "AL%d", select);
276 break;
277 case 28:
278 case 29:
279 fprintf(fp, "%s%d", str, select);
280 break;
281 default:
282 unreachable("Invalid texture register");
283 }
284 }
285
286
287 static char *srcmod_names_int[4] = {
288 ".sext",
289 ".zext",
290 ".replicate",
291 ".lshift",
292 };
293
294 static char *argmod_names[3] = {
295 "",
296 ".inv",
297 ".x2",
298 };
299
300 static char *index_format_names[4] = {
301 "",
302 ".u64",
303 ".u32",
304 ".s32"
305 };
306
307 static void
print_alu_outmod(FILE * fp,unsigned outmod,bool is_int,bool half)308 print_alu_outmod(FILE *fp, unsigned outmod, bool is_int, bool half)
309 {
310 if (is_int && !half) {
311 assert(outmod == midgard_outmod_keeplo);
312 return;
313 }
314
315 if (!is_int && half)
316 fprintf(fp, ".shrink");
317
318 mir_print_outmod(fp, outmod, is_int);
319 }
320
321 /* arg == 0 (dest), arg == 1 (src1), arg == 2 (src2) */
322 static midgard_special_arg_mod
midgard_alu_special_arg_mod(midgard_alu_op op,unsigned arg)323 midgard_alu_special_arg_mod(midgard_alu_op op, unsigned arg) {
324 midgard_special_arg_mod mod = midgard_arg_mod_none;
325
326 switch (op) {
327 case midgard_alu_op_ishladd:
328 case midgard_alu_op_ishlsub:
329 if (arg == 1) mod = midgard_arg_mod_x2;
330 break;
331
332 default:
333 break;
334 }
335
336 return mod;
337 }
338
339 static void
print_quad_word(FILE * fp,uint32_t * words,unsigned tabs)340 print_quad_word(FILE *fp, uint32_t *words, unsigned tabs)
341 {
342 unsigned i;
343
344 for (i = 0; i < 4; i++)
345 fprintf(fp, "0x%08X%s ", words[i], i == 3 ? "" : ",");
346
347 fprintf(fp, "\n");
348 }
349
350 static const char components[16] = "xyzwefghijklmnop";
351
352 static int
bits_for_mode(midgard_reg_mode mode)353 bits_for_mode(midgard_reg_mode mode)
354 {
355 switch (mode) {
356 case midgard_reg_mode_8:
357 return 8;
358 case midgard_reg_mode_16:
359 return 16;
360 case midgard_reg_mode_32:
361 return 32;
362 case midgard_reg_mode_64:
363 return 64;
364 default:
365 unreachable("Invalid reg mode");
366 return 0;
367 }
368 }
369
370 static int
bits_for_mode_halved(midgard_reg_mode mode,bool half)371 bits_for_mode_halved(midgard_reg_mode mode, bool half)
372 {
373 unsigned bits = bits_for_mode(mode);
374
375 if (half)
376 bits >>= 1;
377
378 return bits;
379 }
380
381 static void
print_vec_selectors_64(FILE * fp,unsigned swizzle,midgard_reg_mode reg_mode,midgard_src_expand_mode expand_mode,unsigned selector_offset,uint8_t mask)382 print_vec_selectors_64(FILE *fp, unsigned swizzle,
383 midgard_reg_mode reg_mode,
384 midgard_src_expand_mode expand_mode,
385 unsigned selector_offset, uint8_t mask)
386 {
387 bool expands = INPUT_EXPANDS(expand_mode);
388
389 unsigned comp_skip = expands ? 1 : 2;
390 unsigned mask_bit = 0;
391 for (unsigned i = selector_offset; i < 4; i += comp_skip, mask_bit += 4) {
392 if (!(mask & (1 << mask_bit))) continue;
393
394 unsigned a = (swizzle >> (i * 2)) & 3;
395
396 if (INPUT_EXPANDS(expand_mode)) {
397 if (expand_mode == midgard_src_expand_high)
398 a += 2;
399
400 fprintf(fp, "%c", components[a / 2]);
401 continue;
402 }
403
404 unsigned b = (swizzle >> ((i+1) * 2)) & 3;
405
406 /* Normally we're adjacent, but if there's an issue,
407 * don't make it ambiguous */
408
409 if (b == a + 1)
410 fprintf(fp, "%c", a >> 1 ? 'Y' : 'X');
411 else
412 fprintf(fp, "[%c%c]", components[a], components[b]);
413 }
414 }
415
416 static void
print_vec_selectors(FILE * fp,unsigned swizzle,midgard_reg_mode reg_mode,unsigned selector_offset,uint8_t mask,unsigned * mask_offset)417 print_vec_selectors(FILE *fp, unsigned swizzle,
418 midgard_reg_mode reg_mode,
419 unsigned selector_offset, uint8_t mask,
420 unsigned *mask_offset)
421 {
422 assert(reg_mode != midgard_reg_mode_64);
423
424 unsigned mask_skip = MAX2(bits_for_mode(reg_mode) / 16, 1);
425
426 bool is_vec16 = reg_mode == midgard_reg_mode_8;
427
428 for (unsigned i = 0; i < 4; i++, *mask_offset += mask_skip) {
429 if (!(mask & (1 << *mask_offset))) continue;
430
431 unsigned c = (swizzle >> (i * 2)) & 3;
432
433 /* Vec16 has two components per swizzle selector. */
434 if (is_vec16)
435 c *= 2;
436
437 c += selector_offset;
438
439 fprintf(fp, "%c", components[c]);
440 if (is_vec16)
441 fprintf(fp, "%c", components[c+1]);
442 }
443 }
444
445 static void
print_vec_swizzle(FILE * fp,unsigned swizzle,midgard_src_expand_mode expand,midgard_reg_mode mode,uint8_t mask)446 print_vec_swizzle(FILE *fp, unsigned swizzle,
447 midgard_src_expand_mode expand,
448 midgard_reg_mode mode,
449 uint8_t mask)
450 {
451 unsigned bits = bits_for_mode_halved(mode, INPUT_EXPANDS(expand));
452
453 /* Swizzle selectors are divided in two halves that are always
454 * mirrored, the only difference is the starting component offset.
455 * The number represents an offset into the components[] array. */
456 unsigned first_half = 0;
457 unsigned second_half = (128 / bits) / 2; /* only used for 8 and 16-bit */
458
459 switch (expand) {
460 case midgard_src_passthrough:
461 if (swizzle == 0xE4) return; /* identity swizzle */
462 break;
463
464 case midgard_src_expand_low:
465 second_half /= 2;
466 break;
467
468 case midgard_src_expand_high:
469 first_half = second_half;
470 second_half += second_half / 2;
471 break;
472
473 /* The rest of the cases are only used for 8 and 16-bit */
474
475 case midgard_src_rep_low:
476 second_half = 0;
477 break;
478
479 case midgard_src_rep_high:
480 first_half = second_half;
481 break;
482
483 case midgard_src_swap:
484 first_half = second_half;
485 second_half = 0;
486 break;
487
488 case midgard_src_expand_low_swap:
489 first_half = second_half / 2;
490 second_half = 0;
491 break;
492
493 case midgard_src_expand_high_swap:
494 first_half = second_half + second_half / 2;
495 break;
496
497 default:
498 unreachable("Invalid expand mode");
499 break;
500 }
501
502 fprintf(fp, ".");
503
504 /* Vec2 are weird so we use a separate function to simplify things. */
505 if (mode == midgard_reg_mode_64) {
506 print_vec_selectors_64(fp, swizzle, mode, expand, first_half, mask);
507 return;
508 }
509
510 unsigned mask_offs = 0;
511 print_vec_selectors(fp, swizzle, mode, first_half, mask, &mask_offs);
512 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16)
513 print_vec_selectors(fp, swizzle, mode, second_half, mask, &mask_offs);
514 }
515
516 static void
print_scalar_constant(FILE * fp,unsigned src_binary,const midgard_constants * consts,midgard_scalar_alu * alu)517 print_scalar_constant(FILE *fp, unsigned src_binary,
518 const midgard_constants *consts,
519 midgard_scalar_alu *alu)
520 {
521 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
522 assert(consts != NULL);
523
524 fprintf(fp, "#");
525 mir_print_constant_component(fp, consts, src->component,
526 src->full ?
527 midgard_reg_mode_32 : midgard_reg_mode_16,
528 false, src->mod, alu->op);
529 }
530
531 static void
print_vector_constants(FILE * fp,unsigned src_binary,const midgard_constants * consts,midgard_vector_alu * alu)532 print_vector_constants(FILE *fp, unsigned src_binary,
533 const midgard_constants *consts,
534 midgard_vector_alu *alu)
535 {
536 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
537 bool expands = INPUT_EXPANDS(src->expand_mode);
538 unsigned bits = bits_for_mode_halved(alu->reg_mode, expands);
539 unsigned max_comp = (sizeof(*consts) * 8) / bits;
540 unsigned comp_mask, num_comp = 0;
541
542 assert(consts);
543 assert(max_comp <= 16);
544
545 comp_mask = effective_writemask(alu->op, condense_writemask(alu->mask, bits));
546 num_comp = util_bitcount(comp_mask);
547
548 if (num_comp > 1)
549 fprintf(fp, "<");
550 else
551 fprintf(fp, "#");
552
553 bool first = true;
554
555 for (unsigned i = 0; i < max_comp; ++i) {
556 if (!(comp_mask & (1 << i))) continue;
557
558 unsigned c = (src->swizzle >> (i * 2)) & 3;
559
560 if (bits == 16 && !expands) {
561 bool upper = i >= 4;
562
563 switch (src->expand_mode) {
564 case midgard_src_passthrough:
565 c += upper * 4;
566 break;
567 case midgard_src_rep_low:
568 break;
569 case midgard_src_rep_high:
570 c += 4;
571 break;
572 case midgard_src_swap:
573 c += !upper * 4;
574 break;
575 default:
576 unreachable("invalid expand mode");
577 break;
578 }
579 } else if (bits == 32 && !expands) {
580 /* Implicitly ok */
581 } else if (bits == 64 && !expands) {
582 /* Implicitly ok */
583 } else if (bits == 8 && !expands) {
584 bool upper = i >= 8;
585
586 unsigned index = (i >> 1) & 3;
587 unsigned base = (src->swizzle >> (index * 2)) & 3;
588 c = base * 2;
589
590 switch (src->expand_mode) {
591 case midgard_src_passthrough:
592 c += upper * 8;
593 break;
594 case midgard_src_rep_low:
595 break;
596 case midgard_src_rep_high:
597 c += 8;
598 break;
599 case midgard_src_swap:
600 c += !upper * 8;
601 break;
602 default:
603 unreachable("invalid expand mode");
604 break;
605 }
606
607 /* We work on twos, actually */
608 if (i & 1)
609 c++;
610 }
611
612 if (first)
613 first = false;
614 else
615 fprintf(fp, ", ");
616
617 mir_print_constant_component(fp, consts, c, alu->reg_mode,
618 expands, src->mod, alu->op);
619 }
620
621 if (num_comp > 1)
622 fprintf(fp, ">");
623 }
624
625 static void
print_srcmod(FILE * fp,bool is_int,bool expands,unsigned mod,bool scalar)626 print_srcmod(FILE *fp, bool is_int, bool expands, unsigned mod, bool scalar)
627 {
628 /* Modifiers change meaning depending on the op's context */
629
630 if (is_int) {
631 if (expands)
632 fprintf(fp, "%s", srcmod_names_int[mod]);
633 } else {
634 if (mod & MIDGARD_FLOAT_MOD_ABS)
635 fprintf(fp, ".abs");
636 if (mod & MIDGARD_FLOAT_MOD_NEG)
637 fprintf(fp, ".neg");
638 if (expands)
639 fprintf(fp, ".widen");
640 }
641 }
642
643 static void
print_vector_src(disassemble_context * ctx,FILE * fp,unsigned src_binary,midgard_reg_mode mode,unsigned reg,midgard_shrink_mode shrink_mode,uint8_t src_mask,bool is_int,midgard_special_arg_mod arg_mod)644 print_vector_src(disassemble_context *ctx, FILE *fp, unsigned src_binary,
645 midgard_reg_mode mode, unsigned reg,
646 midgard_shrink_mode shrink_mode,
647 uint8_t src_mask, bool is_int,
648 midgard_special_arg_mod arg_mod)
649 {
650 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
651
652 validate_expand_mode(src->expand_mode, mode);
653
654 print_alu_reg(ctx, fp, reg, false);
655
656 print_vec_swizzle(fp, src->swizzle, src->expand_mode, mode, src_mask);
657
658 fprintf(fp, "%s", argmod_names[arg_mod]);
659
660 print_srcmod(fp, is_int, INPUT_EXPANDS(src->expand_mode), src->mod, false);
661 }
662
663 static uint16_t
decode_vector_imm(unsigned src2_reg,unsigned imm)664 decode_vector_imm(unsigned src2_reg, unsigned imm)
665 {
666 uint16_t ret;
667 ret = src2_reg << 11;
668 ret |= (imm & 0x7) << 8;
669 ret |= (imm >> 3) & 0xFF;
670 return ret;
671 }
672
673 static void
print_immediate(FILE * fp,uint16_t imm,bool is_instruction_int)674 print_immediate(FILE *fp, uint16_t imm, bool is_instruction_int)
675 {
676 if (is_instruction_int)
677 fprintf(fp, "#%u", imm);
678 else
679 fprintf(fp, "#%g", _mesa_half_to_float(imm));
680 }
681
682 static void
update_dest(disassemble_context * ctx,unsigned reg)683 update_dest(disassemble_context *ctx, unsigned reg)
684 {
685 /* We should record writes as marking this as a work register. Store
686 * the max register in work_count; we'll add one at the end */
687
688 if (reg < 16) {
689 ctx->midg_stats.work_count = MAX2(reg, ctx->midg_stats.work_count);
690 ctx->midg_ever_written |= (1 << reg);
691 }
692 }
693
694 static void
print_dest(disassemble_context * ctx,FILE * fp,unsigned reg)695 print_dest(disassemble_context *ctx, FILE *fp, unsigned reg)
696 {
697 update_dest(ctx, reg);
698 print_alu_reg(ctx, fp, reg, true);
699 }
700
701 /* For 16-bit+ masks, we read off from the 8-bit mask field. For 16-bit (vec8),
702 * it's just one bit per channel, easy peasy. For 32-bit (vec4), it's one bit
703 * per channel with one duplicate bit in the middle. For 64-bit (vec2), it's
704 * one-bit per channel with _3_ duplicate bits in the middle. Basically, just
705 * subdividing the 128-bit word in 16-bit increments. For 64-bit, we uppercase
706 * the mask to make it obvious what happened */
707
708 static void
print_alu_mask(FILE * fp,uint8_t mask,unsigned bits,midgard_shrink_mode shrink_mode)709 print_alu_mask(FILE *fp, uint8_t mask, unsigned bits, midgard_shrink_mode shrink_mode)
710 {
711 /* Skip 'complete' masks */
712
713 if (shrink_mode == midgard_shrink_mode_none && mask == 0xFF)
714 return;
715
716 fprintf(fp, ".");
717
718 unsigned skip = MAX2(bits / 16, 1);
719 bool tripped = false;
720
721 /* To apply an upper destination shrink_mode, we "shift" the alphabet.
722 * E.g. with an upper shrink_mode on 32-bit, instead of xyzw, print efgh.
723 * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
724
725 const char *alphabet = components;
726
727 if (shrink_mode == midgard_shrink_mode_upper) {
728 assert(bits != 8);
729 alphabet += (128 / bits);
730 }
731
732 for (unsigned i = 0; i < 8; i += skip) {
733 bool a = (mask & (1 << i)) != 0;
734
735 for (unsigned j = 1; j < skip; ++j) {
736 bool dupe = (mask & (1 << (i + j))) != 0;
737 tripped |= (dupe != a);
738 }
739
740 if (a) {
741 /* TODO: handle shrinking from 16-bit */
742 unsigned comp_idx = bits == 8 ? i * 2 : i;
743 char c = alphabet[comp_idx / skip];
744
745 fprintf(fp, "%c", c);
746 if (bits == 8)
747 fprintf(fp, "%c", alphabet[comp_idx+1]);
748 }
749 }
750
751 if (tripped)
752 fprintf(fp, " /* %X */", mask);
753 }
754
755 /* TODO: 16-bit mode */
756 static void
print_ldst_mask(FILE * fp,unsigned mask,unsigned swizzle)757 print_ldst_mask(FILE *fp, unsigned mask, unsigned swizzle) {
758 fprintf(fp, ".");
759
760 for (unsigned i = 0; i < 4; ++i) {
761 bool write = (mask & (1 << i)) != 0;
762 unsigned c = (swizzle >> (i * 2)) & 3;
763 /* We can't omit the swizzle here since many ldst ops have a
764 * combined swizzle/writemask, and it would be ambiguous to not
765 * print the masked-out components. */
766 fprintf(fp, "%c", write ? components[c] : '~');
767 }
768 }
769
770 static void
print_tex_mask(FILE * fp,unsigned mask,bool upper)771 print_tex_mask(FILE *fp, unsigned mask, bool upper)
772 {
773 if (mask == 0xF) {
774 if (upper)
775 fprintf(fp, "'");
776
777 return;
778 }
779
780 fprintf(fp, ".");
781
782 for (unsigned i = 0; i < 4; ++i) {
783 bool a = (mask & (1 << i)) != 0;
784 if (a)
785 fprintf(fp, "%c", components[i + (upper ? 4 : 0)]);
786 }
787 }
788
789 static void
print_vector_field(disassemble_context * ctx,FILE * fp,const char * name,uint16_t * words,uint16_t reg_word,const midgard_constants * consts,unsigned tabs,bool verbose)790 print_vector_field(disassemble_context *ctx, FILE *fp, const char *name,
791 uint16_t *words, uint16_t reg_word,
792 const midgard_constants *consts, unsigned tabs, bool verbose)
793 {
794 midgard_reg_info *reg_info = (midgard_reg_info *)®_word;
795 midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
796 midgard_reg_mode mode = alu_field->reg_mode;
797 midgard_alu_op op = alu_field->op;
798 unsigned shrink_mode = alu_field->shrink_mode;
799 bool is_int = midgard_is_integer_op(op);
800 bool is_int_out = midgard_is_integer_out_op(op);
801
802 if (verbose)
803 fprintf(fp, "%s.", name);
804
805 bool is_instruction_int = print_alu_opcode(fp, alu_field->op);
806
807 /* Print lane width */
808 fprintf(fp, ".%c%d", is_int_out ? 'i' : 'f', bits_for_mode(mode));
809
810 fprintf(fp, " ");
811
812 /* Mask denoting status of 8-lanes */
813 uint8_t mask = alu_field->mask;
814
815 /* First, print the destination */
816 print_dest(ctx, fp, reg_info->out_reg);
817
818 if (shrink_mode != midgard_shrink_mode_none) {
819 bool shrinkable = (mode != midgard_reg_mode_8);
820 bool known = shrink_mode != 0x3; /* Unused value */
821
822 if (!(shrinkable && known))
823 fprintf(fp, "/* do%u */ ", shrink_mode);
824 }
825
826 /* Instructions like fdot4 do *not* replicate, ensure the
827 * mask is of only a single component */
828
829 unsigned rep = GET_CHANNEL_COUNT(alu_opcode_props[op].props);
830
831 if (rep) {
832 unsigned comp_mask = condense_writemask(mask, bits_for_mode(mode));
833 unsigned num_comp = util_bitcount(comp_mask);
834 if (num_comp != 1)
835 fprintf(fp, "/* err too many components */");
836 }
837 print_alu_mask(fp, mask, bits_for_mode(mode), shrink_mode);
838
839 /* Print output modifiers */
840
841 print_alu_outmod(fp, alu_field->outmod, is_int_out, shrink_mode != midgard_shrink_mode_none);
842
843 /* Mask out unused components based on the writemask, but don't mask out
844 * components that are used for interlane instructions like fdot3. */
845 uint8_t src_mask =
846 rep ? expand_writemask(mask_of(rep), util_logbase2(128 / bits_for_mode(mode))) : mask;
847
848 fprintf(fp, ", ");
849
850 if (reg_info->src1_reg == REGISTER_CONSTANT)
851 print_vector_constants(fp, alu_field->src1, consts, alu_field);
852 else {
853 midgard_special_arg_mod argmod = midgard_alu_special_arg_mod(op, 1);
854 print_vector_src(ctx, fp, alu_field->src1, mode, reg_info->src1_reg,
855 shrink_mode, src_mask, is_int, argmod);
856 }
857
858 fprintf(fp, ", ");
859
860 if (reg_info->src2_imm) {
861 uint16_t imm = decode_vector_imm(reg_info->src2_reg, alu_field->src2 >> 2);
862 print_immediate(fp, imm, is_instruction_int);
863 } else if (reg_info->src2_reg == REGISTER_CONSTANT) {
864 print_vector_constants(fp, alu_field->src2, consts, alu_field);
865 } else {
866 midgard_special_arg_mod argmod = midgard_alu_special_arg_mod(op, 2);
867 print_vector_src(ctx, fp, alu_field->src2, mode, reg_info->src2_reg,
868 shrink_mode, src_mask, is_int, argmod);
869 }
870
871 ctx->midg_stats.instruction_count++;
872 fprintf(fp, "\n");
873 }
874
875 static void
print_scalar_src(disassemble_context * ctx,FILE * fp,bool is_int,unsigned src_binary,unsigned reg)876 print_scalar_src(disassemble_context *ctx, FILE *fp, bool is_int, unsigned src_binary, unsigned reg)
877 {
878 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
879
880 print_alu_reg(ctx, fp, reg, false);
881
882 unsigned c = src->component;
883
884 if (src->full) {
885 assert((c & 1) == 0);
886 c >>= 1;
887 }
888
889 fprintf(fp, ".%c", components[c]);
890
891 print_srcmod(fp, is_int, !src->full, src->mod, true);
892 }
893
894 static uint16_t
decode_scalar_imm(unsigned src2_reg,unsigned imm)895 decode_scalar_imm(unsigned src2_reg, unsigned imm)
896 {
897 uint16_t ret;
898 ret = src2_reg << 11;
899 ret |= (imm & 3) << 9;
900 ret |= (imm & 4) << 6;
901 ret |= (imm & 0x38) << 2;
902 ret |= imm >> 6;
903 return ret;
904 }
905
906 static void
print_scalar_field(disassemble_context * ctx,FILE * fp,const char * name,uint16_t * words,uint16_t reg_word,const midgard_constants * consts,unsigned tabs,bool verbose)907 print_scalar_field(disassemble_context *ctx, FILE *fp, const char *name,
908 uint16_t *words, uint16_t reg_word,
909 const midgard_constants *consts, unsigned tabs, bool verbose)
910 {
911 midgard_reg_info *reg_info = (midgard_reg_info *)®_word;
912 midgard_scalar_alu *alu_field = (midgard_scalar_alu *) words;
913 bool is_int = midgard_is_integer_op(alu_field->op);
914 bool is_int_out = midgard_is_integer_out_op(alu_field->op);
915 bool full = alu_field->output_full;
916
917 if (alu_field->reserved)
918 fprintf(fp, "scalar ALU reserved bit set\n");
919
920 if (verbose)
921 fprintf(fp, "%s.", name);
922
923 bool is_instruction_int = print_alu_opcode(fp, alu_field->op);
924
925 /* Print lane width, in this case the lane width is always 32-bit, but
926 * we print it anyway to make it consistent with the other instructions. */
927 fprintf(fp, ".%c32", is_int_out ? 'i' : 'f');
928
929 fprintf(fp, " ");
930
931 print_dest(ctx, fp, reg_info->out_reg);
932 unsigned c = alu_field->output_component;
933
934 if (full) {
935 assert((c & 1) == 0);
936 c >>= 1;
937 }
938
939 fprintf(fp, ".%c", components[c]);
940
941 print_alu_outmod(fp, alu_field->outmod, is_int_out, !full);
942
943 fprintf(fp, ", ");
944
945 if (reg_info->src1_reg == REGISTER_CONSTANT)
946 print_scalar_constant(fp, alu_field->src1, consts, alu_field);
947 else
948 print_scalar_src(ctx, fp, is_int, alu_field->src1, reg_info->src1_reg);
949
950 fprintf(fp, ", ");
951
952 if (reg_info->src2_imm) {
953 uint16_t imm = decode_scalar_imm(reg_info->src2_reg,
954 alu_field->src2);
955 print_immediate(fp, imm, is_instruction_int);
956 } else if (reg_info->src2_reg == REGISTER_CONSTANT) {
957 print_scalar_constant(fp, alu_field->src2, consts, alu_field);
958 } else
959 print_scalar_src(ctx, fp, is_int, alu_field->src2, reg_info->src2_reg);
960
961 ctx->midg_stats.instruction_count++;
962 fprintf(fp, "\n");
963 }
964
965 static void
print_branch_op(FILE * fp,unsigned op)966 print_branch_op(FILE *fp, unsigned op)
967 {
968 switch (op) {
969 case midgard_jmp_writeout_op_branch_uncond:
970 fprintf(fp, "uncond.");
971 break;
972
973 case midgard_jmp_writeout_op_branch_cond:
974 fprintf(fp, "cond.");
975 break;
976
977 case midgard_jmp_writeout_op_writeout:
978 fprintf(fp, "write.");
979 break;
980
981 case midgard_jmp_writeout_op_tilebuffer_pending:
982 fprintf(fp, "tilebuffer.");
983 break;
984
985 case midgard_jmp_writeout_op_discard:
986 fprintf(fp, "discard.");
987 break;
988
989 default:
990 fprintf(fp, "unk%u.", op);
991 break;
992 }
993 }
994
995 static void
print_branch_cond(FILE * fp,int cond)996 print_branch_cond(FILE *fp, int cond)
997 {
998 switch (cond) {
999 case midgard_condition_write0:
1000 fprintf(fp, "write0");
1001 break;
1002
1003 case midgard_condition_false:
1004 fprintf(fp, "false");
1005 break;
1006
1007 case midgard_condition_true:
1008 fprintf(fp, "true");
1009 break;
1010
1011 case midgard_condition_always:
1012 fprintf(fp, "always");
1013 break;
1014
1015 default:
1016 fprintf(fp, "unk%X", cond);
1017 break;
1018 }
1019 }
1020
1021 static const char *
function_call_mode(enum midgard_call_mode mode)1022 function_call_mode(enum midgard_call_mode mode)
1023 {
1024 switch (mode) {
1025 case midgard_call_mode_default: return "";
1026 case midgard_call_mode_call: return ".call";
1027 case midgard_call_mode_return: return ".return";
1028 default: return ".reserved";
1029 }
1030 }
1031
1032 static bool
print_compact_branch_writeout_field(disassemble_context * ctx,FILE * fp,uint16_t word)1033 print_compact_branch_writeout_field(disassemble_context *ctx, FILE *fp, uint16_t word)
1034 {
1035 midgard_jmp_writeout_op op = word & 0x7;
1036 ctx->midg_stats.instruction_count++;
1037
1038 switch (op) {
1039 case midgard_jmp_writeout_op_branch_uncond: {
1040 midgard_branch_uncond br_uncond;
1041 memcpy((char *) &br_uncond, (char *) &word, sizeof(br_uncond));
1042 fprintf(fp, "br.uncond%s ", function_call_mode(br_uncond.call_mode));
1043
1044 if (br_uncond.offset >= 0)
1045 fprintf(fp, "+");
1046
1047 fprintf(fp, "%d -> %s", br_uncond.offset,
1048 midgard_tag_props[br_uncond.dest_tag].name);
1049 fprintf(fp, "\n");
1050
1051 return br_uncond.offset >= 0;
1052 }
1053
1054 case midgard_jmp_writeout_op_branch_cond:
1055 case midgard_jmp_writeout_op_writeout:
1056 case midgard_jmp_writeout_op_discard:
1057 default: {
1058 midgard_branch_cond br_cond;
1059 memcpy((char *) &br_cond, (char *) &word, sizeof(br_cond));
1060
1061 fprintf(fp, "br.");
1062
1063 print_branch_op(fp, br_cond.op);
1064 print_branch_cond(fp, br_cond.cond);
1065
1066 fprintf(fp, " ");
1067
1068 if (br_cond.offset >= 0)
1069 fprintf(fp, "+");
1070
1071 fprintf(fp, "%d -> %s", br_cond.offset,
1072 midgard_tag_props[br_cond.dest_tag].name);
1073 fprintf(fp, "\n");
1074
1075 return br_cond.offset >= 0;
1076 }
1077 }
1078
1079 return false;
1080 }
1081
1082 static bool
print_extended_branch_writeout_field(disassemble_context * ctx,FILE * fp,uint8_t * words,unsigned next)1083 print_extended_branch_writeout_field(disassemble_context *ctx, FILE *fp, uint8_t *words,
1084 unsigned next)
1085 {
1086 midgard_branch_extended br;
1087 memcpy((char *) &br, (char *) words, sizeof(br));
1088
1089 fprintf(fp, "brx%s.", function_call_mode(br.call_mode));
1090
1091 print_branch_op(fp, br.op);
1092
1093 /* Condition codes are a LUT in the general case, but simply repeated 8 times for single-channel conditions.. Check this. */
1094
1095 bool single_channel = true;
1096
1097 for (unsigned i = 0; i < 16; i += 2) {
1098 single_channel &= (((br.cond >> i) & 0x3) == (br.cond & 0x3));
1099 }
1100
1101 if (single_channel)
1102 print_branch_cond(fp, br.cond & 0x3);
1103 else
1104 fprintf(fp, "lut%X", br.cond);
1105
1106 fprintf(fp, " ");
1107
1108 if (br.offset >= 0)
1109 fprintf(fp, "+");
1110
1111 fprintf(fp, "%d -> %s\n", br.offset,
1112 midgard_tag_props[br.dest_tag].name);
1113
1114 unsigned I = next + br.offset * 4;
1115
1116 if (ctx->midg_tags[I] && ctx->midg_tags[I] != br.dest_tag) {
1117 fprintf(fp, "\t/* XXX TAG ERROR: jumping to %s but tagged %s \n",
1118 midgard_tag_props[br.dest_tag].name,
1119 midgard_tag_props[ctx->midg_tags[I]].name);
1120 }
1121
1122 ctx->midg_tags[I] = br.dest_tag;
1123
1124 ctx->midg_stats.instruction_count++;
1125 return br.offset >= 0;
1126 }
1127
1128 static unsigned
num_alu_fields_enabled(uint32_t control_word)1129 num_alu_fields_enabled(uint32_t control_word)
1130 {
1131 unsigned ret = 0;
1132
1133 if ((control_word >> 17) & 1)
1134 ret++;
1135
1136 if ((control_word >> 19) & 1)
1137 ret++;
1138
1139 if ((control_word >> 21) & 1)
1140 ret++;
1141
1142 if ((control_word >> 23) & 1)
1143 ret++;
1144
1145 if ((control_word >> 25) & 1)
1146 ret++;
1147
1148 return ret;
1149 }
1150
1151 static bool
print_alu_word(disassemble_context * ctx,FILE * fp,uint32_t * words,unsigned num_quad_words,unsigned tabs,unsigned next,bool verbose)1152 print_alu_word(disassemble_context *ctx, FILE *fp, uint32_t *words,
1153 unsigned num_quad_words, unsigned tabs, unsigned next,
1154 bool verbose)
1155 {
1156 uint32_t control_word = words[0];
1157 uint16_t *beginning_ptr = (uint16_t *)(words + 1);
1158 unsigned num_fields = num_alu_fields_enabled(control_word);
1159 uint16_t *word_ptr = beginning_ptr + num_fields;
1160 unsigned num_words = 2 + num_fields;
1161 const midgard_constants *consts = NULL;
1162 bool branch_forward = false;
1163
1164 if ((control_word >> 17) & 1)
1165 num_words += 3;
1166
1167 if ((control_word >> 19) & 1)
1168 num_words += 2;
1169
1170 if ((control_word >> 21) & 1)
1171 num_words += 3;
1172
1173 if ((control_word >> 23) & 1)
1174 num_words += 2;
1175
1176 if ((control_word >> 25) & 1)
1177 num_words += 3;
1178
1179 if ((control_word >> 26) & 1)
1180 num_words += 1;
1181
1182 if ((control_word >> 27) & 1)
1183 num_words += 3;
1184
1185 if (num_quad_words > (num_words + 7) / 8) {
1186 assert(num_quad_words == (num_words + 15) / 8);
1187 //Assume that the extra quadword is constants
1188 consts = (midgard_constants *)(words + (4 * num_quad_words - 4));
1189 }
1190
1191 if ((control_word >> 16) & 1)
1192 fprintf(fp, "unknown bit 16 enabled\n");
1193
1194 if ((control_word >> 17) & 1) {
1195 print_vector_field(ctx, fp, "vmul", word_ptr, *beginning_ptr, consts, tabs, verbose);
1196 beginning_ptr += 1;
1197 word_ptr += 3;
1198 }
1199
1200 if ((control_word >> 18) & 1)
1201 fprintf(fp, "unknown bit 18 enabled\n");
1202
1203 if ((control_word >> 19) & 1) {
1204 print_scalar_field(ctx, fp, "sadd", word_ptr, *beginning_ptr, consts, tabs, verbose);
1205 beginning_ptr += 1;
1206 word_ptr += 2;
1207 }
1208
1209 if ((control_word >> 20) & 1)
1210 fprintf(fp, "unknown bit 20 enabled\n");
1211
1212 if ((control_word >> 21) & 1) {
1213 print_vector_field(ctx, fp, "vadd", word_ptr, *beginning_ptr, consts, tabs, verbose);
1214 beginning_ptr += 1;
1215 word_ptr += 3;
1216 }
1217
1218 if ((control_word >> 22) & 1)
1219 fprintf(fp, "unknown bit 22 enabled\n");
1220
1221 if ((control_word >> 23) & 1) {
1222 print_scalar_field(ctx, fp, "smul", word_ptr, *beginning_ptr, consts, tabs, verbose);
1223 beginning_ptr += 1;
1224 word_ptr += 2;
1225 }
1226
1227 if ((control_word >> 24) & 1)
1228 fprintf(fp, "unknown bit 24 enabled\n");
1229
1230 if ((control_word >> 25) & 1) {
1231 print_vector_field(ctx, fp, "lut", word_ptr, *beginning_ptr, consts, tabs, verbose);
1232 word_ptr += 3;
1233 }
1234
1235 if ((control_word >> 26) & 1) {
1236 branch_forward |= print_compact_branch_writeout_field(ctx, fp, *word_ptr);
1237 word_ptr += 1;
1238 }
1239
1240 if ((control_word >> 27) & 1) {
1241 branch_forward |= print_extended_branch_writeout_field(ctx, fp, (uint8_t *) word_ptr, next);
1242 word_ptr += 3;
1243 }
1244
1245 if (consts)
1246 fprintf(fp, "uconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
1247 consts->u32[0], consts->u32[1],
1248 consts->u32[2], consts->u32[3]);
1249
1250 return branch_forward;
1251 }
1252
1253 /* TODO: how can we use this now that we know that these params can't be known
1254 * before run time in every single case? Maybe just use it in the cases we can? */
1255 UNUSED static void
print_varying_parameters(FILE * fp,midgard_load_store_word * word)1256 print_varying_parameters(FILE *fp, midgard_load_store_word *word)
1257 {
1258 midgard_varying_params p = midgard_unpack_varying_params(*word);
1259
1260 /* If a varying, there are qualifiers */
1261 if (p.flat_shading)
1262 fprintf(fp, ".flat");
1263
1264 if (p.perspective_correction)
1265 fprintf(fp, ".correction");
1266
1267 if (p.centroid_mapping)
1268 fprintf(fp, ".centroid");
1269
1270 if (p.interpolate_sample)
1271 fprintf(fp, ".sample");
1272
1273 switch (p.modifier) {
1274 case midgard_varying_mod_perspective_y:
1275 fprintf(fp, ".perspectivey");
1276 break;
1277 case midgard_varying_mod_perspective_z:
1278 fprintf(fp, ".perspectivez");
1279 break;
1280 case midgard_varying_mod_perspective_w:
1281 fprintf(fp, ".perspectivew");
1282 break;
1283 default:
1284 unreachable("invalid varying modifier");
1285 break;
1286 }
1287 }
1288
1289 static bool
is_op_varying(unsigned op)1290 is_op_varying(unsigned op)
1291 {
1292 switch (op) {
1293 case midgard_op_st_vary_16:
1294 case midgard_op_st_vary_32:
1295 case midgard_op_st_vary_32i:
1296 case midgard_op_st_vary_32u:
1297 case midgard_op_ld_vary_16:
1298 case midgard_op_ld_vary_32:
1299 case midgard_op_ld_vary_32i:
1300 case midgard_op_ld_vary_32u:
1301 return true;
1302 }
1303
1304 return false;
1305 }
1306
1307 static bool
is_op_attribute(unsigned op)1308 is_op_attribute(unsigned op)
1309 {
1310 switch (op) {
1311 case midgard_op_ld_attr_16:
1312 case midgard_op_ld_attr_32:
1313 case midgard_op_ld_attr_32i:
1314 case midgard_op_ld_attr_32u:
1315 return true;
1316 }
1317
1318 return false;
1319 }
1320
1321 /* Helper to print integer well-formatted, but only when non-zero. */
1322 static void
midgard_print_sint(FILE * fp,int n)1323 midgard_print_sint(FILE *fp, int n)
1324 {
1325 if (n > 0)
1326 fprintf(fp, " + 0x%X", n);
1327 else if (n < 0)
1328 fprintf(fp, " - 0x%X", -n);
1329 }
1330
1331 static void
update_stats(signed * stat,unsigned address)1332 update_stats(signed *stat, unsigned address)
1333 {
1334 if (*stat >= 0)
1335 *stat = MAX2(*stat, address + 1);
1336 }
1337
1338 static void
print_load_store_instr(disassemble_context * ctx,FILE * fp,uint64_t data,bool verbose)1339 print_load_store_instr(disassemble_context *ctx, FILE *fp, uint64_t data, bool verbose)
1340 {
1341 midgard_load_store_word *word = (midgard_load_store_word *) &data;
1342
1343 print_ld_st_opcode(fp, word->op);
1344
1345 if (word->op == midgard_op_trap) {
1346 fprintf(fp, " 0x%X\n", word->signed_offset);
1347 return;
1348 }
1349
1350 /* Print opcode modifiers */
1351
1352 if (OP_USES_ATTRIB(word->op)) {
1353 /* Print non-default attribute tables */
1354 bool default_secondary =
1355 (word->op == midgard_op_st_vary_32) ||
1356 (word->op == midgard_op_st_vary_16) ||
1357 (word->op == midgard_op_st_vary_32u) ||
1358 (word->op == midgard_op_st_vary_32i) ||
1359 (word->op == midgard_op_ld_vary_32) ||
1360 (word->op == midgard_op_ld_vary_16) ||
1361 (word->op == midgard_op_ld_vary_32u) ||
1362 (word->op == midgard_op_ld_vary_32i);
1363
1364 bool default_primary =
1365 (word->op == midgard_op_ld_attr_32) ||
1366 (word->op == midgard_op_ld_attr_16) ||
1367 (word->op == midgard_op_ld_attr_32u) ||
1368 (word->op == midgard_op_ld_attr_32i);
1369
1370 bool has_default = (default_secondary || default_primary);
1371 bool is_secondary = (word->index_format >> 1);
1372
1373 if (has_default && (is_secondary != default_secondary))
1374 fprintf(fp, ".%s", is_secondary ? "secondary" : "primary");
1375 } else if (word->op == midgard_op_ld_cubemap_coords || OP_IS_PROJECTION(word->op))
1376 fprintf(fp, ".%s", word->bitsize_toggle ? "f32" : "f16");
1377
1378 fprintf(fp, " ");
1379
1380 /* src/dest register */
1381
1382 if (!OP_IS_STORE(word->op)) {
1383 print_ldst_write_reg(fp, word->reg);
1384
1385 /* Some opcodes don't have a swizzable src register, and
1386 * instead the swizzle is applied before the result is written
1387 * to the dest reg. For these ops, we combine the writemask
1388 * with the swizzle to display them in the disasm compactly. */
1389 unsigned swizzle = word->swizzle;
1390 if ((OP_IS_REG2REG_LDST(word->op) &&
1391 word->op != midgard_op_lea &&
1392 word->op != midgard_op_lea_image) || OP_IS_ATOMIC(word->op))
1393 swizzle = 0xE4;
1394 print_ldst_mask(fp, word->mask, swizzle);
1395 } else {
1396 uint8_t mask =
1397 (word->mask & 0x1) |
1398 ((word->mask & 0x2) << 1) |
1399 ((word->mask & 0x4) << 2) |
1400 ((word->mask & 0x8) << 3);
1401 mask |= mask << 1;
1402 print_ldst_read_reg(fp, word->reg);
1403 print_vec_swizzle(fp, word->swizzle, midgard_src_passthrough,
1404 midgard_reg_mode_32, mask);
1405 }
1406
1407 /* ld_ubo args */
1408 if (OP_IS_UBO_READ(word->op)) {
1409 if (word->signed_offset & 1) { /* buffer index imm */
1410 unsigned imm = midgard_unpack_ubo_index_imm(*word);
1411 fprintf(fp, ", %u", imm);
1412 } else { /* buffer index from reg */
1413 fprintf(fp, ", ");
1414 print_ldst_read_reg(fp, word->arg_reg);
1415 fprintf(fp, ".%c", components[word->arg_comp]);
1416 }
1417
1418 fprintf(fp, ", ");
1419 print_ldst_read_reg(fp, word->index_reg);
1420 fprintf(fp, ".%c", components[word->index_comp]);
1421 if (word->index_shift)
1422 fprintf(fp, " << %u", word->index_shift);
1423 midgard_print_sint(fp, UNPACK_LDST_UBO_OFS(word->signed_offset));
1424 }
1425
1426 /* mem addr expression */
1427 if (OP_HAS_ADDRESS(word->op)) {
1428 fprintf(fp, ", ");
1429 bool first = true;
1430
1431 /* Skip printing zero */
1432 if (word->arg_reg != 7 || verbose) {
1433 print_ldst_read_reg(fp, word->arg_reg);
1434 fprintf(fp, ".u%d.%c",
1435 word->bitsize_toggle ? 64 : 32, components[word->arg_comp]);
1436 first = false;
1437 }
1438
1439 if ((word->op < midgard_op_atomic_cmpxchg ||
1440 word->op > midgard_op_atomic_cmpxchg64_be) &&
1441 word->index_reg != 0x7) {
1442 if (!first)
1443 fprintf(fp, " + ");
1444
1445 print_ldst_read_reg(fp, word->index_reg);
1446 fprintf(fp, "%s.%c",
1447 index_format_names[word->index_format],
1448 components[word->index_comp]);
1449 if (word->index_shift)
1450 fprintf(fp, " << %u", word->index_shift);
1451 }
1452
1453 midgard_print_sint(fp, word->signed_offset);
1454 }
1455
1456 /* src reg for reg2reg ldst opcodes */
1457 if (OP_IS_REG2REG_LDST(word->op)) {
1458 fprintf(fp, ", ");
1459 print_ldst_read_reg(fp, word->arg_reg);
1460 print_vec_swizzle(fp, word->swizzle, midgard_src_passthrough,
1461 midgard_reg_mode_32, 0xFF);
1462 }
1463
1464 /* atomic ops encode the source arg where the ldst swizzle would be. */
1465 if (OP_IS_ATOMIC(word->op)) {
1466 unsigned src = (word->swizzle >> 2) & 0x7;
1467 unsigned src_comp = word->swizzle & 0x3;
1468 fprintf(fp, ", ");
1469 print_ldst_read_reg(fp, src);
1470 fprintf(fp, ".%c", components[src_comp]);
1471 }
1472
1473 /* CMPXCHG encodes the extra comparison arg where the index reg would be. */
1474 if (word->op >= midgard_op_atomic_cmpxchg &&
1475 word->op <= midgard_op_atomic_cmpxchg64_be) {
1476 fprintf(fp, ", ");
1477 print_ldst_read_reg(fp, word->index_reg);
1478 fprintf(fp, ".%c", components[word->index_comp]);
1479 }
1480
1481 /* index reg for attr/vary/images, selector for ld/st_special */
1482 if (OP_IS_SPECIAL(word->op) || OP_USES_ATTRIB(word->op)) {
1483 fprintf(fp, ", ");
1484 print_ldst_read_reg(fp, word->index_reg);
1485 fprintf(fp, ".%c", components[word->index_comp]);
1486 if (word->index_shift)
1487 fprintf(fp, " << %u", word->index_shift);
1488 midgard_print_sint(fp, UNPACK_LDST_ATTRIB_OFS(word->signed_offset));
1489 }
1490
1491 /* vertex reg for attrib/varying ops, coord reg for image ops */
1492 if (OP_USES_ATTRIB(word->op)) {
1493 fprintf(fp, ", ");
1494 print_ldst_read_reg(fp, word->arg_reg);
1495
1496 if (OP_IS_IMAGE(word->op))
1497 fprintf(fp, ".u%d", word->bitsize_toggle ? 64 : 32);
1498
1499 fprintf(fp, ".%c", components[word->arg_comp]);
1500
1501 if (word->bitsize_toggle && !OP_IS_IMAGE(word->op))
1502 midgard_print_sint(fp, UNPACK_LDST_VERTEX_OFS(word->signed_offset));
1503 }
1504
1505 /* TODO: properly decode format specifier for PACK/UNPACK ops */
1506 if (OP_IS_PACK_COLOUR(word->op) || OP_IS_UNPACK_COLOUR(word->op)) {
1507 fprintf(fp, ", ");
1508 unsigned format_specifier = (word->signed_offset << 4) | word->index_shift;
1509 fprintf(fp, "0x%X", format_specifier);
1510 }
1511
1512 fprintf(fp, "\n");
1513
1514 /* Debugging stuff */
1515
1516 if (is_op_varying(word->op)) {
1517 /* Do some analysis: check if direct access */
1518
1519 if (word->index_reg == 0x7 && ctx->midg_stats.varying_count >= 0)
1520 update_stats(&ctx->midg_stats.varying_count,
1521 UNPACK_LDST_ATTRIB_OFS(word->signed_offset));
1522 else
1523 ctx->midg_stats.varying_count = -16;
1524 } else if (is_op_attribute(word->op)) {
1525 if (word->index_reg == 0x7 && ctx->midg_stats.attribute_count >= 0)
1526 update_stats(&ctx->midg_stats.attribute_count,
1527 UNPACK_LDST_ATTRIB_OFS(word->signed_offset));
1528 else
1529 ctx->midg_stats.attribute_count = -16;
1530 }
1531
1532 if (!OP_IS_STORE(word->op))
1533 update_dest(ctx, word->reg);
1534
1535 if (OP_IS_UBO_READ(word->op))
1536 update_stats(&ctx->midg_stats.uniform_buffer_count,
1537 UNPACK_LDST_UBO_OFS(word->signed_offset));
1538
1539 ctx->midg_stats.instruction_count++;
1540 }
1541
1542 static void
print_load_store_word(disassemble_context * ctx,FILE * fp,uint32_t * word,bool verbose)1543 print_load_store_word(disassemble_context *ctx, FILE *fp, uint32_t *word, bool verbose)
1544 {
1545 midgard_load_store *load_store = (midgard_load_store *) word;
1546
1547 if (load_store->word1 != 3) {
1548 print_load_store_instr(ctx, fp, load_store->word1, verbose);
1549 }
1550
1551 if (load_store->word2 != 3) {
1552 print_load_store_instr(ctx, fp, load_store->word2, verbose);
1553 }
1554 }
1555
1556 static void
print_texture_reg_select(FILE * fp,uint8_t u,unsigned base)1557 print_texture_reg_select(FILE *fp, uint8_t u, unsigned base)
1558 {
1559 midgard_tex_register_select sel;
1560 memcpy(&sel, &u, sizeof(u));
1561
1562 print_tex_reg(fp, base + sel.select, false);
1563
1564 unsigned component = sel.component;
1565
1566 /* Use the upper half in half-reg mode */
1567 if (sel.upper) {
1568 assert(!sel.full);
1569 component += 4;
1570 }
1571
1572 fprintf(fp, ".%c.%d", components[component], sel.full ? 32 : 16);
1573
1574 assert(sel.zero == 0);
1575 }
1576
1577 static void
print_texture_format(FILE * fp,int format)1578 print_texture_format(FILE *fp, int format)
1579 {
1580 /* Act like a modifier */
1581 fprintf(fp, ".");
1582
1583 switch (format) {
1584 DEFINE_CASE(1, "1d");
1585 DEFINE_CASE(2, "2d");
1586 DEFINE_CASE(3, "3d");
1587 DEFINE_CASE(0, "cube");
1588
1589 default:
1590 unreachable("Bad format");
1591 }
1592 }
1593
1594 static bool
midgard_op_has_helpers(unsigned op)1595 midgard_op_has_helpers(unsigned op)
1596 {
1597 switch (op) {
1598 case midgard_tex_op_normal:
1599 case midgard_tex_op_derivative:
1600 return true;
1601 default:
1602 return false;
1603 }
1604 }
1605
1606 static void
print_texture_op(FILE * fp,unsigned op)1607 print_texture_op(FILE *fp, unsigned op)
1608 {
1609 if (tex_opcode_props[op].name)
1610 fprintf(fp, "%s", tex_opcode_props[op].name);
1611 else
1612 fprintf(fp, "tex_op_%02X", op);
1613 }
1614
1615 static bool
texture_op_takes_bias(unsigned op)1616 texture_op_takes_bias(unsigned op)
1617 {
1618 return op == midgard_tex_op_normal;
1619 }
1620
1621 static char
sampler_type_name(enum mali_sampler_type t)1622 sampler_type_name(enum mali_sampler_type t)
1623 {
1624 switch (t) {
1625 case MALI_SAMPLER_FLOAT:
1626 return 'f';
1627 case MALI_SAMPLER_UNSIGNED:
1628 return 'u';
1629 case MALI_SAMPLER_SIGNED:
1630 return 'i';
1631 default:
1632 return '?';
1633 }
1634
1635 }
1636
1637 static void
print_texture_barrier(FILE * fp,uint32_t * word)1638 print_texture_barrier(FILE *fp, uint32_t *word)
1639 {
1640 midgard_texture_barrier_word *barrier = (midgard_texture_barrier_word *) word;
1641
1642 if (barrier->type != TAG_TEXTURE_4_BARRIER)
1643 fprintf(fp, "/* barrier tag %X != tex/bar */ ", barrier->type);
1644
1645 if (!barrier->cont)
1646 fprintf(fp, "/* cont missing? */");
1647
1648 if (!barrier->last)
1649 fprintf(fp, "/* last missing? */");
1650
1651 if (barrier->zero1)
1652 fprintf(fp, "/* zero1 = 0x%X */ ", barrier->zero1);
1653
1654 if (barrier->zero2)
1655 fprintf(fp, "/* zero2 = 0x%X */ ", barrier->zero2);
1656
1657 if (barrier->zero3)
1658 fprintf(fp, "/* zero3 = 0x%X */ ", barrier->zero3);
1659
1660 if (barrier->zero4)
1661 fprintf(fp, "/* zero4 = 0x%X */ ", barrier->zero4);
1662
1663 if (barrier->zero5)
1664 fprintf(fp, "/* zero4 = 0x%" PRIx64 " */ ", barrier->zero5);
1665
1666 if (barrier->out_of_order)
1667 fprintf(fp, ".ooo%u", barrier->out_of_order);
1668
1669 fprintf(fp, "\n");
1670 }
1671
1672 #undef DEFINE_CASE
1673
1674 static const char *
texture_mode(enum mali_texture_mode mode)1675 texture_mode(enum mali_texture_mode mode)
1676 {
1677 switch (mode) {
1678 case TEXTURE_NORMAL: return "";
1679 case TEXTURE_SHADOW: return ".shadow";
1680 case TEXTURE_GATHER_SHADOW: return ".gather.shadow";
1681 case TEXTURE_GATHER_X: return ".gatherX";
1682 case TEXTURE_GATHER_Y: return ".gatherY";
1683 case TEXTURE_GATHER_Z: return ".gatherZ";
1684 case TEXTURE_GATHER_W: return ".gatherW";
1685 default: return "unk";
1686 }
1687 }
1688
1689 static const char *
derivative_mode(enum mali_derivative_mode mode)1690 derivative_mode(enum mali_derivative_mode mode)
1691 {
1692 switch (mode) {
1693 case TEXTURE_DFDX: return ".x";
1694 case TEXTURE_DFDY: return ".y";
1695 default: return "unk";
1696 }
1697 }
1698
1699 static const char *
partial_exection_mode(enum midgard_partial_execution mode)1700 partial_exection_mode(enum midgard_partial_execution mode)
1701 {
1702 switch (mode) {
1703 case MIDGARD_PARTIAL_EXECUTION_NONE: return "";
1704 case MIDGARD_PARTIAL_EXECUTION_SKIP: return ".skip";
1705 case MIDGARD_PARTIAL_EXECUTION_KILL: return ".kill";
1706 default: return ".reserved";
1707 }
1708 }
1709
1710 static void
print_texture_word(disassemble_context * ctx,FILE * fp,uint32_t * word,unsigned tabs,unsigned in_reg_base,unsigned out_reg_base)1711 print_texture_word(disassemble_context *ctx, FILE *fp, uint32_t *word,
1712 unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
1713 {
1714 midgard_texture_word *texture = (midgard_texture_word *) word;
1715 ctx->midg_stats.helper_invocations |= midgard_op_has_helpers(texture->op);
1716 validate_sampler_type(texture->op, texture->sampler_type);
1717
1718 /* Broad category of texture operation in question */
1719 print_texture_op(fp, texture->op);
1720
1721 /* Barriers use a dramatically different code path */
1722 if (texture->op == midgard_tex_op_barrier) {
1723 print_texture_barrier(fp, word);
1724 return;
1725 } else if (texture->type == TAG_TEXTURE_4_BARRIER)
1726 fprintf (fp, "/* nonbarrier had tex/bar tag */ ");
1727 else if (texture->type == TAG_TEXTURE_4_VTX)
1728 fprintf (fp, ".vtx");
1729
1730 if (texture->op == midgard_tex_op_derivative)
1731 fprintf(fp, "%s", derivative_mode(texture->mode));
1732 else
1733 fprintf(fp, "%s", texture_mode(texture->mode));
1734
1735 /* Specific format in question */
1736 print_texture_format(fp, texture->format);
1737
1738 /* Instruction "modifiers" parallel the ALU instructions. */
1739 fputs(partial_exection_mode(texture->exec), fp);
1740
1741 if (texture->out_of_order)
1742 fprintf(fp, ".ooo%u", texture->out_of_order);
1743
1744 fprintf(fp, " ");
1745 print_tex_reg(fp, out_reg_base + texture->out_reg_select, true);
1746 print_tex_mask(fp, texture->mask, texture->out_upper);
1747 fprintf(fp, ".%c%d", texture->sampler_type == MALI_SAMPLER_FLOAT ? 'f' : 'i',
1748 texture->out_full ? 32 : 16);
1749 assert(!(texture->out_full && texture->out_upper));
1750
1751 /* Output modifiers are only valid for float texture operations */
1752 if (texture->sampler_type == MALI_SAMPLER_FLOAT)
1753 mir_print_outmod(fp, texture->outmod, false);
1754
1755 fprintf(fp, ", ");
1756
1757 /* Depending on whether we read from textures directly or indirectly,
1758 * we may be able to update our analysis */
1759
1760 if (texture->texture_register) {
1761 fprintf(fp, "texture[");
1762 print_texture_reg_select(fp, texture->texture_handle, in_reg_base);
1763 fprintf(fp, "], ");
1764
1765 /* Indirect, tut tut */
1766 ctx->midg_stats.texture_count = -16;
1767 } else {
1768 fprintf(fp, "texture%u, ", texture->texture_handle);
1769 update_stats(&ctx->midg_stats.texture_count, texture->texture_handle);
1770 }
1771
1772 /* Print the type, GL style */
1773 fprintf(fp, "%csampler", sampler_type_name(texture->sampler_type));
1774
1775 if (texture->sampler_register) {
1776 fprintf(fp, "[");
1777 print_texture_reg_select(fp, texture->sampler_handle, in_reg_base);
1778 fprintf(fp, "]");
1779
1780 ctx->midg_stats.sampler_count = -16;
1781 } else {
1782 fprintf(fp, "%u", texture->sampler_handle);
1783 update_stats(&ctx->midg_stats.sampler_count, texture->sampler_handle);
1784 }
1785
1786 print_vec_swizzle(fp, texture->swizzle, midgard_src_passthrough, midgard_reg_mode_32, 0xFF);
1787
1788 fprintf(fp, ", ");
1789
1790 midgard_src_expand_mode exp =
1791 texture->in_reg_upper ? midgard_src_expand_high : midgard_src_passthrough;
1792 print_tex_reg(fp, in_reg_base + texture->in_reg_select, false);
1793 print_vec_swizzle(fp, texture->in_reg_swizzle, exp, midgard_reg_mode_32, 0xFF);
1794 fprintf(fp, ".%d", texture->in_reg_full ? 32 : 16);
1795 assert(!(texture->in_reg_full && texture->in_reg_upper));
1796
1797 /* There is *always* an offset attached. Of
1798 * course, that offset is just immediate #0 for a
1799 * GLES call that doesn't take an offset. If there
1800 * is a non-negative non-zero offset, this is
1801 * specified in immediate offset mode, with the
1802 * values in the offset_* fields as immediates. If
1803 * this is a negative offset, we instead switch to
1804 * a register offset mode, where the offset_*
1805 * fields become register triplets */
1806
1807 if (texture->offset_register) {
1808 fprintf(fp, " + ");
1809
1810 bool full = texture->offset & 1;
1811 bool select = texture->offset & 2;
1812 bool upper = texture->offset & 4;
1813 unsigned swizzle = texture->offset >> 3;
1814 midgard_src_expand_mode exp =
1815 upper ? midgard_src_expand_high : midgard_src_passthrough;
1816
1817 print_tex_reg(fp, in_reg_base + select, false);
1818 print_vec_swizzle(fp, swizzle, exp, midgard_reg_mode_32, 0xFF);
1819 fprintf(fp, ".%d", full ? 32 : 16);
1820 assert(!(texture->out_full && texture->out_upper));
1821
1822 fprintf(fp, ", ");
1823 } else if (texture->offset) {
1824 /* Only select ops allow negative immediate offsets, verify */
1825
1826 signed offset_x = (texture->offset & 0xF);
1827 signed offset_y = ((texture->offset >> 4) & 0xF);
1828 signed offset_z = ((texture->offset >> 8) & 0xF);
1829
1830 bool neg_x = offset_x < 0;
1831 bool neg_y = offset_y < 0;
1832 bool neg_z = offset_z < 0;
1833 bool any_neg = neg_x || neg_y || neg_z;
1834
1835 if (any_neg && texture->op != midgard_tex_op_fetch)
1836 fprintf(fp, "/* invalid negative */ ");
1837
1838 /* Regardless, just print the immediate offset */
1839
1840 fprintf(fp, " + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
1841 } else {
1842 fprintf(fp, ", ");
1843 }
1844
1845 char lod_operand = texture_op_takes_bias(texture->op) ? '+' : '=';
1846
1847 if (texture->lod_register) {
1848 fprintf(fp, "lod %c ", lod_operand);
1849 print_texture_reg_select(fp, texture->bias, in_reg_base);
1850 fprintf(fp, ", ");
1851
1852 if (texture->bias_int)
1853 fprintf(fp, " /* bias_int = 0x%X */", texture->bias_int);
1854 } else if (texture->op == midgard_tex_op_fetch) {
1855 /* For texel fetch, the int LOD is in the fractional place and
1856 * there is no fraction. We *always* have an explicit LOD, even
1857 * if it's zero. */
1858
1859 if (texture->bias_int)
1860 fprintf(fp, " /* bias_int = 0x%X */ ", texture->bias_int);
1861
1862 fprintf(fp, "lod = %u, ", texture->bias);
1863 } else if (texture->bias || texture->bias_int) {
1864 signed bias_int = texture->bias_int;
1865 float bias_frac = texture->bias / 256.0f;
1866 float bias = bias_int + bias_frac;
1867
1868 bool is_bias = texture_op_takes_bias(texture->op);
1869 char sign = (bias >= 0.0) ? '+' : '-';
1870 char operand = is_bias ? sign : '=';
1871
1872 fprintf(fp, "lod %c %f, ", operand, fabsf(bias));
1873 }
1874
1875 fprintf(fp, "\n");
1876
1877 /* While not zero in general, for these simple instructions the
1878 * following unknowns are zero, so we don't include them */
1879
1880 if (texture->unknown4 ||
1881 texture->unknown8) {
1882 fprintf(fp, "// unknown4 = 0x%x\n", texture->unknown4);
1883 fprintf(fp, "// unknown8 = 0x%x\n", texture->unknown8);
1884 }
1885
1886 ctx->midg_stats.instruction_count++;
1887 }
1888
1889 struct midgard_disasm_stats
disassemble_midgard(FILE * fp,uint8_t * code,size_t size,unsigned gpu_id,bool verbose)1890 disassemble_midgard(FILE *fp, uint8_t *code, size_t size, unsigned gpu_id, bool verbose)
1891 {
1892 uint32_t *words = (uint32_t *) code;
1893 unsigned num_words = size / 4;
1894 int tabs = 0;
1895
1896 bool branch_forward = false;
1897
1898 int last_next_tag = -1;
1899
1900 unsigned i = 0;
1901
1902 disassemble_context ctx = {
1903 .midg_tags = calloc(sizeof(ctx.midg_tags[0]), num_words),
1904 .midg_stats = {0},
1905 .midg_ever_written = 0,
1906 };
1907
1908 while (i < num_words) {
1909 unsigned tag = words[i] & 0xF;
1910 unsigned next_tag = (words[i] >> 4) & 0xF;
1911 unsigned num_quad_words = midgard_tag_props[tag].size;
1912
1913 if (ctx.midg_tags[i] && ctx.midg_tags[i] != tag) {
1914 fprintf(fp, "\t/* XXX: TAG ERROR branch, got %s expected %s */\n",
1915 midgard_tag_props[tag].name,
1916 midgard_tag_props[ctx.midg_tags[i]].name);
1917 }
1918
1919 ctx.midg_tags[i] = tag;
1920
1921 /* Check the tag. The idea is to ensure that next_tag is
1922 * *always* recoverable from the disassembly, such that we may
1923 * safely omit printing next_tag. To show this, we first
1924 * consider that next tags are semantically off-byone -- we end
1925 * up parsing tag n during step n+1. So, we ensure after we're
1926 * done disassembling the next tag of the final bundle is BREAK
1927 * and warn otherwise. We also ensure that the next tag is
1928 * never INVALID. Beyond that, since the last tag is checked
1929 * outside the loop, we can check one tag prior. If equal to
1930 * the current tag (which is unique), we're done. Otherwise, we
1931 * print if that tag was > TAG_BREAK, which implies the tag was
1932 * not TAG_BREAK or TAG_INVALID. But we already checked for
1933 * TAG_INVALID, so it's just if the last tag was TAG_BREAK that
1934 * we're silent. So we throw in a print for break-next on at
1935 * the end of the bundle (if it's not the final bundle, which
1936 * we already check for above), disambiguating this case as
1937 * well. Hence in all cases we are unambiguous, QED. */
1938
1939 if (next_tag == TAG_INVALID)
1940 fprintf(fp, "\t/* XXX: invalid next tag */\n");
1941
1942 if (last_next_tag > TAG_BREAK && last_next_tag != tag) {
1943 fprintf(fp, "\t/* XXX: TAG ERROR sequence, got %s expexted %s */\n",
1944 midgard_tag_props[tag].name,
1945 midgard_tag_props[last_next_tag].name);
1946 }
1947
1948 last_next_tag = next_tag;
1949
1950 /* Tags are unique in the following way:
1951 *
1952 * INVALID, BREAK, UNKNOWN_*: verbosely printed
1953 * TEXTURE_4_BARRIER: verified by barrier/!barrier op
1954 * TEXTURE_4_VTX: .vtx tag printed
1955 * TEXTURE_4: tetxure lack of barriers or .vtx
1956 * TAG_LOAD_STORE_4: only load/store
1957 * TAG_ALU_4/8/12/16: by number of instructions/constants
1958 * TAG_ALU_4_8/12/16_WRITEOUT: ^^ with .writeout tag
1959 */
1960
1961 switch (tag) {
1962 case TAG_TEXTURE_4_VTX ... TAG_TEXTURE_4_BARRIER: {
1963 bool interpipe_aliasing =
1964 midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
1965
1966 print_texture_word(&ctx, fp, &words[i], tabs,
1967 interpipe_aliasing ? 0 : REG_TEX_BASE,
1968 interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
1969 break;
1970 }
1971
1972 case TAG_LOAD_STORE_4:
1973 print_load_store_word(&ctx, fp, &words[i], verbose);
1974 break;
1975
1976 case TAG_ALU_4 ... TAG_ALU_16_WRITEOUT:
1977 branch_forward = print_alu_word(&ctx, fp, &words[i], num_quad_words, tabs, i + 4*num_quad_words, verbose);
1978
1979 /* TODO: infer/verify me */
1980 if (tag >= TAG_ALU_4_WRITEOUT)
1981 fprintf(fp, "writeout\n");
1982
1983 break;
1984
1985 default:
1986 fprintf(fp, "Unknown word type %u:\n", words[i] & 0xF);
1987 num_quad_words = 1;
1988 print_quad_word(fp, &words[i], tabs);
1989 fprintf(fp, "\n");
1990 break;
1991 }
1992
1993 /* We are parsing per bundle anyway. Add before we start
1994 * breaking out so we don't miss the final bundle. */
1995
1996 ctx.midg_stats.bundle_count++;
1997 ctx.midg_stats.quadword_count += num_quad_words;
1998
1999 /* Include a synthetic "break" instruction at the end of the
2000 * bundle to signify that if, absent a branch, the shader
2001 * execution will stop here. Stop disassembly at such a break
2002 * based on a heuristic */
2003
2004 if (next_tag == TAG_BREAK) {
2005 if (branch_forward) {
2006 fprintf(fp, "break\n");
2007 } else {
2008 fprintf(fp, "\n");
2009 break;
2010 }
2011 }
2012
2013 fprintf(fp, "\n");
2014
2015 i += 4 * num_quad_words;
2016 }
2017
2018 if (last_next_tag != TAG_BREAK) {
2019 fprintf(fp, "/* XXX: shader ended with tag %s */\n",
2020 midgard_tag_props[last_next_tag].name);
2021 }
2022
2023 free(ctx.midg_tags);
2024
2025 /* We computed work_count as max_work_registers, so add one to get the
2026 * count. If no work registers are written, you still have one work
2027 * reported, which is exactly what the hardware expects */
2028
2029 ctx.midg_stats.work_count++;
2030
2031 return ctx.midg_stats;
2032 }
2033