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Searched refs:rsrc1 (Results 1 – 12 of 12) sorted by relevance

/third_party/mesa3d/src/amd/compiler/
Daco_statistics.cpp103 BlockCycleEstimator::resource rsrc1; member
192 if (perf.rsrc1 != resource_count) { in use_resources()
193 res_available[(int)perf.rsrc1] = cur_cycle + perf.cost1; in use_resources()
194 res_usage[(int)perf.rsrc1] += perf.cost1; in use_resources()
206 if (perf.rsrc1 != resource_count) in cycles_until_res_available()
207 cost = MAX2(cost, res_available[(int)perf.rsrc1] - cur_cycle); in cycles_until_res_available()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; in code_object_to_config() local
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1); in code_object_to_config()
102 out_config->rsrc1 = rsrc1; in code_object_to_config()
198 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) / in si_create_compute_state_async()
207 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); in si_create_compute_state_async()
581 radeon_emit(config->rsrc1); in si_switch_compute_shader()
587 config->rsrc1, config->rsrc2); in si_switch_compute_shader()
Dsi_state_shaders.cpp697 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_ls()
1106 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | in si_shader_gs() local
1120 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_gs()
1124 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1); in si_shader_gs()
1735 uint32_t rsrc1 = in si_shader_vs() local
1749 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_vs()
1759 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1); in si_shader_vs()
2010 uint32_t rsrc1 = in si_shader_ps() local
2016 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_ps()
2019 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1); in si_shader_ps()
Dsi_state_draw.cpp833 radeon_emit(ls_current->config.rsrc1); in si_emit_derived_tess_state()
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader.c1691 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) | in radv_postprocess_config()
1697 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); in radv_postprocess_config()
1706 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1717 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1744 config_out->rsrc1 |= in radv_postprocess_config()
1750 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1777 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1783 config_out->rsrc1 |= S_00B228_MEM_ORDERED(1); in radv_postprocess_config()
1788 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
1793 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10); in radv_postprocess_config()
[all …]
Dradv_shader.h518 uint32_t rsrc1; member
Dradv_pipeline.c5656 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_vs()
5734 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_es()
5754 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_ls()
5774 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_ngg()
5952 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_hs()
5958 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_hs()
6147 radeon_emit(cs, gs->config.rsrc1); in radv_pipeline_emit_hw_gs()
6157 radeon_emit(cs, gs->config.rsrc1); in radv_pipeline_emit_hw_gs()
6401 radeon_emit(cs, ps->config.rsrc1); in radv_pipeline_emit_fragment_shader()
7176 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_emit_hw_cs()
Dradv_device.c4234 uint32_t rsrc1; in radv_emit_compute_scratch() local
4240 rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32); in radv_emit_compute_scratch()
4243 rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1); in radv_emit_compute_scratch()
4245 rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1); in radv_emit_compute_scratch()
4259 radeon_emit(cs, rsrc1); in radv_emit_compute_scratch()
4503 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32); in radv_update_preamble_cs() local
4506 rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1); in radv_update_preamble_cs()
4508 rsrc1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1); in radv_update_preamble_cs()
4511 map[1] = rsrc1; in radv_update_preamble_cs()
Dradv_cmd_buffer.c3221 uint32_t rsrc1 = vs_shader->config.rsrc1; in emit_prolog_regs() local
3222 if (chip < GFX10 && G_00B228_SGPRS(prolog->rsrc1) > G_00B228_SGPRS(vs_shader->config.rsrc1)) in emit_prolog_regs()
3223 rsrc1 = (rsrc1 & C_00B228_SGPRS) | (prolog->rsrc1 & ~C_00B228_SGPRS); in emit_prolog_regs()
3228 assert(G_00B848_VGPRS(vs_shader->config.rsrc1) >= G_00B848_VGPRS(prolog->rsrc1)); in emit_prolog_regs()
3249 radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1); in emit_prolog_regs()
3251 assert(rsrc1 == vs_shader->config.rsrc1); in emit_prolog_regs()
/third_party/mesa3d/src/amd/common/
Dac_binary.h48 unsigned rsrc1; member
Dac_binary.c61 conf->rsrc1 = value; in ac_parse_shader_binary_config()
Dac_rtld.c557 assert(config->rsrc1 == 0 && config->rsrc2 == 0); in ac_rtld_read_config()
558 config->rsrc1 = c.rsrc1; in ac_rtld_read_config()