| /third_party/mesa3d/src/intel/compiler/ |
| D | test_simd_selection.cpp | 39 const bool spilled = true; variable
99 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
164 brw_simd_mark_compiled(SIMD8, prog_data, spilled); in TEST_F()
166 brw_simd_mark_compiled(SIMD16, prog_data, spilled); in TEST_F()
168 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
256 brw_simd_mark_compiled(SIMD8, prog_data, spilled); in TEST_F()
268 brw_simd_mark_compiled(SIMD16, prog_data, spilled); in TEST_F()
297 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
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| D | brw_simd_selection.c | 133 brw_simd_mark_compiled(unsigned simd, struct brw_cs_prog_data *prog_data, bool spilled) in brw_simd_mark_compiled() argument
140 if (spilled) { in brw_simd_mark_compiled()
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| D | brw_private.h | 45 bool spilled);
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| D | brw_fs_reg_allocate.cpp | 1198 bool spilled = false; in assign_regs() local
1230 spilled = true; in assign_regs()
1235 if (spilled) in assign_regs()
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
| D | regalloc.c | 248 alu_dest->ssa.spilled = true; in ppir_update_spilled_src()
423 if (reg->spilled) { in ppir_regalloc_choose_spill_node()
488 chosen->spilled = true; in ppir_regalloc_choose_spill_node()
535 static bool ppir_regalloc_prog_try(ppir_compiler *comp, bool *spilled) in ppir_regalloc_prog_try() argument
562 *spilled = false; in ppir_regalloc_prog_try()
574 *spilled = true; in ppir_regalloc_prog_try()
610 bool spilled = false; in ppir_regalloc_prog() local
629 while (!ppir_regalloc_prog_try(comp, &spilled)) in ppir_regalloc_prog()
630 if (!spilled) in ppir_regalloc_prog()
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| D | ppir.h | 229 bool spilled; member
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| /third_party/mesa3d/src/panfrost/midgard/ |
| D | midgard_ra.c | 449 allocate_registers(compiler_context *ctx, bool *spilled) in allocate_registers() argument
719 *spilled = !lcra_solve(l); in allocate_registers()
1146 bool spilled = false; in mir_ra() local
1156 if (spilled) { in mir_ra()
1181 l = allocate_registers(ctx, &spilled); in mir_ra()
1182 } while(spilled && ((iter_count--) > 0)); in mir_ra()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_spill.cpp | 513 for (auto spilled : ctx.spills_exit[block_idx - 1]) { in init_live_in_vars() local
514 auto it = next_use_distances.find(spilled.first); in init_live_in_vars()
521 if (it->second.first >= loop_end || ctx.remat.count(spilled.first)) { in init_live_in_vars()
522 ctx.spills_entry[block_idx][spilled.first] = spilled.second; in init_live_in_vars()
523 spilled_registers += spilled.first; in init_live_in_vars()
524 loop_demand -= spilled.first; in init_live_in_vars()
889 auto spilled = ctx.spills_exit[pred_idx].find(var); in add_coupling_code() local
890 if (spilled != ctx.spills_exit[pred_idx].end()) { in add_coupling_code()
891 if (spilled->second != def_spill_id) in add_coupling_code()
892 ctx.add_affinity(def_spill_id, spilled->second); in add_coupling_code()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | README.txt | 77 Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
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| /third_party/mesa3d/docs/relnotes/ |
| D | 9.0.3.rst | 148 - i965/vs: Try again when we've successfully spilled a reg.
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| D | 19.3.0.rst | 811 - aco: fix transitive affinities of spilled variables
816 - aco: don't add interferences between spilled phi operands
818 - aco: ensure that spilled VGPR reloads are done after p_logical_start
3359 - lima/ppir: print register index and components number for spilled
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_ra.c | 2595 bool spilled = false; in ir3_ra() local
2607 spilled = true; in ir3_ra()
2661 if (spilled) { in ir3_ra()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 992 bool *spilled = ctx->spilled_arrays; // assumed calloc:ed in choose_spill_arrays() local
1002 if (!spilled[i] && size > largest) { in choose_spill_arrays()
1008 spilled[largest_index] = true; in choose_spill_arrays()
1023 …map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled) in map_tgsi_reg_index_to_r600_gpr() argument
1032 *spilled = true; in map_tgsi_reg_index_to_r600_gpr()
1037 *spilled = false; in map_tgsi_reg_index_to_r600_gpr()
1050 *spilled = false; in map_tgsi_reg_index_to_r600_gpr()
1176 bool spilled; in tgsi_declaration() local
1179 &spilled); in tgsi_declaration()
1181 if (!spilled) { in tgsi_declaration()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 494 // RIP is not spilled anywhere for now, so stick to 32-bit alignment
503 // Since RBP will never be spilled, stick to a 32 alignment to save
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| D | X86CallingConv.td | 737 /// values are spilled on the stack.
790 /// values are spilled on the stack.
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| D | README.txt | 873 Likewise, we isel "x<<1" into "add reg,reg". If reg is spilled, this should
883 However, if xmm2 gets spilled, we end up with really ugly code like this:
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| D | README-SSE.txt | 245 Now consider if the ... code caused xmm1 to get spilled. This might produce
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 306 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
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| D | PPCInstrInfo.td | 1384 // spilled), so we'll need to scavenge a register for it.
2749 // spilled), so we'll need to scavenge a register for it.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | TargetOpcodes.def | 125 /// to prevent the stack guard value or address from being spilled to the
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | README.txt | 22 the top-bits known to be sign or zero extended. If spilled, we should be able
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| D | ARMInstrFormats.td | 226 // explicit operand so that it can be register-allocated and spilled
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/docs/ |
| D | DESIGN.rst | 668 In this case, some register needs to be forcibly spilled to the stack and
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/ |
| D | DESIGN.rst | 668 In this case, some register needs to be forcibly spilled to the stack and
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| /third_party/libwebsockets/minimal-examples/api-tests/api-test-fts/ |
| D | the-picture-of-dorian-gray.txt | 5422 spilled from the cup she was holding. The carnations of the painting
6958 blood had been spilled. What could atone for that? Ah! for that there
7040 and stained with dark rings of spilled liquor. Some Malays were
8029 you had done more than one?" asked his companion as he spilled into his
8456 brighter, and more like blood newly spilled. Then he trembled. Had it
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