1 /* 2 * Copyright (c) 2022 Chipsea Technologies (Shenzhen) Corp., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef PPG_CS1262_SPI_H 10 #define PPG_CS1262_SPI_H 11 12 #include "hdf_types.h" 13 #include "sensor_platform_if.h" 14 /***************************************** TYPEDEF ******************************************/ 15 typedef enum { 16 CS1262_REG_BIT_RESET = 0, 17 CS1262_REG_BIT_SET = 1, 18 } Cs1262BitStatus; 19 20 typedef struct { 21 uint16_t regAddr; 22 union { 23 uint16_t regVal; 24 uint16_t *regValGroup; 25 }; 26 uint16_t regLen; 27 } Cs1262RegGroup; 28 29 typedef struct { 30 uint32_t reserve : 2; 31 uint32_t adc_data : 22; 32 uint32_t tl : 2; 33 uint32_t rx : 2; 34 uint32_t phaseGroup : 4; 35 } Cs1262FifoVal; 36 37 /****************************************** DEFINE ******************************************/ 38 // lock reg 39 #define CS1262_LOCK 0x0000 40 // unlock reg 41 #define CS1262_UN_LOCK1 0x0059 42 #define CS1262_UN_LOCK2 0x0016 43 #define CS1262_UN_LOCK3 0x0088 44 45 /****************************************** OFFSET ******************************************/ 46 // PRF 47 #define PRF_START_BIT (0x0000) 48 // REG WR PROT 49 #define LOCK_REG_OFFSET (0x01u << 0) 50 51 // RESET CON 52 #define FIFORST_REG_OFFSET (0x01u << 1) 53 #define TERST_REG_OFFSET (0x01u << 2) 54 #define ADCRST_REG_OFFSET (0x01u << 3) 55 56 // IER IFR 57 #define INT_MODE_TRIGER (0 << 15) // 0 trigger 58 59 #define LED_WARN_IER_OFFSET 5 60 #define REG_ERR_IER_OFFSET 4 61 #define TS_RDY_IER_OFFSET 3 62 #define DATA_RDY_IER_OFFSET 2 63 #define THR_DET_IER_OFFSET 1 64 #define FIFO_RDY_IER_OFFSET 0 65 66 #define LED_WARN_IFR_OFFSET 5 67 #define REG_ERR_IFR_OFFSET 4 68 #define TS_RDY_IFR_OFFSET 3 69 #define DATA_RDY_IFR_OFFSET 2 70 #define THR_DET_IFR_OFFSET 1 71 #define FIFO_RDY_IFR_OFFSET 0 72 73 #define IFR_RDY_FLAG 0x0001 74 // TE CTRL 75 #define PRF_START_OFFSET (0x01u << 0) 76 77 // FIFO STATE 78 #define FIFO_FULL_OFFSET (0x01u << 12) 79 #define FIFO_EMPTY_OFFSET (0x01u << 11) 80 #define FIFO_NUM_OFFSET 0x3FF 81 82 // RESET OFFSET 83 #define CS1262_FIFO_RST_OFFSET 1 84 #define CS1262_TE_RST_OFFSET 2 85 #define CS1262_ADC_RST_OFFSET 3 86 87 /******************************************* REGS *******************************************/ 88 // SYS_BA 89 #define CS1262_SYS_BA (0x0000) 90 #define CS1262_WRPROT_REG (CS1262_SYS_BA + 0x00) 91 #define CS1262_CLOCK_REG (CS1262_SYS_BA + 0x01) 92 #define CS1262_RSTCON_REG (CS1262_SYS_BA + 0x02) 93 #define CS1262_IER_REG (CS1262_SYS_BA + 0x03) 94 #define CS1262_IFR_REG (CS1262_SYS_BA + 0x04) 95 #define CS1262_SYS_STATE_REG (CS1262_SYS_BA + 0x05) 96 // TL_BA 97 #define CS1262_TL_BA (0x0010) 98 // TX_BA 99 #define CS1262_TX_BA (0x0050) 100 // RX_BA 101 #define CS1262_RX_BA (0x0070) 102 // TE_BA 103 #define CS1262_TE_BA (0x00E0) 104 #define CS1262_TE_CTRL_REG (CS1262_TE_BA + 0x00) 105 // TE_BA 106 #define CS1262_WEAR_BA (0x0120) 107 // FIFO & ADC 108 #define CS1262_ADC_BA (0x140) 109 #define CS1262_FIFO_DATA_REG (CS1262_ADC_BA + 0x00) 110 #define CS1262_FIFO_STATE_REG (CS1262_ADC_BA + 0x01) 111 #define CS1262_FIFO_OFFSET_REG (CS1262_ADC_BA + 0x02) 112 // ID_BA 113 #define CS1262_ID_BA (0x1F0) 114 #define CS1262_CHIP_ID1_REG (CS1262_ID_BA + 0x01) 115 116 #define CS1262_ENTER_DEEPSLEEP_CMD 0x08C4 117 #define CS1262_EXIT_DEEPSLEEP_CMD 0x08C1 118 #define CS1262_CHIP_REST_CMD 0xC2 119 120 /****************************************** DEFINE ******************************************/ 121 #define CS1262_SPI_NOCHECK_SINGLEWRITE 0x95 122 #define CS1262_SPI_CKSUNCHECK_SINGLEWRITE 0x96 // checksum for single write 123 #define CS1262_SPI_NOCHECK_CONTINUOUSWRITE 0x99 124 #define CS1262_SPI_CKSUNCHECK_CONTINUOUSWRITE 0x9A // checksum for continuous write 125 126 #define CS1262_SPI_NOCHECK_SINGLEREAD 0x65 127 #define CS1262_SPI_CKSUNCHECK_SINGLEREAD 0x66 // checksum for single read 128 #define CS1262_SPI_NOCHECK_CONTINUOUSREAD 0x69 129 #define CS1262_SPI_CKSUNCHECK_CONTINUOUSREAD 0x6A // checksum for continuous read 130 131 #define CS1262_SPI_ACK_ADDR 0xA3 132 #define CS1262_SPI_NACK_ADDR 0xA3 133 #define CS1262_SPI_ACK_DATA 0xA5 134 #define CS1262_SPI_NACK_DATA 0xAA 135 136 #define CS1262_SPI_DUMMY_DATA 0x00 137 /*********************************** function prototypes *************************************/ 138 int32_t Cs1262ReadRegs(uint16_t regAddr, uint16_t *dataBuf, uint16_t dataLen); 139 int32_t Cs1262WriteReg(uint16_t regAddr, uint16_t data); 140 int32_t Cs1262WriteRegs(uint16_t regAddr, uint16_t *dataBuf, uint16_t dataLen); 141 int32_t Cs1262WriteRegbit(uint16_t regAddr, uint16_t setbit, Cs1262BitStatus bitval); 142 int32_t Cs1262WriteData(uint8_t *data, uint16_t dataLen); 143 int32_t Cs1262WriteGroup(Cs1262RegGroup *regGroup, uint16_t groupLen); 144 int32_t Cs1262ReadFifoReg(Cs1262FifoVal *fifoBuf, uint16_t fifoLen); 145 int32_t Cs1262InitSpi(struct SensorBusCfg *busCfg); 146 void Cs1262ReleaseSpi(struct SensorBusCfg *busCfg); 147 #endif /* CS1262_SPI_H */ 148