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1Rockchip RK3288 specific extensions to the Analogix Display Port
2================================
3
4Required properties:
5- compatible: "rockchip,rk3288-dp",
6	      "rockchip,rk3399-edp";
7
8- reg: physical base address of the controller and length
9
10- clocks: from common clock binding: handle to dp clock.
11	  of memory mapped region.
12
13- clock-names: from common clock binding:
14	       Required elements: "dp" "pclk"
15
16- resets: Must contain an entry for each entry in reset-names.
17	  See ../reset/reset.txt for details.
18
19- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
20- pinctrl-0: pin-control mode. should be <&edp_hpd>
21
22- reset-names: Must include the name "dp"
23
24- rockchip,grf: this soc should set GRF regs, so need get grf here.
25
26- ports: there are 2 port nodes with endpoint definitions as defined in
27  Documentation/devicetree/bindings/media/video-interfaces.txt.
28    Port 0: contained 2 endpoints, connecting to the output of vop.
29    Port 1: contained 1 endpoint, connecting to the input of panel.
30
31Optional property for different chips:
32- clocks: from common clock binding: handle to grf_vio clock.
33
34- clock-names: from common clock binding:
35	       Required elements: "grf"
36
37For the below properties, please refer to Analogix DP binding document:
38 * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
39- phys (required)
40- phy-names (required)
41- hpd-gpios (optional)
42- force-hpd (optional)
43-------------------------------------------------------------------------------
44
45Example:
46	dp-controller: dp@ff970000 {
47		compatible = "rockchip,rk3288-dp";
48		reg = <0xff970000 0x4000>;
49		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
50		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
51		clock-names = "dp", "pclk";
52		phys = <&dp_phy>;
53		phy-names = "dp";
54
55		rockchip,grf = <&grf>;
56		resets = <&cru 111>;
57		reset-names = "dp";
58
59		pinctrl-names = "default";
60		pinctrl-0 = <&edp_hpd>;
61
62
63		ports {
64			#address-cells = <1>;
65			#size-cells = <0>;
66			edp_in: port@0 {
67				reg = <0>;
68				#address-cells = <1>;
69				#size-cells = <0>;
70				edp_in_vopb: endpoint@0 {
71					reg = <0>;
72					remote-endpoint = <&vopb_out_edp>;
73				};
74				edp_in_vopl: endpoint@1 {
75					reg = <1>;
76					remote-endpoint = <&vopl_out_edp>;
77				};
78			};
79
80			edp_out: port@1 {
81				reg = <1>;
82				#address-cells = <1>;
83				#size-cells = <0>;
84				edp_out_panel: endpoint {
85					reg = <0>;
86					remote-endpoint = <&panel_in_edp>
87				};
88			};
89		};
90	};
91
92	pinctrl {
93		edp {
94			edp_hpd: edp-hpd {
95				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
96			};
97		};
98	};
99