1* Mediatek MT65XX Pin Controller 2 3The Mediatek's Pin controller is used to control SoC pins. 4 5Required properties: 6- compatible: value should be one of the following. 7 "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. 8 "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. 9 "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. 10 "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. 11 "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. 12 "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. 13 "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. 14 "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. 15 "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. 16- pins-are-numbered: Specify the subnodes are using numbered pinmux to 17 specify pins. 18- gpio-controller : Marks the device node as a gpio controller. 19- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 20 binding is used, the amount of cells must be specified as 2. See the below 21 mentioned gpio binding representation for description of particular cells. 22 23 Eg: <&pio 6 0> 24 <[phandle of the gpio controller node] 25 [line number within the gpio controller] 26 [flags]> 27 28 Values for gpio specifier: 29 - Line number: is a value between 0 to 202. 30 - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>. 31 Only the following flags are supported: 32 0 - GPIO_ACTIVE_HIGH 33 1 - GPIO_ACTIVE_LOW 34 35Optional properties: 36- mediatek,pctl-regmap: Should be a phandle of the syscfg node. 37- reg: physicall address base for EINT registers 38- interrupt-controller: Marks the device node as an interrupt controller 39- #interrupt-cells: Should be two. 40- interrupts : The interrupt outputs from the controller. 41 42Please refer to pinctrl-bindings.txt in this directory for details of the 43common pinctrl bindings used by client devices. 44 45Subnode format 46A pinctrl node should contain at least one subnodes representing the 47pinctrl groups available on the machine. Each subnode will list the 48pins it needs, and how they should be configured, with regard to muxer 49configuration, pullups, drive strength, input enable/disable and input schmitt. 50 51 node { 52 pinmux = <PIN_NUMBER_PINMUX>; 53 GENERIC_PINCONFIG; 54 }; 55 56Required properties: 57- pinmux: integer array, represents gpio pin number and mux setting. 58 Supported pin number and mux varies for different SoCs, and are defined 59 as macros in boot/dts/<soc>-pinfunc.h directly. 60 61Optional properties: 62- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, 63 bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, 64 input-schmitt-enable, input-schmitt-disable and drive-strength are valid. 65 66 Some special pins have extra pull up strength, there are R0 and R1 pull-up 67 resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. 68 So when config bias-pull-up, it support arguments for those special pins. 69 Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00. 70 See dt-bindings/pinctrl/mt65xx.h. 71 72 When config drive-strength, it can support some arguments, such as 73 MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. 74 75Examples: 76 77#include "mt8135-pinfunc.h" 78 79... 80{ 81 syscfg_pctl_a: syscfg-pctl-a@10005000 { 82 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; 83 reg = <0 0x10005000 0 0x1000>; 84 }; 85 86 syscfg_pctl_b: syscfg-pctl-b@1020c020 { 87 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; 88 reg = <0 0x1020C020 0 0x1000>; 89 }; 90 91 pinctrl@1c20800 { 92 compatible = "mediatek,mt8135-pinctrl"; 93 reg = <0 0x1000B000 0 0x1000>; 94 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; 95 pins-are-numbered; 96 gpio-controller; 97 #gpio-cells = <2>; 98 interrupt-controller; 99 #interrupt-cells = <2>; 100 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 103 104 i2c0_pins_a: i2c0@0 { 105 pins1 { 106 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, 107 <MT8135_PIN_101_SCL0__FUNC_SCL0>; 108 bias-disable; 109 }; 110 }; 111 112 i2c1_pins_a: i2c1@0 { 113 pins { 114 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, 115 <MT8135_PIN_196_SCL1__FUNC_SCL1>; 116 bias-pull-up = <55>; 117 }; 118 }; 119 120 i2c2_pins_a: i2c2@0 { 121 pins1 { 122 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; 123 bias-pull-down; 124 }; 125 126 pins2 { 127 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; 128 bias-pull-up; 129 }; 130 }; 131 132 i2c3_pins_a: i2c3@0 { 133 pins1 { 134 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>, 135 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>; 136 bias-pull-up = <55>; 137 }; 138 139 pins2 { 140 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>, 141 <MT8135_PIN_36_SDA3__FUNC_SDA3>; 142 output-low; 143 bias-pull-up = <55>; 144 }; 145 146 pins3 { 147 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>, 148 <MT8135_PIN_60_JTDI__FUNC_JTDI>; 149 drive-strength = <32>; 150 }; 151 }; 152 153 ... 154 } 155}; 156