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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2014 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6sx-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6sx-pinfunc.h"
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	/*
15	 * The decompressor and also some bootloaders rely on a
16	 * pre-existing /chosen node to be available to insert the
17	 * command line and merge other ATAGS info.
18	 */
19	chosen {};
20
21	aliases {
22		can0 = &flexcan1;
23		can1 = &flexcan2;
24		ethernet0 = &fec1;
25		ethernet1 = &fec2;
26		gpio0 = &gpio1;
27		gpio1 = &gpio2;
28		gpio2 = &gpio3;
29		gpio3 = &gpio4;
30		gpio4 = &gpio5;
31		gpio5 = &gpio6;
32		gpio6 = &gpio7;
33		i2c0 = &i2c1;
34		i2c1 = &i2c2;
35		i2c2 = &i2c3;
36		i2c3 = &i2c4;
37		mmc0 = &usdhc1;
38		mmc1 = &usdhc2;
39		mmc2 = &usdhc3;
40		mmc3 = &usdhc4;
41		serial0 = &uart1;
42		serial1 = &uart2;
43		serial2 = &uart3;
44		serial3 = &uart4;
45		serial4 = &uart5;
46		serial5 = &uart6;
47		spi0 = &ecspi1;
48		spi1 = &ecspi2;
49		spi2 = &ecspi3;
50		spi3 = &ecspi4;
51		spi4 = &ecspi5;
52		usbphy0 = &usbphy1;
53		usbphy1 = &usbphy2;
54	};
55
56	cpus {
57		#address-cells = <1>;
58		#size-cells = <0>;
59
60		cpu0: cpu@0 {
61			compatible = "arm,cortex-a9";
62			device_type = "cpu";
63			reg = <0>;
64			next-level-cache = <&L2>;
65			operating-points = <
66				/* kHz    uV */
67				996000  1250000
68				792000  1175000
69				396000  1075000
70				198000	975000
71			>;
72			fsl,soc-operating-points = <
73				/* ARM kHz  SOC uV */
74				996000      1175000
75				792000      1175000
76				396000      1175000
77				198000	    1175000
78			>;
79			clock-latency = <61036>; /* two CLK32 periods */
80			#cooling-cells = <2>;
81			clocks = <&clks IMX6SX_CLK_ARM>,
82				 <&clks IMX6SX_CLK_PLL2_PFD2>,
83				 <&clks IMX6SX_CLK_STEP>,
84				 <&clks IMX6SX_CLK_PLL1_SW>,
85				 <&clks IMX6SX_CLK_PLL1_SYS>;
86			clock-names = "arm", "pll2_pfd2_396m", "step",
87				      "pll1_sw", "pll1_sys";
88			arm-supply = <&reg_arm>;
89			soc-supply = <&reg_soc>;
90			nvmem-cells = <&cpu_speed_grade>;
91			nvmem-cell-names = "speed_grade";
92		};
93	};
94
95	ckil: clock-ckil {
96		compatible = "fixed-clock";
97		#clock-cells = <0>;
98		clock-frequency = <32768>;
99		clock-output-names = "ckil";
100	};
101
102	osc: clock-osc {
103		compatible = "fixed-clock";
104		#clock-cells = <0>;
105		clock-frequency = <24000000>;
106		clock-output-names = "osc";
107	};
108
109	ipp_di0: clock-ipp-di0 {
110		compatible = "fixed-clock";
111		#clock-cells = <0>;
112		clock-frequency = <0>;
113		clock-output-names = "ipp_di0";
114	};
115
116	ipp_di1: clock-ipp-di1 {
117		compatible = "fixed-clock";
118		#clock-cells = <0>;
119		clock-frequency = <0>;
120		clock-output-names = "ipp_di1";
121	};
122
123	anaclk1: clock-anaclk1 {
124		compatible = "fixed-clock";
125		#clock-cells = <0>;
126		clock-frequency = <0>;
127		clock-output-names = "anaclk1";
128	};
129
130	anaclk2: clock-anaclk2 {
131		compatible = "fixed-clock";
132		#clock-cells = <0>;
133		clock-frequency = <0>;
134		clock-output-names = "anaclk2";
135	};
136
137	mqs: mqs {
138		compatible = "fsl,imx6sx-mqs";
139		gpr = <&gpr>;
140		status = "disabled";
141	};
142
143	pmu {
144		compatible = "arm,cortex-a9-pmu";
145		interrupt-parent = <&gpc>;
146		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
147	};
148
149	usbphynop1: usbphynop1 {
150		compatible = "usb-nop-xceiv";
151		#phy-cells = <0>;
152	};
153
154	soc {
155		#address-cells = <1>;
156		#size-cells = <1>;
157		compatible = "simple-bus";
158		interrupt-parent = <&gpc>;
159		ranges;
160
161		ocram_s: sram@8f8000 {
162			compatible = "mmio-sram";
163			reg = <0x008f8000 0x4000>;
164			ranges = <0 0x008f8000 0x4000>;
165			#address-cells = <1>;
166			#size-cells = <1>;
167			clocks = <&clks IMX6SX_CLK_OCRAM_S>;
168		};
169
170		ocram: sram@900000 {
171			compatible = "mmio-sram";
172			reg = <0x00900000 0x20000>;
173			ranges = <0 0x00900000 0x20000>;
174			#address-cells = <1>;
175			#size-cells = <1>;
176			clocks = <&clks IMX6SX_CLK_OCRAM>;
177		};
178
179		intc: interrupt-controller@a01000 {
180			compatible = "arm,cortex-a9-gic";
181			#interrupt-cells = <3>;
182			interrupt-controller;
183			reg = <0x00a01000 0x1000>,
184			      <0x00a00100 0x100>;
185			interrupt-parent = <&intc>;
186		};
187
188		L2: cache-controller@a02000 {
189			compatible = "arm,pl310-cache";
190			reg = <0x00a02000 0x1000>;
191			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
192			cache-unified;
193			cache-level = <2>;
194			arm,tag-latency = <4 2 3>;
195			arm,data-latency = <4 2 3>;
196		};
197
198		gpu: gpu@1800000 {
199			compatible = "vivante,gc";
200			reg = <0x01800000 0x4000>;
201			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
202			clocks = <&clks IMX6SX_CLK_GPU>,
203				 <&clks IMX6SX_CLK_GPU>,
204				 <&clks IMX6SX_CLK_GPU>;
205			clock-names = "bus", "core", "shader";
206			power-domains = <&pd_pu>;
207		};
208
209		dma_apbh: dma-apbh@1804000 {
210			compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
211			reg = <0x01804000 0x2000>;
212			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
213				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
214				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
215				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
216			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
217			#dma-cells = <1>;
218			dma-channels = <4>;
219			clocks = <&clks IMX6SX_CLK_APBH_DMA>;
220		};
221
222		gpmi: nand-controller@1806000{
223			compatible = "fsl,imx6sx-gpmi-nand";
224			#address-cells = <1>;
225			#size-cells = <1>;
226			reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
227			reg-names = "gpmi-nand", "bch";
228			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
229			interrupt-names = "bch";
230			clocks = <&clks IMX6SX_CLK_GPMI_IO>,
231				 <&clks IMX6SX_CLK_GPMI_APB>,
232				 <&clks IMX6SX_CLK_GPMI_BCH>,
233				 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
234				 <&clks IMX6SX_CLK_PER1_BCH>;
235			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
236				      "gpmi_bch_apb", "per1_bch";
237			dmas = <&dma_apbh 0>;
238			dma-names = "rx-tx";
239			status = "disabled";
240		};
241
242		aips1: bus@2000000 {
243			compatible = "fsl,aips-bus", "simple-bus";
244			#address-cells = <1>;
245			#size-cells = <1>;
246			reg = <0x02000000 0x100000>;
247			ranges;
248
249			spba-bus@2000000 {
250				compatible = "fsl,spba-bus", "simple-bus";
251				#address-cells = <1>;
252				#size-cells = <1>;
253				reg = <0x02000000 0x40000>;
254				ranges;
255
256				spdif: spdif@2004000 {
257					compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
258					reg = <0x02004000 0x4000>;
259					interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
260					dmas = <&sdma 14 18 0>,
261					       <&sdma 15 18 0>;
262					dma-names = "rx", "tx";
263					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
264						 <&clks IMX6SX_CLK_OSC>,
265						 <&clks IMX6SX_CLK_SPDIF>,
266						 <&clks 0>, <&clks 0>, <&clks 0>,
267						 <&clks IMX6SX_CLK_IPG>,
268						 <&clks 0>, <&clks 0>,
269						 <&clks IMX6SX_CLK_SPBA>;
270					clock-names = "core", "rxtx0",
271						      "rxtx1", "rxtx2",
272						      "rxtx3", "rxtx4",
273						      "rxtx5", "rxtx6",
274						      "rxtx7", "spba";
275					status = "disabled";
276				};
277
278				ecspi1: spi@2008000 {
279					#address-cells = <1>;
280					#size-cells = <0>;
281					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
282					reg = <0x02008000 0x4000>;
283					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
284					clocks = <&clks IMX6SX_CLK_ECSPI1>,
285						 <&clks IMX6SX_CLK_ECSPI1>;
286					clock-names = "ipg", "per";
287					status = "disabled";
288				};
289
290				ecspi2: spi@200c000 {
291					#address-cells = <1>;
292					#size-cells = <0>;
293					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
294					reg = <0x0200c000 0x4000>;
295					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
296					clocks = <&clks IMX6SX_CLK_ECSPI2>,
297						 <&clks IMX6SX_CLK_ECSPI2>;
298					clock-names = "ipg", "per";
299					status = "disabled";
300				};
301
302				ecspi3: spi@2010000 {
303					#address-cells = <1>;
304					#size-cells = <0>;
305					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
306					reg = <0x02010000 0x4000>;
307					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
308					clocks = <&clks IMX6SX_CLK_ECSPI3>,
309						 <&clks IMX6SX_CLK_ECSPI3>;
310					clock-names = "ipg", "per";
311					status = "disabled";
312				};
313
314				ecspi4: spi@2014000 {
315					#address-cells = <1>;
316					#size-cells = <0>;
317					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
318					reg = <0x02014000 0x4000>;
319					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
320					clocks = <&clks IMX6SX_CLK_ECSPI4>,
321						 <&clks IMX6SX_CLK_ECSPI4>;
322					clock-names = "ipg", "per";
323					status = "disabled";
324				};
325
326				uart1: serial@2020000 {
327					compatible = "fsl,imx6sx-uart",
328						     "fsl,imx6q-uart", "fsl,imx21-uart";
329					reg = <0x02020000 0x4000>;
330					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
331					clocks = <&clks IMX6SX_CLK_UART_IPG>,
332						 <&clks IMX6SX_CLK_UART_SERIAL>;
333					clock-names = "ipg", "per";
334					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
335					dma-names = "rx", "tx";
336					status = "disabled";
337				};
338
339				esai: esai@2024000 {
340					compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
341					reg = <0x02024000 0x4000>;
342					interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
343					clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
344						 <&clks IMX6SX_CLK_ESAI_MEM>,
345						 <&clks IMX6SX_CLK_ESAI_EXTAL>,
346						 <&clks IMX6SX_CLK_ESAI_IPG>,
347						 <&clks IMX6SX_CLK_SPBA>;
348					clock-names = "core", "mem", "extal",
349						      "fsys", "spba";
350					dmas = <&sdma 23 21 0>,
351					       <&sdma 24 21 0>;
352					dma-names = "rx", "tx";
353					status = "disabled";
354				};
355
356				ssi1: ssi@2028000 {
357					#sound-dai-cells = <0>;
358					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
359					reg = <0x02028000 0x4000>;
360					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
361					clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
362						 <&clks IMX6SX_CLK_SSI1>;
363					clock-names = "ipg", "baud";
364					dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
365					dma-names = "rx", "tx";
366					fsl,fifo-depth = <15>;
367					status = "disabled";
368				};
369
370				ssi2: ssi@202c000 {
371					#sound-dai-cells = <0>;
372					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
373					reg = <0x0202c000 0x4000>;
374					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
375					clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
376						 <&clks IMX6SX_CLK_SSI2>;
377					clock-names = "ipg", "baud";
378					dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
379					dma-names = "rx", "tx";
380					fsl,fifo-depth = <15>;
381					status = "disabled";
382				};
383
384				ssi3: ssi@2030000 {
385					#sound-dai-cells = <0>;
386					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
387					reg = <0x02030000 0x4000>;
388					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
389					clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
390						 <&clks IMX6SX_CLK_SSI3>;
391					clock-names = "ipg", "baud";
392					dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
393					dma-names = "rx", "tx";
394					fsl,fifo-depth = <15>;
395					status = "disabled";
396				};
397
398				asrc: asrc@2034000 {
399					compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
400					reg = <0x02034000 0x4000>;
401					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
402					clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
403						<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
404						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
405						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
406						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
407						<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
408						<&clks IMX6SX_CLK_SPBA>;
409					clock-names = "mem", "ipg", "asrck_0",
410						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
411						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
412						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
413						"asrck_d", "asrck_e", "asrck_f", "spba";
414					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
415					       <&sdma 19 23 1>, <&sdma 20 23 1>,
416					       <&sdma 21 23 1>, <&sdma 22 23 1>;
417					dma-names = "rxa", "rxb", "rxc",
418						    "txa", "txb", "txc";
419					fsl,asrc-rate  = <48000>;
420					fsl,asrc-width = <16>;
421					status = "okay";
422				};
423			};
424
425			pwm1: pwm@2080000 {
426				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
427				reg = <0x02080000 0x4000>;
428				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
429				clocks = <&clks IMX6SX_CLK_PWM1>,
430					 <&clks IMX6SX_CLK_PWM1>;
431				clock-names = "ipg", "per";
432				#pwm-cells = <3>;
433			};
434
435			pwm2: pwm@2084000 {
436				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
437				reg = <0x02084000 0x4000>;
438				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
439				clocks = <&clks IMX6SX_CLK_PWM2>,
440					 <&clks IMX6SX_CLK_PWM2>;
441				clock-names = "ipg", "per";
442				#pwm-cells = <3>;
443			};
444
445			pwm3: pwm@2088000 {
446				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
447				reg = <0x02088000 0x4000>;
448				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
449				clocks = <&clks IMX6SX_CLK_PWM3>,
450					 <&clks IMX6SX_CLK_PWM3>;
451				clock-names = "ipg", "per";
452				#pwm-cells = <3>;
453			};
454
455			pwm4: pwm@208c000 {
456				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
457				reg = <0x0208c000 0x4000>;
458				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
459				clocks = <&clks IMX6SX_CLK_PWM4>,
460					 <&clks IMX6SX_CLK_PWM4>;
461				clock-names = "ipg", "per";
462				#pwm-cells = <3>;
463			};
464
465			flexcan1: can@2090000 {
466				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
467				reg = <0x02090000 0x4000>;
468				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
469				clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
470					 <&clks IMX6SX_CLK_CAN1_SERIAL>;
471				clock-names = "ipg", "per";
472				fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
473				status = "disabled";
474			};
475
476			flexcan2: can@2094000 {
477				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
478				reg = <0x02094000 0x4000>;
479				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
480				clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
481					 <&clks IMX6SX_CLK_CAN2_SERIAL>;
482				clock-names = "ipg", "per";
483				fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
484				status = "disabled";
485			};
486
487			gpt: timer@2098000 {
488				compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
489				reg = <0x02098000 0x4000>;
490				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
491				clocks = <&clks IMX6SX_CLK_GPT_BUS>,
492					 <&clks IMX6SX_CLK_GPT_3M>;
493				clock-names = "ipg", "per";
494			};
495
496			gpio1: gpio@209c000 {
497				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
498				reg = <0x0209c000 0x4000>;
499				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
500					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
501				gpio-controller;
502				#gpio-cells = <2>;
503				interrupt-controller;
504				#interrupt-cells = <2>;
505				gpio-ranges = <&iomuxc 0 5 26>;
506			};
507
508			gpio2: gpio@20a0000 {
509				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
510				reg = <0x020a0000 0x4000>;
511				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
512					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
513				gpio-controller;
514				#gpio-cells = <2>;
515				interrupt-controller;
516				#interrupt-cells = <2>;
517				gpio-ranges = <&iomuxc 0 31 20>;
518			};
519
520			gpio3: gpio@20a4000 {
521				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
522				reg = <0x020a4000 0x4000>;
523				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
524					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
525				gpio-controller;
526				#gpio-cells = <2>;
527				interrupt-controller;
528				#interrupt-cells = <2>;
529				gpio-ranges = <&iomuxc 0 51 29>;
530			};
531
532			gpio4: gpio@20a8000 {
533				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
534				reg = <0x020a8000 0x4000>;
535				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
536					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
537				gpio-controller;
538				#gpio-cells = <2>;
539				interrupt-controller;
540				#interrupt-cells = <2>;
541				gpio-ranges = <&iomuxc 0 80 32>;
542			};
543
544			gpio5: gpio@20ac000 {
545				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
546				reg = <0x020ac000 0x4000>;
547				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
548					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
549				gpio-controller;
550				#gpio-cells = <2>;
551				interrupt-controller;
552				#interrupt-cells = <2>;
553				gpio-ranges = <&iomuxc 0 112 24>;
554			};
555
556			gpio6: gpio@20b0000 {
557				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
558				reg = <0x020b0000 0x4000>;
559				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
560					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
561				gpio-controller;
562				#gpio-cells = <2>;
563				interrupt-controller;
564				#interrupt-cells = <2>;
565				gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
566			};
567
568			gpio7: gpio@20b4000 {
569				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
570				reg = <0x020b4000 0x4000>;
571				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
572					     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
573				gpio-controller;
574				#gpio-cells = <2>;
575				interrupt-controller;
576				#interrupt-cells = <2>;
577				gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
578			};
579
580			kpp: keypad@20b8000 {
581				compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
582				reg = <0x020b8000 0x4000>;
583				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
584				clocks = <&clks IMX6SX_CLK_IPG>;
585				status = "disabled";
586			};
587
588			wdog1: watchdog@20bc000 {
589				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
590				reg = <0x020bc000 0x4000>;
591				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
592				clocks = <&clks IMX6SX_CLK_IPG>;
593			};
594
595			wdog2: watchdog@20c0000 {
596				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
597				reg = <0x020c0000 0x4000>;
598				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
599				clocks = <&clks IMX6SX_CLK_IPG>;
600				status = "disabled";
601			};
602
603			clks: clock-controller@20c4000 {
604				compatible = "fsl,imx6sx-ccm";
605				reg = <0x020c4000 0x4000>;
606				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
607					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
608				#clock-cells = <1>;
609				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
610				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
611			};
612
613			anatop: anatop@20c8000 {
614				compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
615					     "syscon", "simple-mfd";
616				reg = <0x020c8000 0x1000>;
617				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
618					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
619					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
620
621				reg_vdd1p1: regulator-1p1 {
622					compatible = "fsl,anatop-regulator";
623					regulator-name = "vdd1p1";
624					regulator-min-microvolt = <1000000>;
625					regulator-max-microvolt = <1200000>;
626					regulator-always-on;
627					anatop-reg-offset = <0x110>;
628					anatop-vol-bit-shift = <8>;
629					anatop-vol-bit-width = <5>;
630					anatop-min-bit-val = <4>;
631					anatop-min-voltage = <800000>;
632					anatop-max-voltage = <1375000>;
633					anatop-enable-bit = <0>;
634				};
635
636				reg_vdd3p0: regulator-3p0 {
637					compatible = "fsl,anatop-regulator";
638					regulator-name = "vdd3p0";
639					regulator-min-microvolt = <2800000>;
640					regulator-max-microvolt = <3150000>;
641					regulator-always-on;
642					anatop-reg-offset = <0x120>;
643					anatop-vol-bit-shift = <8>;
644					anatop-vol-bit-width = <5>;
645					anatop-min-bit-val = <0>;
646					anatop-min-voltage = <2625000>;
647					anatop-max-voltage = <3400000>;
648					anatop-enable-bit = <0>;
649				};
650
651				reg_vdd2p5: regulator-2p5 {
652					compatible = "fsl,anatop-regulator";
653					regulator-name = "vdd2p5";
654					regulator-min-microvolt = <2250000>;
655					regulator-max-microvolt = <2750000>;
656					regulator-always-on;
657					anatop-reg-offset = <0x130>;
658					anatop-vol-bit-shift = <8>;
659					anatop-vol-bit-width = <5>;
660					anatop-min-bit-val = <0>;
661					anatop-min-voltage = <2100000>;
662					anatop-max-voltage = <2875000>;
663					anatop-enable-bit = <0>;
664				};
665
666				reg_arm: regulator-vddcore {
667					compatible = "fsl,anatop-regulator";
668					regulator-name = "vddarm";
669					regulator-min-microvolt = <725000>;
670					regulator-max-microvolt = <1450000>;
671					regulator-always-on;
672					anatop-reg-offset = <0x140>;
673					anatop-vol-bit-shift = <0>;
674					anatop-vol-bit-width = <5>;
675					anatop-delay-reg-offset = <0x170>;
676					anatop-delay-bit-shift = <24>;
677					anatop-delay-bit-width = <2>;
678					anatop-min-bit-val = <1>;
679					anatop-min-voltage = <725000>;
680					anatop-max-voltage = <1450000>;
681				};
682
683				reg_pcie: regulator-vddpcie {
684					compatible = "fsl,anatop-regulator";
685					regulator-name = "vddpcie";
686					regulator-min-microvolt = <725000>;
687					regulator-max-microvolt = <1450000>;
688					anatop-reg-offset = <0x140>;
689					anatop-vol-bit-shift = <9>;
690					anatop-vol-bit-width = <5>;
691					anatop-delay-reg-offset = <0x170>;
692					anatop-delay-bit-shift = <26>;
693					anatop-delay-bit-width = <2>;
694					anatop-min-bit-val = <1>;
695					anatop-min-voltage = <725000>;
696					anatop-max-voltage = <1450000>;
697				};
698
699				reg_soc: regulator-vddsoc {
700					compatible = "fsl,anatop-regulator";
701					regulator-name = "vddsoc";
702					regulator-min-microvolt = <725000>;
703					regulator-max-microvolt = <1450000>;
704					regulator-always-on;
705					anatop-reg-offset = <0x140>;
706					anatop-vol-bit-shift = <18>;
707					anatop-vol-bit-width = <5>;
708					anatop-delay-reg-offset = <0x170>;
709					anatop-delay-bit-shift = <28>;
710					anatop-delay-bit-width = <2>;
711					anatop-min-bit-val = <1>;
712					anatop-min-voltage = <725000>;
713					anatop-max-voltage = <1450000>;
714				};
715
716				tempmon: tempmon {
717					compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
718					interrupt-parent = <&gpc>;
719					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
720					fsl,tempmon = <&anatop>;
721					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
722					nvmem-cell-names = "calib", "temp_grade";
723					clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
724				};
725			};
726
727			usbphy1: usbphy@20c9000 {
728				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
729				reg = <0x020c9000 0x1000>;
730				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
731				clocks = <&clks IMX6SX_CLK_USBPHY1>;
732				fsl,anatop = <&anatop>;
733			};
734
735			usbphy2: usbphy@20ca000 {
736				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
737				reg = <0x020ca000 0x1000>;
738				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
739				clocks = <&clks IMX6SX_CLK_USBPHY2>;
740				fsl,anatop = <&anatop>;
741			};
742
743			snvs: snvs@20cc000 {
744				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
745				reg = <0x020cc000 0x4000>;
746
747				snvs_rtc: snvs-rtc-lp {
748					compatible = "fsl,sec-v4.0-mon-rtc-lp";
749					regmap = <&snvs>;
750					offset = <0x34>;
751					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
752				};
753
754				snvs_poweroff: snvs-poweroff {
755					compatible = "syscon-poweroff";
756					regmap = <&snvs>;
757					offset = <0x38>;
758					value = <0x60>;
759					mask = <0x60>;
760					status = "disabled";
761				};
762
763				snvs_pwrkey: snvs-powerkey {
764					compatible = "fsl,sec-v4.0-pwrkey";
765					regmap = <&snvs>;
766					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
767					linux,keycode = <KEY_POWER>;
768					wakeup-source;
769					status = "disabled";
770				};
771			};
772
773			epit1: epit@20d0000 {
774				reg = <0x020d0000 0x4000>;
775				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
776			};
777
778			epit2: epit@20d4000 {
779				reg = <0x020d4000 0x4000>;
780				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
781			};
782
783			src: reset-controller@20d8000 {
784				compatible = "fsl,imx6sx-src", "fsl,imx51-src";
785				reg = <0x020d8000 0x4000>;
786				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
787					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
788				#reset-cells = <1>;
789			};
790
791			gpc: gpc@20dc000 {
792				compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
793				reg = <0x020dc000 0x4000>;
794				interrupt-controller;
795				#interrupt-cells = <3>;
796				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
797				interrupt-parent = <&intc>;
798				clocks = <&clks IMX6SX_CLK_IPG>;
799				clock-names = "ipg";
800
801				pgc {
802					#address-cells = <1>;
803					#size-cells = <0>;
804
805					power-domain@0 {
806						reg = <0>;
807						#power-domain-cells = <0>;
808					};
809
810					pd_pu: power-domain@1 {
811						reg = <1>;
812						#power-domain-cells = <0>;
813						power-supply = <&reg_soc>;
814						clocks = <&clks IMX6SX_CLK_GPU>;
815					};
816
817					pd_disp: power-domain@2 {
818						reg = <2>;
819						#power-domain-cells = <0>;
820						clocks = <&clks IMX6SX_CLK_PXP_AXI>,
821							 <&clks IMX6SX_CLK_DISPLAY_AXI>,
822							 <&clks IMX6SX_CLK_LCDIF1_PIX>,
823							 <&clks IMX6SX_CLK_LCDIF_APB>,
824							 <&clks IMX6SX_CLK_LCDIF2_PIX>,
825							 <&clks IMX6SX_CLK_CSI>,
826							 <&clks IMX6SX_CLK_VADC>;
827					};
828
829					pd_pci: power-domain@3 {
830						reg = <3>;
831						#power-domain-cells = <0>;
832						power-supply = <&reg_pcie>;
833					};
834				};
835			};
836
837			iomuxc: pinctrl@20e0000 {
838				compatible = "fsl,imx6sx-iomuxc";
839				reg = <0x020e0000 0x4000>;
840			};
841
842			gpr: iomuxc-gpr@20e4000 {
843				compatible = "fsl,imx6sx-iomuxc-gpr",
844					     "fsl,imx6q-iomuxc-gpr", "syscon";
845				reg = <0x020e4000 0x4000>;
846			};
847
848			sdma: sdma@20ec000 {
849				compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
850				reg = <0x020ec000 0x4000>;
851				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
852				clocks = <&clks IMX6SX_CLK_IPG>,
853					 <&clks IMX6SX_CLK_SDMA>;
854				clock-names = "ipg", "ahb";
855				#dma-cells = <3>;
856				/* imx6sx reuses imx6q sdma firmware */
857				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
858			};
859		};
860
861		aips2: bus@2100000 {
862			compatible = "fsl,aips-bus", "simple-bus";
863			#address-cells = <1>;
864			#size-cells = <1>;
865			reg = <0x02100000 0x100000>;
866			ranges;
867
868			crypto: crypto@2100000 {
869				compatible = "fsl,sec-v4.0";
870				#address-cells = <1>;
871				#size-cells = <1>;
872				reg = <0x2100000 0x10000>;
873				ranges = <0 0x2100000 0x10000>;
874				interrupt-parent = <&intc>;
875				clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
876					 <&clks IMX6SX_CLK_CAAM_ACLK>,
877					 <&clks IMX6SX_CLK_CAAM_IPG>,
878					 <&clks IMX6SX_CLK_EIM_SLOW>;
879				clock-names = "mem", "aclk", "ipg", "emi_slow";
880
881				sec_jr0: jr@1000 {
882					compatible = "fsl,sec-v4.0-job-ring";
883					reg = <0x1000 0x1000>;
884					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
885				};
886
887				sec_jr1: jr@2000 {
888					compatible = "fsl,sec-v4.0-job-ring";
889					reg = <0x2000 0x1000>;
890					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
891				};
892			};
893
894			usbotg1: usb@2184000 {
895				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
896				reg = <0x02184000 0x200>;
897				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
898				clocks = <&clks IMX6SX_CLK_USBOH3>;
899				fsl,usbphy = <&usbphy1>;
900				fsl,usbmisc = <&usbmisc 0>;
901				fsl,anatop = <&anatop>;
902				ahb-burst-config = <0x0>;
903				tx-burst-size-dword = <0x10>;
904				rx-burst-size-dword = <0x10>;
905				status = "disabled";
906			};
907
908			usbotg2: usb@2184200 {
909				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
910				reg = <0x02184200 0x200>;
911				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
912				clocks = <&clks IMX6SX_CLK_USBOH3>;
913				fsl,usbphy = <&usbphy2>;
914				fsl,usbmisc = <&usbmisc 1>;
915				ahb-burst-config = <0x0>;
916				tx-burst-size-dword = <0x10>;
917				rx-burst-size-dword = <0x10>;
918				status = "disabled";
919			};
920
921			usbh: usb@2184400 {
922				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
923				reg = <0x02184400 0x200>;
924				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
925				clocks = <&clks IMX6SX_CLK_USBOH3>;
926				fsl,usbphy = <&usbphynop1>;
927				fsl,usbmisc = <&usbmisc 2>;
928				phy_type = "hsic";
929				fsl,anatop = <&anatop>;
930				dr_mode = "host";
931				ahb-burst-config = <0x0>;
932				tx-burst-size-dword = <0x10>;
933				rx-burst-size-dword = <0x10>;
934				status = "disabled";
935			};
936
937			usbmisc: usbmisc@2184800 {
938				#index-cells = <1>;
939				compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
940				reg = <0x02184800 0x200>;
941				clocks = <&clks IMX6SX_CLK_USBOH3>;
942			};
943
944			fec1: ethernet@2188000 {
945				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
946				reg = <0x02188000 0x4000>;
947				interrupt-names = "int0", "pps";
948				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
949					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
950				clocks = <&clks IMX6SX_CLK_ENET>,
951					 <&clks IMX6SX_CLK_ENET_AHB>,
952					 <&clks IMX6SX_CLK_ENET_PTP>,
953					 <&clks IMX6SX_CLK_ENET_REF>,
954					 <&clks IMX6SX_CLK_ENET_PTP>;
955				clock-names = "ipg", "ahb", "ptp",
956					      "enet_clk_ref", "enet_out";
957				fsl,num-tx-queues = <3>;
958				fsl,num-rx-queues = <3>;
959				fsl,stop-mode = <&gpr 0x10 3>;
960				status = "disabled";
961			};
962
963			mlb: mlb@218c000 {
964				reg = <0x0218c000 0x4000>;
965				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
966					     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
967					     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
968				clocks = <&clks IMX6SX_CLK_MLB>;
969				status = "disabled";
970			};
971
972			usdhc1: mmc@2190000 {
973				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
974				reg = <0x02190000 0x4000>;
975				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
976				clocks = <&clks IMX6SX_CLK_USDHC1>,
977					 <&clks IMX6SX_CLK_USDHC1>,
978					 <&clks IMX6SX_CLK_USDHC1>;
979				clock-names = "ipg", "ahb", "per";
980				bus-width = <4>;
981				status = "disabled";
982			};
983
984			usdhc2: mmc@2194000 {
985				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
986				reg = <0x02194000 0x4000>;
987				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
988				clocks = <&clks IMX6SX_CLK_USDHC2>,
989					 <&clks IMX6SX_CLK_USDHC2>,
990					 <&clks IMX6SX_CLK_USDHC2>;
991				clock-names = "ipg", "ahb", "per";
992				bus-width = <4>;
993				status = "disabled";
994			};
995
996			usdhc3: mmc@2198000 {
997				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
998				reg = <0x02198000 0x4000>;
999				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1000				clocks = <&clks IMX6SX_CLK_USDHC3>,
1001					 <&clks IMX6SX_CLK_USDHC3>,
1002					 <&clks IMX6SX_CLK_USDHC3>;
1003				clock-names = "ipg", "ahb", "per";
1004				bus-width = <4>;
1005				status = "disabled";
1006			};
1007
1008			usdhc4: mmc@219c000 {
1009				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1010				reg = <0x0219c000 0x4000>;
1011				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1012				clocks = <&clks IMX6SX_CLK_USDHC4>,
1013					 <&clks IMX6SX_CLK_USDHC4>,
1014					 <&clks IMX6SX_CLK_USDHC4>;
1015				clock-names = "ipg", "ahb", "per";
1016				bus-width = <4>;
1017				status = "disabled";
1018			};
1019
1020			i2c1: i2c@21a0000 {
1021				#address-cells = <1>;
1022				#size-cells = <0>;
1023				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1024				reg = <0x021a0000 0x4000>;
1025				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1026				clocks = <&clks IMX6SX_CLK_I2C1>;
1027				status = "disabled";
1028			};
1029
1030			i2c2: i2c@21a4000 {
1031				#address-cells = <1>;
1032				#size-cells = <0>;
1033				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1034				reg = <0x021a4000 0x4000>;
1035				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1036				clocks = <&clks IMX6SX_CLK_I2C2>;
1037				status = "disabled";
1038			};
1039
1040			i2c3: i2c@21a8000 {
1041				#address-cells = <1>;
1042				#size-cells = <0>;
1043				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1044				reg = <0x021a8000 0x4000>;
1045				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1046				clocks = <&clks IMX6SX_CLK_I2C3>;
1047				status = "disabled";
1048			};
1049
1050			memory-controller@21b0000 {
1051				compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1052				reg = <0x021b0000 0x4000>;
1053				clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1054			};
1055
1056			fec2: ethernet@21b4000 {
1057				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1058				reg = <0x021b4000 0x4000>;
1059				interrupt-names = "int0", "pps";
1060				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1061					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1062				clocks = <&clks IMX6SX_CLK_ENET>,
1063					 <&clks IMX6SX_CLK_ENET_AHB>,
1064					 <&clks IMX6SX_CLK_ENET_PTP>,
1065					 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1066					 <&clks IMX6SX_CLK_ENET_PTP>;
1067				clock-names = "ipg", "ahb", "ptp",
1068					      "enet_clk_ref", "enet_out";
1069				fsl,stop-mode = <&gpr 0x10 4>;
1070				status = "disabled";
1071			};
1072
1073			weim: weim@21b8000 {
1074				#address-cells = <2>;
1075				#size-cells = <1>;
1076				compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1077				reg = <0x021b8000 0x4000>;
1078				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1079				clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1080				fsl,weim-cs-gpr = <&gpr>;
1081				status = "disabled";
1082			};
1083
1084			ocotp: efuse@21bc000 {
1085				#address-cells = <1>;
1086				#size-cells = <1>;
1087				compatible = "fsl,imx6sx-ocotp", "syscon";
1088				reg = <0x021bc000 0x4000>;
1089				clocks = <&clks IMX6SX_CLK_OCOTP>;
1090
1091				cpu_speed_grade: speed-grade@10 {
1092					reg = <0x10 4>;
1093				};
1094
1095				tempmon_calib: calib@38 {
1096					reg = <0x38 4>;
1097				};
1098
1099				tempmon_temp_grade: temp-grade@20 {
1100					reg = <0x20 4>;
1101				};
1102			};
1103
1104			sai1: sai@21d4000 {
1105				compatible = "fsl,imx6sx-sai";
1106				reg = <0x021d4000 0x4000>;
1107				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1108				clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1109					 <&clks IMX6SX_CLK_SAI1>,
1110					 <&clks 0>, <&clks 0>;
1111				clock-names = "bus", "mclk1", "mclk2", "mclk3";
1112				dma-names = "rx", "tx";
1113				dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1114				status = "disabled";
1115			};
1116
1117			audmux: audmux@21d8000 {
1118				compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1119				reg = <0x021d8000 0x4000>;
1120				status = "disabled";
1121			};
1122
1123			sai2: sai@21dc000 {
1124				compatible = "fsl,imx6sx-sai";
1125				reg = <0x021dc000 0x4000>;
1126				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1127				clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1128					 <&clks IMX6SX_CLK_SAI2>,
1129					 <&clks 0>, <&clks 0>;
1130				clock-names = "bus", "mclk1", "mclk2", "mclk3";
1131				dma-names = "rx", "tx";
1132				dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1133				status = "disabled";
1134			};
1135
1136			qspi1: spi@21e0000 {
1137				#address-cells = <1>;
1138				#size-cells = <0>;
1139				compatible = "fsl,imx6sx-qspi";
1140				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1141				reg-names = "QuadSPI", "QuadSPI-memory";
1142				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1143				clocks = <&clks IMX6SX_CLK_QSPI1>,
1144					 <&clks IMX6SX_CLK_QSPI1>;
1145				clock-names = "qspi_en", "qspi";
1146				status = "disabled";
1147			};
1148
1149			qspi2: spi@21e4000 {
1150				#address-cells = <1>;
1151				#size-cells = <0>;
1152				compatible = "fsl,imx6sx-qspi";
1153				reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1154				reg-names = "QuadSPI", "QuadSPI-memory";
1155				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1156				clocks = <&clks IMX6SX_CLK_QSPI2>,
1157					 <&clks IMX6SX_CLK_QSPI2>;
1158				clock-names = "qspi_en", "qspi";
1159				status = "disabled";
1160			};
1161
1162			uart2: serial@21e8000 {
1163				compatible = "fsl,imx6sx-uart",
1164					     "fsl,imx6q-uart", "fsl,imx21-uart";
1165				reg = <0x021e8000 0x4000>;
1166				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1167				clocks = <&clks IMX6SX_CLK_UART_IPG>,
1168					 <&clks IMX6SX_CLK_UART_SERIAL>;
1169				clock-names = "ipg", "per";
1170				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1171				dma-names = "rx", "tx";
1172				status = "disabled";
1173			};
1174
1175			uart3: serial@21ec000 {
1176				compatible = "fsl,imx6sx-uart",
1177					     "fsl,imx6q-uart", "fsl,imx21-uart";
1178				reg = <0x021ec000 0x4000>;
1179				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1180				clocks = <&clks IMX6SX_CLK_UART_IPG>,
1181					 <&clks IMX6SX_CLK_UART_SERIAL>;
1182				clock-names = "ipg", "per";
1183				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1184				dma-names = "rx", "tx";
1185				status = "disabled";
1186			};
1187
1188			uart4: serial@21f0000 {
1189				compatible = "fsl,imx6sx-uart",
1190					     "fsl,imx6q-uart", "fsl,imx21-uart";
1191				reg = <0x021f0000 0x4000>;
1192				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1193				clocks = <&clks IMX6SX_CLK_UART_IPG>,
1194					 <&clks IMX6SX_CLK_UART_SERIAL>;
1195				clock-names = "ipg", "per";
1196				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1197				dma-names = "rx", "tx";
1198				status = "disabled";
1199			};
1200
1201			uart5: serial@21f4000 {
1202				compatible = "fsl,imx6sx-uart",
1203					     "fsl,imx6q-uart", "fsl,imx21-uart";
1204				reg = <0x021f4000 0x4000>;
1205				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1206				clocks = <&clks IMX6SX_CLK_UART_IPG>,
1207					 <&clks IMX6SX_CLK_UART_SERIAL>;
1208				clock-names = "ipg", "per";
1209				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1210				dma-names = "rx", "tx";
1211				status = "disabled";
1212			};
1213
1214			i2c4: i2c@21f8000 {
1215				#address-cells = <1>;
1216				#size-cells = <0>;
1217				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1218				reg = <0x021f8000 0x4000>;
1219				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1220				clocks = <&clks IMX6SX_CLK_I2C4>;
1221				status = "disabled";
1222			};
1223		};
1224
1225		aips3: bus@2200000 {
1226			compatible = "fsl,aips-bus", "simple-bus";
1227			#address-cells = <1>;
1228			#size-cells = <1>;
1229			reg = <0x02200000 0x100000>;
1230			ranges;
1231
1232			spba-bus@2240000 {
1233				compatible = "fsl,spba-bus", "simple-bus";
1234				#address-cells = <1>;
1235				#size-cells = <1>;
1236				reg = <0x02240000 0x40000>;
1237				ranges;
1238
1239				csi1: csi@2214000 {
1240					reg = <0x02214000 0x4000>;
1241					interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1242					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1243						 <&clks IMX6SX_CLK_CSI>,
1244						 <&clks IMX6SX_CLK_DCIC1>;
1245					clock-names = "disp-axi", "csi_mclk", "dcic";
1246					status = "disabled";
1247				};
1248
1249				pxp: pxp@2218000 {
1250					compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1251					reg = <0x02218000 0x4000>;
1252					interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1253					clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1254					clock-names = "axi";
1255					power-domains = <&pd_disp>;
1256					status = "disabled";
1257				};
1258
1259				csi2: csi@221c000 {
1260					reg = <0x0221c000 0x4000>;
1261					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1262					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1263						 <&clks IMX6SX_CLK_CSI>,
1264						 <&clks IMX6SX_CLK_DCIC2>;
1265					clock-names = "disp-axi", "csi_mclk", "dcic";
1266					status = "disabled";
1267				};
1268
1269				lcdif1: lcdif@2220000 {
1270					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1271					reg = <0x02220000 0x4000>;
1272					interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1273					clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1274						 <&clks IMX6SX_CLK_LCDIF_APB>,
1275						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1276					clock-names = "pix", "axi", "disp_axi";
1277					power-domains = <&pd_disp>;
1278					status = "disabled";
1279				};
1280
1281				lcdif2: lcdif@2224000 {
1282					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1283					reg = <0x02224000 0x4000>;
1284					interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1285					clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1286						 <&clks IMX6SX_CLK_LCDIF_APB>,
1287						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1288					clock-names = "pix", "axi", "disp_axi";
1289					power-domains = <&pd_disp>;
1290					status = "disabled";
1291				};
1292
1293				vadc: vadc@2228000 {
1294					reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1295					reg-names = "vadc-vafe", "vadc-vdec";
1296					clocks = <&clks IMX6SX_CLK_VADC>,
1297						 <&clks IMX6SX_CLK_CSI>;
1298					clock-names = "vadc", "csi";
1299					power-domains = <&pd_disp>;
1300					status = "disabled";
1301				};
1302			};
1303
1304			adc1: adc@2280000 {
1305				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1306				reg = <0x02280000 0x4000>;
1307				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1308				clocks = <&clks IMX6SX_CLK_IPG>;
1309				clock-names = "adc";
1310				fsl,adck-max-frequency = <30000000>, <40000000>,
1311							 <20000000>;
1312				status = "disabled";
1313			};
1314
1315			adc2: adc@2284000 {
1316				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1317				reg = <0x02284000 0x4000>;
1318				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1319				clocks = <&clks IMX6SX_CLK_IPG>;
1320				clock-names = "adc";
1321				fsl,adck-max-frequency = <30000000>, <40000000>,
1322							 <20000000>;
1323				status = "disabled";
1324			};
1325
1326			wdog3: watchdog@2288000 {
1327				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1328				reg = <0x02288000 0x4000>;
1329				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1330				clocks = <&clks IMX6SX_CLK_IPG>;
1331				status = "disabled";
1332			};
1333
1334			ecspi5: spi@228c000 {
1335				#address-cells = <1>;
1336				#size-cells = <0>;
1337				compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1338				reg = <0x0228c000 0x4000>;
1339				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1340				clocks = <&clks IMX6SX_CLK_ECSPI5>,
1341					 <&clks IMX6SX_CLK_ECSPI5>;
1342				clock-names = "ipg", "per";
1343				status = "disabled";
1344			};
1345
1346			uart6: serial@22a0000 {
1347				compatible = "fsl,imx6sx-uart",
1348					     "fsl,imx6q-uart", "fsl,imx21-uart";
1349				reg = <0x022a0000 0x4000>;
1350				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1351				clocks = <&clks IMX6SX_CLK_UART_IPG>,
1352					 <&clks IMX6SX_CLK_UART_SERIAL>;
1353				clock-names = "ipg", "per";
1354				dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1355				dma-names = "rx", "tx";
1356				status = "disabled";
1357			};
1358
1359			pwm5: pwm@22a4000 {
1360				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1361				reg = <0x022a4000 0x4000>;
1362				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1363				clocks = <&clks IMX6SX_CLK_PWM5>,
1364					 <&clks IMX6SX_CLK_PWM5>;
1365				clock-names = "ipg", "per";
1366				#pwm-cells = <3>;
1367			};
1368
1369			pwm6: pwm@22a8000 {
1370				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1371				reg = <0x022a8000 0x4000>;
1372				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1373				clocks = <&clks IMX6SX_CLK_PWM6>,
1374					 <&clks IMX6SX_CLK_PWM6>;
1375				clock-names = "ipg", "per";
1376				#pwm-cells = <3>;
1377			};
1378
1379			pwm7: pwm@22ac000 {
1380				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1381				reg = <0x022ac000 0x4000>;
1382				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1383				clocks = <&clks IMX6SX_CLK_PWM7>,
1384					 <&clks IMX6SX_CLK_PWM7>;
1385				clock-names = "ipg", "per";
1386				#pwm-cells = <3>;
1387			};
1388
1389			pwm8: pwm@22b0000 {
1390				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1391				reg = <0x0022b0000 0x4000>;
1392				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1393				clocks = <&clks IMX6SX_CLK_PWM8>,
1394					 <&clks IMX6SX_CLK_PWM8>;
1395				clock-names = "ipg", "per";
1396				#pwm-cells = <3>;
1397			};
1398		};
1399
1400		pcie: pcie@8ffc000 {
1401			compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1402			reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1403			reg-names = "dbi", "config";
1404			#address-cells = <3>;
1405			#size-cells = <2>;
1406			device_type = "pci";
1407			bus-range = <0x00 0xff>;
1408			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1409				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1410			num-lanes = <1>;
1411			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1412			interrupt-names = "msi";
1413			#interrupt-cells = <1>;
1414			interrupt-map-mask = <0 0 0 0x7>;
1415			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1416					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1417					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1418					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1419			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1420				 <&clks IMX6SX_CLK_LVDS1_OUT>,
1421				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1422				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1423			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1424			power-domains = <&pd_disp>, <&pd_pci>;
1425			power-domain-names = "pcie", "pcie_phy";
1426			status = "disabled";
1427		};
1428	};
1429};
1430