1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 idle-states { 57 entry-method = "psci"; 58 59 cpu_sleep_wait: cpu-sleep-wait { 60 compatible = "arm,idle-state"; 61 arm,psci-suspend-param = <0x0010000>; 62 local-timer-stop; 63 entry-latency-us = <100>; 64 exit-latency-us = <50>; 65 min-residency-us = <1000>; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 compatible = "arm,cortex-a7"; 71 device_type = "cpu"; 72 reg = <0>; 73 clock-frequency = <792000000>; 74 clock-latency = <61036>; /* two CLK32 periods */ 75 clocks = <&clks IMX7D_CLK_ARM>; 76 cpu-idle-states = <&cpu_sleep_wait>; 77 }; 78 }; 79 80 ckil: clock-cki { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <32768>; 84 clock-output-names = "ckil"; 85 }; 86 87 osc: clock-osc { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc"; 92 }; 93 94 usbphynop1: usbphynop1 { 95 compatible = "usb-nop-xceiv"; 96 clocks = <&clks IMX7D_USB_PHY1_CLK>; 97 clock-names = "main_clk"; 98 #phy-cells = <0>; 99 }; 100 101 usbphynop3: usbphynop3 { 102 compatible = "usb-nop-xceiv"; 103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 104 clock-names = "main_clk"; 105 power-domains = <&pgc_hsic_phy>; 106 #phy-cells = <0>; 107 }; 108 109 pmu { 110 compatible = "arm,cortex-a7-pmu"; 111 interrupt-parent = <&gpc>; 112 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 113 interrupt-affinity = <&cpu0>; 114 }; 115 116 replicator { 117 /* 118 * non-configurable replicators don't show up on the 119 * AMBA bus. As such no need to add "arm,primecell" 120 */ 121 compatible = "arm,coresight-static-replicator"; 122 123 out-ports { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 /* replicator output ports */ 127 port@0 { 128 reg = <0>; 129 replicator_out_port0: endpoint { 130 remote-endpoint = <&tpiu_in_port>; 131 }; 132 }; 133 134 port@1 { 135 reg = <1>; 136 replicator_out_port1: endpoint { 137 remote-endpoint = <&etr_in_port>; 138 }; 139 }; 140 }; 141 142 in-ports { 143 port { 144 replicator_in_port0: endpoint { 145 remote-endpoint = <&etf_out_port>; 146 }; 147 }; 148 }; 149 }; 150 151 timer { 152 compatible = "arm,armv7-timer"; 153 interrupt-parent = <&intc>; 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 158 }; 159 160 soc { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "simple-bus"; 164 interrupt-parent = <&gpc>; 165 ranges; 166 167 funnel@30041000 { 168 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 169 reg = <0x30041000 0x1000>; 170 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 171 clock-names = "apb_pclk"; 172 173 ca_funnel_in_ports: in-ports { 174 port { 175 ca_funnel_in_port0: endpoint { 176 remote-endpoint = <&etm0_out_port>; 177 }; 178 }; 179 180 /* the other input ports are not connect to anything */ 181 }; 182 183 out-ports { 184 port { 185 ca_funnel_out_port0: endpoint { 186 remote-endpoint = <&hugo_funnel_in_port0>; 187 }; 188 }; 189 190 }; 191 }; 192 193 etm@3007c000 { 194 compatible = "arm,coresight-etm3x", "arm,primecell"; 195 reg = <0x3007c000 0x1000>; 196 cpu = <&cpu0>; 197 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 198 clock-names = "apb_pclk"; 199 200 out-ports { 201 port { 202 etm0_out_port: endpoint { 203 remote-endpoint = <&ca_funnel_in_port0>; 204 }; 205 }; 206 }; 207 }; 208 209 funnel@30083000 { 210 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 211 reg = <0x30083000 0x1000>; 212 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 213 clock-names = "apb_pclk"; 214 215 in-ports { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 port@0 { 220 reg = <0>; 221 hugo_funnel_in_port0: endpoint { 222 remote-endpoint = <&ca_funnel_out_port0>; 223 }; 224 }; 225 226 port@1 { 227 reg = <1>; 228 hugo_funnel_in_port1: endpoint { 229 /* M4 input */ 230 }; 231 }; 232 /* the other input ports are not connect to anything */ 233 }; 234 235 out-ports { 236 port { 237 hugo_funnel_out_port0: endpoint { 238 remote-endpoint = <&etf_in_port>; 239 }; 240 }; 241 }; 242 }; 243 244 etf@30084000 { 245 compatible = "arm,coresight-tmc", "arm,primecell"; 246 reg = <0x30084000 0x1000>; 247 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 248 clock-names = "apb_pclk"; 249 250 in-ports { 251 port { 252 etf_in_port: endpoint { 253 remote-endpoint = <&hugo_funnel_out_port0>; 254 }; 255 }; 256 }; 257 258 out-ports { 259 port { 260 etf_out_port: endpoint { 261 remote-endpoint = <&replicator_in_port0>; 262 }; 263 }; 264 }; 265 }; 266 267 etr@30086000 { 268 compatible = "arm,coresight-tmc", "arm,primecell"; 269 reg = <0x30086000 0x1000>; 270 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 271 clock-names = "apb_pclk"; 272 273 in-ports { 274 port { 275 etr_in_port: endpoint { 276 remote-endpoint = <&replicator_out_port1>; 277 }; 278 }; 279 }; 280 }; 281 282 tpiu@30087000 { 283 compatible = "arm,coresight-tpiu", "arm,primecell"; 284 reg = <0x30087000 0x1000>; 285 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 286 clock-names = "apb_pclk"; 287 288 in-ports { 289 port { 290 tpiu_in_port: endpoint { 291 remote-endpoint = <&replicator_out_port0>; 292 }; 293 }; 294 }; 295 }; 296 297 intc: interrupt-controller@31001000 { 298 compatible = "arm,cortex-a7-gic"; 299 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 300 #interrupt-cells = <3>; 301 interrupt-controller; 302 interrupt-parent = <&intc>; 303 reg = <0x31001000 0x1000>, 304 <0x31002000 0x2000>, 305 <0x31004000 0x2000>, 306 <0x31006000 0x2000>; 307 }; 308 309 aips1: bus@30000000 { 310 compatible = "fsl,aips-bus", "simple-bus"; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 reg = <0x30000000 0x400000>; 314 ranges; 315 316 gpio1: gpio@30200000 { 317 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 318 reg = <0x30200000 0x10000>; 319 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 320 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 321 gpio-controller; 322 #gpio-cells = <2>; 323 interrupt-controller; 324 #interrupt-cells = <2>; 325 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 326 }; 327 328 gpio2: gpio@30210000 { 329 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 330 reg = <0x30210000 0x10000>; 331 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 13 32>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 gpio-ranges = <&iomuxc 0 45 29>; 350 }; 351 352 gpio4: gpio@30230000 { 353 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 354 reg = <0x30230000 0x10000>; 355 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 gpio-ranges = <&iomuxc 0 74 24>; 362 }; 363 364 gpio5: gpio@30240000 { 365 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 366 reg = <0x30240000 0x10000>; 367 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 gpio-ranges = <&iomuxc 0 98 18>; 374 }; 375 376 gpio6: gpio@30250000 { 377 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 378 reg = <0x30250000 0x10000>; 379 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 gpio-ranges = <&iomuxc 0 116 23>; 386 }; 387 388 gpio7: gpio@30260000 { 389 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 390 reg = <0x30260000 0x10000>; 391 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 gpio-ranges = <&iomuxc 0 139 16>; 398 }; 399 400 wdog1: watchdog@30280000 { 401 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 402 reg = <0x30280000 0x10000>; 403 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 405 }; 406 407 wdog2: watchdog@30290000 { 408 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 409 reg = <0x30290000 0x10000>; 410 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 412 status = "disabled"; 413 }; 414 415 wdog3: watchdog@302a0000 { 416 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 417 reg = <0x302a0000 0x10000>; 418 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 420 status = "disabled"; 421 }; 422 423 wdog4: watchdog@302b0000 { 424 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 425 reg = <0x302b0000 0x10000>; 426 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 428 status = "disabled"; 429 }; 430 431 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 432 compatible = "fsl,imx7d-iomuxc-lpsr"; 433 reg = <0x302c0000 0x10000>; 434 fsl,input-sel = <&iomuxc>; 435 }; 436 437 gpt1: timer@302d0000 { 438 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 439 reg = <0x302d0000 0x10000>; 440 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 442 <&clks IMX7D_GPT1_ROOT_CLK>; 443 clock-names = "ipg", "per"; 444 }; 445 446 gpt2: timer@302e0000 { 447 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 448 reg = <0x302e0000 0x10000>; 449 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 451 <&clks IMX7D_GPT2_ROOT_CLK>; 452 clock-names = "ipg", "per"; 453 status = "disabled"; 454 }; 455 456 gpt3: timer@302f0000 { 457 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 458 reg = <0x302f0000 0x10000>; 459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 461 <&clks IMX7D_GPT3_ROOT_CLK>; 462 clock-names = "ipg", "per"; 463 status = "disabled"; 464 }; 465 466 gpt4: timer@30300000 { 467 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 468 reg = <0x30300000 0x10000>; 469 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 471 <&clks IMX7D_GPT4_ROOT_CLK>; 472 clock-names = "ipg", "per"; 473 status = "disabled"; 474 }; 475 476 kpp: keypad@30320000 { 477 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 478 reg = <0x30320000 0x10000>; 479 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 481 status = "disabled"; 482 }; 483 484 iomuxc: pinctrl@30330000 { 485 compatible = "fsl,imx7d-iomuxc"; 486 reg = <0x30330000 0x10000>; 487 }; 488 489 gpr: iomuxc-gpr@30340000 { 490 compatible = "fsl,imx7d-iomuxc-gpr", 491 "fsl,imx6q-iomuxc-gpr", "syscon", 492 "simple-mfd"; 493 reg = <0x30340000 0x10000>; 494 495 mux: mux-controller { 496 compatible = "mmio-mux"; 497 #mux-control-cells = <0>; 498 mux-reg-masks = <0x14 0x00000010>; 499 }; 500 501 video_mux: csi-mux { 502 compatible = "video-mux"; 503 mux-controls = <&mux 0>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 508 port@0 { 509 reg = <0>; 510 }; 511 512 port@1 { 513 reg = <1>; 514 515 csi_mux_from_mipi_vc0: endpoint { 516 remote-endpoint = <&mipi_vc0_to_csi_mux>; 517 }; 518 }; 519 520 port@2 { 521 reg = <2>; 522 523 csi_mux_to_csi: endpoint { 524 remote-endpoint = <&csi_from_csi_mux>; 525 }; 526 }; 527 }; 528 }; 529 530 ocotp: efuse@30350000 { 531 #address-cells = <1>; 532 #size-cells = <1>; 533 compatible = "fsl,imx7d-ocotp", "syscon"; 534 reg = <0x30350000 0x10000>; 535 clocks = <&clks IMX7D_OCOTP_CLK>; 536 537 tempmon_calib: calib@3c { 538 reg = <0x3c 0x4>; 539 }; 540 541 fuse_grade: fuse-grade@10 { 542 reg = <0x10 0x4>; 543 }; 544 }; 545 546 anatop: anatop@30360000 { 547 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 548 "syscon", "simple-mfd"; 549 reg = <0x30360000 0x10000>; 550 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 552 553 reg_1p0d: regulator-vdd1p0d { 554 compatible = "fsl,anatop-regulator"; 555 regulator-name = "vdd1p0d"; 556 regulator-min-microvolt = <800000>; 557 regulator-max-microvolt = <1200000>; 558 anatop-reg-offset = <0x210>; 559 anatop-vol-bit-shift = <8>; 560 anatop-vol-bit-width = <5>; 561 anatop-min-bit-val = <8>; 562 anatop-min-voltage = <800000>; 563 anatop-max-voltage = <1200000>; 564 anatop-enable-bit = <0>; 565 }; 566 567 reg_1p2: regulator-vdd1p2 { 568 compatible = "fsl,anatop-regulator"; 569 regulator-name = "vdd1p2"; 570 regulator-min-microvolt = <1100000>; 571 regulator-max-microvolt = <1300000>; 572 anatop-reg-offset = <0x220>; 573 anatop-vol-bit-shift = <8>; 574 anatop-vol-bit-width = <5>; 575 anatop-min-bit-val = <0x14>; 576 anatop-min-voltage = <1100000>; 577 anatop-max-voltage = <1300000>; 578 anatop-enable-bit = <0>; 579 }; 580 581 tempmon: tempmon { 582 compatible = "fsl,imx7d-tempmon"; 583 interrupt-parent = <&gpc>; 584 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 585 fsl,tempmon = <&anatop>; 586 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 587 nvmem-cell-names = "calib", "temp_grade"; 588 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 589 }; 590 }; 591 592 snvs: snvs@30370000 { 593 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 594 reg = <0x30370000 0x10000>; 595 596 snvs_rtc: snvs-rtc-lp { 597 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 598 regmap = <&snvs>; 599 offset = <0x34>; 600 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clks IMX7D_SNVS_CLK>; 603 clock-names = "snvs-rtc"; 604 }; 605 606 snvs_pwrkey: snvs-powerkey { 607 compatible = "fsl,sec-v4.0-pwrkey"; 608 regmap = <&snvs>; 609 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clks IMX7D_SNVS_CLK>; 611 clock-names = "snvs-pwrkey"; 612 linux,keycode = <KEY_POWER>; 613 wakeup-source; 614 status = "disabled"; 615 }; 616 }; 617 618 clks: clock-controller@30380000 { 619 compatible = "fsl,imx7d-ccm"; 620 reg = <0x30380000 0x10000>; 621 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 623 #clock-cells = <1>; 624 clocks = <&ckil>, <&osc>; 625 clock-names = "ckil", "osc"; 626 }; 627 628 src: reset-controller@30390000 { 629 compatible = "fsl,imx7d-src", "syscon"; 630 reg = <0x30390000 0x10000>; 631 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 632 #reset-cells = <1>; 633 }; 634 635 gpc: gpc@303a0000 { 636 compatible = "fsl,imx7d-gpc"; 637 reg = <0x303a0000 0x10000>; 638 interrupt-controller; 639 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 640 #interrupt-cells = <3>; 641 interrupt-parent = <&intc>; 642 #power-domain-cells = <1>; 643 644 pgc { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 pgc_mipi_phy: power-domain@0 { 649 #power-domain-cells = <0>; 650 reg = <0>; 651 power-supply = <®_1p0d>; 652 }; 653 654 pgc_pcie_phy: power-domain@1 { 655 #power-domain-cells = <0>; 656 reg = <1>; 657 power-supply = <®_1p0d>; 658 }; 659 660 pgc_hsic_phy: power-domain@2 { 661 #power-domain-cells = <0>; 662 reg = <2>; 663 power-supply = <®_1p2>; 664 }; 665 }; 666 }; 667 }; 668 669 aips2: bus@30400000 { 670 compatible = "fsl,aips-bus", "simple-bus"; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 reg = <0x30400000 0x400000>; 674 ranges; 675 676 adc1: adc@30610000 { 677 compatible = "fsl,imx7d-adc"; 678 reg = <0x30610000 0x10000>; 679 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 681 clock-names = "adc"; 682 #io-channel-cells = <1>; 683 status = "disabled"; 684 }; 685 686 adc2: adc@30620000 { 687 compatible = "fsl,imx7d-adc"; 688 reg = <0x30620000 0x10000>; 689 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 691 clock-names = "adc"; 692 #io-channel-cells = <1>; 693 status = "disabled"; 694 }; 695 696 ecspi4: spi@30630000 { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 700 reg = <0x30630000 0x10000>; 701 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 703 <&clks IMX7D_ECSPI4_ROOT_CLK>; 704 clock-names = "ipg", "per"; 705 status = "disabled"; 706 }; 707 708 pwm1: pwm@30660000 { 709 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 710 reg = <0x30660000 0x10000>; 711 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 713 <&clks IMX7D_PWM1_ROOT_CLK>; 714 clock-names = "ipg", "per"; 715 #pwm-cells = <3>; 716 status = "disabled"; 717 }; 718 719 pwm2: pwm@30670000 { 720 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 721 reg = <0x30670000 0x10000>; 722 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 724 <&clks IMX7D_PWM2_ROOT_CLK>; 725 clock-names = "ipg", "per"; 726 #pwm-cells = <3>; 727 status = "disabled"; 728 }; 729 730 pwm3: pwm@30680000 { 731 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 732 reg = <0x30680000 0x10000>; 733 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 735 <&clks IMX7D_PWM3_ROOT_CLK>; 736 clock-names = "ipg", "per"; 737 #pwm-cells = <3>; 738 status = "disabled"; 739 }; 740 741 pwm4: pwm@30690000 { 742 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 743 reg = <0x30690000 0x10000>; 744 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 746 <&clks IMX7D_PWM4_ROOT_CLK>; 747 clock-names = "ipg", "per"; 748 #pwm-cells = <3>; 749 status = "disabled"; 750 }; 751 752 csi: csi@30710000 { 753 compatible = "fsl,imx7-csi"; 754 reg = <0x30710000 0x10000>; 755 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&clks IMX7D_CLK_DUMMY>, 757 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 758 <&clks IMX7D_CLK_DUMMY>; 759 clock-names = "axi", "mclk", "dcic"; 760 status = "disabled"; 761 762 port { 763 csi_from_csi_mux: endpoint { 764 remote-endpoint = <&csi_mux_to_csi>; 765 }; 766 }; 767 }; 768 769 lcdif: lcdif@30730000 { 770 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 771 reg = <0x30730000 0x10000>; 772 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 774 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 775 clock-names = "pix", "axi"; 776 status = "disabled"; 777 }; 778 779 mipi_csi: mipi-csi@30750000 { 780 compatible = "fsl,imx7-mipi-csi2"; 781 reg = <0x30750000 0x10000>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 786 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 787 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 788 clock-names = "pclk", "wrap", "phy"; 789 power-domains = <&pgc_mipi_phy>; 790 phy-supply = <®_1p0d>; 791 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 792 reset-names = "mrst"; 793 status = "disabled"; 794 795 port@0 { 796 reg = <0>; 797 }; 798 799 port@1 { 800 reg = <1>; 801 802 mipi_vc0_to_csi_mux: endpoint { 803 remote-endpoint = <&csi_mux_from_mipi_vc0>; 804 }; 805 }; 806 }; 807 }; 808 809 aips3: bus@30800000 { 810 compatible = "fsl,aips-bus", "simple-bus"; 811 #address-cells = <1>; 812 #size-cells = <1>; 813 reg = <0x30800000 0x400000>; 814 ranges; 815 816 spba-bus@30800000 { 817 compatible = "fsl,spba-bus", "simple-bus"; 818 #address-cells = <1>; 819 #size-cells = <1>; 820 reg = <0x30800000 0x100000>; 821 ranges; 822 823 ecspi1: spi@30820000 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 827 reg = <0x30820000 0x10000>; 828 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 830 <&clks IMX7D_ECSPI1_ROOT_CLK>; 831 clock-names = "ipg", "per"; 832 status = "disabled"; 833 }; 834 835 ecspi2: spi@30830000 { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 839 reg = <0x30830000 0x10000>; 840 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 842 <&clks IMX7D_ECSPI2_ROOT_CLK>; 843 clock-names = "ipg", "per"; 844 status = "disabled"; 845 }; 846 847 ecspi3: spi@30840000 { 848 #address-cells = <1>; 849 #size-cells = <0>; 850 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 851 reg = <0x30840000 0x10000>; 852 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 854 <&clks IMX7D_ECSPI3_ROOT_CLK>; 855 clock-names = "ipg", "per"; 856 status = "disabled"; 857 }; 858 859 uart1: serial@30860000 { 860 compatible = "fsl,imx7d-uart", 861 "fsl,imx6q-uart"; 862 reg = <0x30860000 0x10000>; 863 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 865 <&clks IMX7D_UART1_ROOT_CLK>; 866 clock-names = "ipg", "per"; 867 status = "disabled"; 868 }; 869 870 uart2: serial@30890000 { 871 compatible = "fsl,imx7d-uart", 872 "fsl,imx6q-uart"; 873 reg = <0x30890000 0x10000>; 874 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 876 <&clks IMX7D_UART2_ROOT_CLK>; 877 clock-names = "ipg", "per"; 878 status = "disabled"; 879 }; 880 881 uart3: serial@30880000 { 882 compatible = "fsl,imx7d-uart", 883 "fsl,imx6q-uart"; 884 reg = <0x30880000 0x10000>; 885 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 887 <&clks IMX7D_UART3_ROOT_CLK>; 888 clock-names = "ipg", "per"; 889 status = "disabled"; 890 }; 891 892 sai1: sai@308a0000 { 893 #sound-dai-cells = <0>; 894 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 895 reg = <0x308a0000 0x10000>; 896 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 898 <&clks IMX7D_SAI1_ROOT_CLK>, 899 <&clks IMX7D_CLK_DUMMY>, 900 <&clks IMX7D_CLK_DUMMY>; 901 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 902 dma-names = "rx", "tx"; 903 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 904 status = "disabled"; 905 }; 906 907 sai2: sai@308b0000 { 908 #sound-dai-cells = <0>; 909 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 910 reg = <0x308b0000 0x10000>; 911 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 913 <&clks IMX7D_SAI2_ROOT_CLK>, 914 <&clks IMX7D_CLK_DUMMY>, 915 <&clks IMX7D_CLK_DUMMY>; 916 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 917 dma-names = "rx", "tx"; 918 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 919 status = "disabled"; 920 }; 921 922 sai3: sai@308c0000 { 923 #sound-dai-cells = <0>; 924 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 925 reg = <0x308c0000 0x10000>; 926 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 928 <&clks IMX7D_SAI3_ROOT_CLK>, 929 <&clks IMX7D_CLK_DUMMY>, 930 <&clks IMX7D_CLK_DUMMY>; 931 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 932 dma-names = "rx", "tx"; 933 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 934 status = "disabled"; 935 }; 936 }; 937 938 crypto: crypto@30900000 { 939 compatible = "fsl,sec-v4.0"; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 reg = <0x30900000 0x40000>; 943 ranges = <0 0x30900000 0x40000>; 944 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clks IMX7D_CAAM_CLK>, 946 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 947 clock-names = "ipg", "aclk"; 948 949 sec_jr0: jr@1000 { 950 compatible = "fsl,sec-v4.0-job-ring"; 951 reg = <0x1000 0x1000>; 952 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 953 }; 954 955 sec_jr1: jr@2000 { 956 compatible = "fsl,sec-v4.0-job-ring"; 957 reg = <0x2000 0x1000>; 958 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 959 }; 960 961 sec_jr2: jr@3000 { 962 compatible = "fsl,sec-v4.0-job-ring"; 963 reg = <0x3000 0x1000>; 964 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 965 }; 966 }; 967 968 flexcan1: can@30a00000 { 969 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 970 reg = <0x30a00000 0x10000>; 971 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&clks IMX7D_CLK_DUMMY>, 973 <&clks IMX7D_CAN1_ROOT_CLK>; 974 clock-names = "ipg", "per"; 975 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 976 status = "disabled"; 977 }; 978 979 flexcan2: can@30a10000 { 980 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 981 reg = <0x30a10000 0x10000>; 982 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clks IMX7D_CLK_DUMMY>, 984 <&clks IMX7D_CAN2_ROOT_CLK>; 985 clock-names = "ipg", "per"; 986 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 987 status = "disabled"; 988 }; 989 990 i2c1: i2c@30a20000 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 994 reg = <0x30a20000 0x10000>; 995 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 997 status = "disabled"; 998 }; 999 1000 i2c2: i2c@30a30000 { 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1004 reg = <0x30a30000 0x10000>; 1005 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1007 status = "disabled"; 1008 }; 1009 1010 i2c3: i2c@30a40000 { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1014 reg = <0x30a40000 0x10000>; 1015 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1017 status = "disabled"; 1018 }; 1019 1020 i2c4: i2c@30a50000 { 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1024 reg = <0x30a50000 0x10000>; 1025 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1027 status = "disabled"; 1028 }; 1029 1030 uart4: serial@30a60000 { 1031 compatible = "fsl,imx7d-uart", 1032 "fsl,imx6q-uart"; 1033 reg = <0x30a60000 0x10000>; 1034 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1036 <&clks IMX7D_UART4_ROOT_CLK>; 1037 clock-names = "ipg", "per"; 1038 status = "disabled"; 1039 }; 1040 1041 uart5: serial@30a70000 { 1042 compatible = "fsl,imx7d-uart", 1043 "fsl,imx6q-uart"; 1044 reg = <0x30a70000 0x10000>; 1045 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1047 <&clks IMX7D_UART5_ROOT_CLK>; 1048 clock-names = "ipg", "per"; 1049 status = "disabled"; 1050 }; 1051 1052 uart6: serial@30a80000 { 1053 compatible = "fsl,imx7d-uart", 1054 "fsl,imx6q-uart"; 1055 reg = <0x30a80000 0x10000>; 1056 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1058 <&clks IMX7D_UART6_ROOT_CLK>; 1059 clock-names = "ipg", "per"; 1060 status = "disabled"; 1061 }; 1062 1063 uart7: serial@30a90000 { 1064 compatible = "fsl,imx7d-uart", 1065 "fsl,imx6q-uart"; 1066 reg = <0x30a90000 0x10000>; 1067 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1069 <&clks IMX7D_UART7_ROOT_CLK>; 1070 clock-names = "ipg", "per"; 1071 status = "disabled"; 1072 }; 1073 1074 mu0a: mailbox@30aa0000 { 1075 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1076 reg = <0x30aa0000 0x10000>; 1077 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1079 #mbox-cells = <2>; 1080 status = "disabled"; 1081 }; 1082 1083 mu0b: mailbox@30ab0000 { 1084 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1085 reg = <0x30ab0000 0x10000>; 1086 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1088 #mbox-cells = <2>; 1089 fsl,mu-side-b; 1090 status = "disabled"; 1091 }; 1092 1093 usbotg1: usb@30b10000 { 1094 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1095 reg = <0x30b10000 0x200>; 1096 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1098 fsl,usbphy = <&usbphynop1>; 1099 fsl,usbmisc = <&usbmisc1 0>; 1100 phy-clkgate-delay-us = <400>; 1101 status = "disabled"; 1102 }; 1103 1104 usbh: usb@30b30000 { 1105 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1106 reg = <0x30b30000 0x200>; 1107 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1109 fsl,usbphy = <&usbphynop3>; 1110 fsl,usbmisc = <&usbmisc3 0>; 1111 phy_type = "hsic"; 1112 dr_mode = "host"; 1113 phy-clkgate-delay-us = <400>; 1114 status = "disabled"; 1115 }; 1116 1117 usbmisc1: usbmisc@30b10200 { 1118 #index-cells = <1>; 1119 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1120 reg = <0x30b10200 0x200>; 1121 }; 1122 1123 usbmisc3: usbmisc@30b30200 { 1124 #index-cells = <1>; 1125 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1126 reg = <0x30b30200 0x200>; 1127 }; 1128 1129 usdhc1: mmc@30b40000 { 1130 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1131 reg = <0x30b40000 0x10000>; 1132 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1134 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1135 <&clks IMX7D_USDHC1_ROOT_CLK>; 1136 clock-names = "ipg", "ahb", "per"; 1137 bus-width = <4>; 1138 status = "disabled"; 1139 }; 1140 1141 usdhc2: mmc@30b50000 { 1142 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1143 reg = <0x30b50000 0x10000>; 1144 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1146 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1147 <&clks IMX7D_USDHC2_ROOT_CLK>; 1148 clock-names = "ipg", "ahb", "per"; 1149 bus-width = <4>; 1150 status = "disabled"; 1151 }; 1152 1153 usdhc3: mmc@30b60000 { 1154 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1155 reg = <0x30b60000 0x10000>; 1156 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1158 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1159 <&clks IMX7D_USDHC3_ROOT_CLK>; 1160 clock-names = "ipg", "ahb", "per"; 1161 bus-width = <4>; 1162 status = "disabled"; 1163 }; 1164 1165 qspi: spi@30bb0000 { 1166 compatible = "fsl,imx7d-qspi"; 1167 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1168 reg-names = "QuadSPI", "QuadSPI-memory"; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1173 <&clks IMX7D_QSPI_ROOT_CLK>; 1174 clock-names = "qspi_en", "qspi"; 1175 status = "disabled"; 1176 }; 1177 1178 sdma: sdma@30bd0000 { 1179 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1180 reg = <0x30bd0000 0x10000>; 1181 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1183 <&clks IMX7D_SDMA_CORE_CLK>; 1184 clock-names = "ipg", "ahb"; 1185 #dma-cells = <3>; 1186 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1187 }; 1188 1189 fec1: ethernet@30be0000 { 1190 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1191 reg = <0x30be0000 0x10000>; 1192 interrupt-names = "int0", "int1", "int2", "pps"; 1193 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1197 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1198 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1199 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1200 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1201 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1202 clock-names = "ipg", "ahb", "ptp", 1203 "enet_clk_ref", "enet_out"; 1204 fsl,num-tx-queues = <3>; 1205 fsl,num-rx-queues = <3>; 1206 fsl,stop-mode = <&gpr 0x10 3>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 dma_apbh: dma-apbh@33000000 { 1212 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1213 reg = <0x33000000 0x2000>; 1214 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1218 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1219 #dma-cells = <1>; 1220 dma-channels = <4>; 1221 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1222 }; 1223 1224 gpmi: nand-controller@33002000{ 1225 compatible = "fsl,imx7d-gpmi-nand"; 1226 #address-cells = <1>; 1227 #size-cells = <1>; 1228 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1229 reg-names = "gpmi-nand", "bch"; 1230 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-names = "bch"; 1232 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1233 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1234 clock-names = "gpmi_io", "gpmi_bch_apb"; 1235 dmas = <&dma_apbh 0>; 1236 dma-names = "rx-tx"; 1237 status = "disabled"; 1238 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1240 }; 1241 }; 1242}; 1243