1/* 2 * Copyright 2017-2018 Sean Wang <sean.wang@mediatek.com> 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7/dts-v1/; 8#include <dt-bindings/input/input.h> 9#include "mt7623n.dtsi" 10#include "mt6323.dtsi" 11 12/ { 13 model = "Bananapi BPI-R2"; 14 compatible = "bananapi,bpi-r2", "mediatek,mt7623"; 15 16 aliases { 17 serial2 = &uart2; 18 }; 19 20 chosen { 21 stdout-path = "serial2:115200n8"; 22 }; 23 24 connector { 25 compatible = "hdmi-connector"; 26 label = "hdmi"; 27 type = "d"; 28 ddc-i2c-bus = <&hdmiddc0>; 29 30 port { 31 hdmi_connector_in: endpoint { 32 remote-endpoint = <&hdmi0_out>; 33 }; 34 }; 35 }; 36 37 cpus { 38 cpu@0 { 39 proc-supply = <&mt6323_vproc_reg>; 40 }; 41 42 cpu@1 { 43 proc-supply = <&mt6323_vproc_reg>; 44 }; 45 46 cpu@2 { 47 proc-supply = <&mt6323_vproc_reg>; 48 }; 49 50 cpu@3 { 51 proc-supply = <&mt6323_vproc_reg>; 52 }; 53 }; 54 55 reg_1p8v: regulator-1p8v { 56 compatible = "regulator-fixed"; 57 regulator-name = "fixed-1.8V"; 58 regulator-min-microvolt = <1800000>; 59 regulator-max-microvolt = <1800000>; 60 regulator-boot-on; 61 regulator-always-on; 62 }; 63 64 reg_3p3v: regulator-3p3v { 65 compatible = "regulator-fixed"; 66 regulator-name = "fixed-3.3V"; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 regulator-boot-on; 70 regulator-always-on; 71 }; 72 73 reg_5v: regulator-5v { 74 compatible = "regulator-fixed"; 75 regulator-name = "fixed-5V"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 regulator-boot-on; 79 regulator-always-on; 80 }; 81 82 reg_vgpu: fixedregulator@0 { 83 compatible = "regulator-fixed"; 84 regulator-name = "vdd_fixed_vgpu"; 85 regulator-min-microvolt = <1150000>; 86 regulator-max-microvolt = <1150000>; 87 }; 88 89 gpio-keys { 90 compatible = "gpio-keys"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&key_pins_a>; 93 94 factory { 95 label = "factory"; 96 linux,code = <BTN_0>; 97 gpios = <&pio 256 GPIO_ACTIVE_LOW>; 98 }; 99 100 wps { 101 label = "wps"; 102 linux,code = <KEY_WPS_BUTTON>; 103 gpios = <&pio 257 GPIO_ACTIVE_HIGH>; 104 }; 105 }; 106 107 leds { 108 compatible = "gpio-leds"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&led_pins_a>; 111 112 blue { 113 label = "bpi-r2:pio:blue"; 114 gpios = <&pio 240 GPIO_ACTIVE_LOW>; 115 default-state = "off"; 116 }; 117 118 green { 119 label = "bpi-r2:pio:green"; 120 gpios = <&pio 241 GPIO_ACTIVE_LOW>; 121 default-state = "off"; 122 }; 123 124 red { 125 label = "bpi-r2:pio:red"; 126 gpios = <&pio 239 GPIO_ACTIVE_LOW>; 127 default-state = "off"; 128 }; 129 }; 130 131 memory@80000000 { 132 device_type = "memory"; 133 reg = <0 0x80000000 0 0x80000000>; 134 }; 135}; 136 137&bls { 138 status = "okay"; 139}; 140 141&btif { 142 status = "okay"; 143}; 144 145&cec { 146 status = "okay"; 147}; 148 149&cir { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&cir_pins_a>; 152 status = "okay"; 153}; 154 155&crypto { 156 status = "okay"; 157}; 158 159&dpi0 { 160 status = "okay"; 161 162 ports { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 port@0 { 166 reg = <0>; 167 dpi0_out: endpoint { 168 remote-endpoint = <&hdmi0_in>; 169 }; 170 }; 171 }; 172}; 173 174ð { 175 status = "okay"; 176 177 gmac0: mac@0 { 178 compatible = "mediatek,eth-mac"; 179 reg = <0>; 180 phy-mode = "trgmii"; 181 182 fixed-link { 183 speed = <1000>; 184 full-duplex; 185 pause; 186 }; 187 }; 188 189 mdio: mdio-bus { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 switch@0 { 194 compatible = "mediatek,mt7530"; 195 reg = <0>; 196 reset-gpios = <&pio 33 0>; 197 core-supply = <&mt6323_vpa_reg>; 198 io-supply = <&mt6323_vemc3v3_reg>; 199 200 ports { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 204 port@0 { 205 reg = <0>; 206 label = "wan"; 207 }; 208 209 port@1 { 210 reg = <1>; 211 label = "lan0"; 212 }; 213 214 port@2 { 215 reg = <2>; 216 label = "lan1"; 217 }; 218 219 port@3 { 220 reg = <3>; 221 label = "lan2"; 222 }; 223 224 port@4 { 225 reg = <4>; 226 label = "lan3"; 227 }; 228 229 port@6 { 230 reg = <6>; 231 label = "cpu"; 232 ethernet = <&gmac0>; 233 phy-mode = "trgmii"; 234 235 fixed-link { 236 speed = <1000>; 237 full-duplex; 238 pause; 239 }; 240 }; 241 }; 242 }; 243 }; 244}; 245 246&hdmi0 { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&hdmi_pins_a>; 249 status = "okay"; 250 251 ports { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 port@0 { 255 reg = <0>; 256 hdmi0_in: endpoint { 257 remote-endpoint = <&dpi0_out>; 258 }; 259 }; 260 261 port@1 { 262 reg = <1>; 263 hdmi0_out: endpoint { 264 remote-endpoint = <&hdmi_connector_in>; 265 }; 266 }; 267 }; 268}; 269 270&hdmiddc0 { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&hdmi_ddc_pins_a>; 273 status = "okay"; 274}; 275 276&hdmi_phy { 277 mediatek,ibias = <0xa>; 278 mediatek,ibias_up = <0x1c>; 279 status = "okay"; 280}; 281 282&i2c0 { 283 pinctrl-names = "default"; 284 pinctrl-0 = <&i2c0_pins_a>; 285 status = "okay"; 286}; 287 288&i2c1 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&i2c1_pins_a>; 291 status = "okay"; 292}; 293 294&mali { 295 mali-supply = <®_vgpu>; 296 status = "okay"; 297}; 298 299&mmc0 { 300 pinctrl-names = "default", "state_uhs"; 301 pinctrl-0 = <&mmc0_pins_default>; 302 pinctrl-1 = <&mmc0_pins_uhs>; 303 status = "okay"; 304 bus-width = <8>; 305 max-frequency = <50000000>; 306 cap-mmc-highspeed; 307 vmmc-supply = <®_3p3v>; 308 vqmmc-supply = <®_1p8v>; 309 non-removable; 310}; 311 312&mmc1 { 313 pinctrl-names = "default", "state_uhs"; 314 pinctrl-0 = <&mmc1_pins_default>; 315 pinctrl-1 = <&mmc1_pins_uhs>; 316 status = "okay"; 317 bus-width = <4>; 318 max-frequency = <50000000>; 319 cap-sd-highspeed; 320 cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; 321 vmmc-supply = <®_3p3v>; 322 vqmmc-supply = <®_3p3v>; 323}; 324 325&mt6323_leds { 326 status = "okay"; 327 328 led@0 { 329 reg = <0>; 330 label = "bpi-r2:isink:green"; 331 default-state = "off"; 332 }; 333 334 led@1 { 335 reg = <1>; 336 label = "bpi-r2:isink:red"; 337 default-state = "off"; 338 }; 339 340 led@2 { 341 reg = <2>; 342 label = "bpi-r2:isink:blue"; 343 default-state = "off"; 344 }; 345}; 346 347&pcie { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pcie_default>; 350 status = "okay"; 351 352 pcie@0,0 { 353 status = "okay"; 354 }; 355 356 pcie@1,0 { 357 status = "okay"; 358 }; 359}; 360 361&pcie0_phy { 362 status = "okay"; 363}; 364 365&pcie1_phy { 366 status = "okay"; 367}; 368 369&pwm { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pwm_pins_a>; 372 status = "okay"; 373}; 374 375&spi0 { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&spi0_pins_a>; 378 status = "okay"; 379}; 380 381&uart0 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&uart0_pins_a>; 384 status = "okay"; 385}; 386 387&uart1 { 388 pinctrl-names = "default"; 389 pinctrl-0 = <&uart1_pins_a>; 390 status = "okay"; 391}; 392 393&uart2 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&uart2_pins_a>; 396 status = "okay"; 397}; 398 399&usb1 { 400 vusb33-supply = <®_3p3v>; 401 vbus-supply = <®_5v>; 402 status = "okay"; 403}; 404 405&usb2 { 406 vusb33-supply = <®_3p3v>; 407 vbus-supply = <®_5v>; 408 status = "okay"; 409}; 410 411&u3phy1 { 412 status = "okay"; 413}; 414 415&u3phy2 { 416 status = "okay"; 417}; 418