• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *  Copyright (C) 2011 Picochip, Jamie Iles
4 */
5/ {
6	model = "Picochip picoXcell PC3X3";
7	compatible = "picochip,pc3x3";
8	#address-cells = <1>;
9	#size-cells = <1>;
10
11	cpus {
12		#address-cells = <0>;
13		#size-cells = <0>;
14
15		cpu {
16			compatible = "arm,arm1176jz-s";
17			device_type = "cpu";
18			cpu-clock = <&arm_clk>, "cpu";
19			d-cache-line-size = <32>;
20			d-cache-size = <32768>;
21			i-cache-line-size = <32>;
22			i-cache-size = <32768>;
23		};
24	};
25
26	clocks {
27		#address-cells = <1>;
28		#size-cells = <1>;
29		ranges;
30
31		clkgate: clkgate@800a0048 {
32			#address-cells = <1>;
33			#size-cells = <0>;
34			reg = <0x800a0048 4>;
35			compatible = "picochip,pc3x3-clk-gate";
36
37			tzprot_clk: clock@0 {
38				compatible = "picochip,pc3x3-gated-clk";
39				clock-outputs = "bus";
40				picochip,clk-disable-bit = <0>;
41				clock-frequency = <200000000>;
42				ref-clock = <&ref_clk>, "ref";
43			};
44
45			spi_clk: clock@1 {
46				compatible = "picochip,pc3x3-gated-clk";
47				clock-outputs = "bus";
48				picochip,clk-disable-bit = <1>;
49				clock-frequency = <200000000>;
50				ref-clock = <&ref_clk>, "ref";
51			};
52
53			dmac0_clk: clock@2 {
54				compatible = "picochip,pc3x3-gated-clk";
55				clock-outputs = "bus";
56				picochip,clk-disable-bit = <2>;
57				clock-frequency = <200000000>;
58				ref-clock = <&ref_clk>, "ref";
59			};
60
61			dmac1_clk: clock@3 {
62				compatible = "picochip,pc3x3-gated-clk";
63				clock-outputs = "bus";
64				picochip,clk-disable-bit = <3>;
65				clock-frequency = <200000000>;
66				ref-clock = <&ref_clk>, "ref";
67			};
68
69			ebi_clk: clock@4 {
70				compatible = "picochip,pc3x3-gated-clk";
71				clock-outputs = "bus";
72				picochip,clk-disable-bit = <4>;
73				clock-frequency = <200000000>;
74				ref-clock = <&ref_clk>, "ref";
75			};
76
77			ipsec_clk: clock@5 {
78				compatible = "picochip,pc3x3-gated-clk";
79				clock-outputs = "bus";
80				picochip,clk-disable-bit = <5>;
81				clock-frequency = <200000000>;
82				ref-clock = <&ref_clk>, "ref";
83			};
84
85			l2_clk: clock@6 {
86				compatible = "picochip,pc3x3-gated-clk";
87				clock-outputs = "bus";
88				picochip,clk-disable-bit = <6>;
89				clock-frequency = <200000000>;
90				ref-clock = <&ref_clk>, "ref";
91			};
92
93			trng_clk: clock@7 {
94				compatible = "picochip,pc3x3-gated-clk";
95				clock-outputs = "bus";
96				picochip,clk-disable-bit = <7>;
97				clock-frequency = <200000000>;
98				ref-clock = <&ref_clk>, "ref";
99			};
100
101			fuse_clk: clock@8 {
102				compatible = "picochip,pc3x3-gated-clk";
103				clock-outputs = "bus";
104				picochip,clk-disable-bit = <8>;
105				clock-frequency = <200000000>;
106				ref-clock = <&ref_clk>, "ref";
107			};
108
109			otp_clk: clock@9 {
110				compatible = "picochip,pc3x3-gated-clk";
111				clock-outputs = "bus";
112				picochip,clk-disable-bit = <9>;
113				clock-frequency = <200000000>;
114				ref-clock = <&ref_clk>, "ref";
115			};
116		};
117
118		arm_clk: clock@11 {
119			compatible = "picochip,pc3x3-pll";
120			reg = <0x800a0050 0x8>;
121			picochip,min-freq = <140000000>;
122			picochip,max-freq = <700000000>;
123			ref-clock = <&ref_clk>, "ref";
124			clock-outputs = "cpu";
125		};
126
127		pclk: clock@12 {
128			compatible = "fixed-clock";
129			clock-outputs = "bus", "pclk";
130			clock-frequency = <200000000>;
131			ref-clock = <&ref_clk>, "ref";
132		};
133	};
134
135	paxi {
136		compatible = "simple-bus";
137		#address-cells = <1>;
138		#size-cells = <1>;
139		ranges = <0 0x80000000 0x400000>;
140
141		emac: gem@30000 {
142			compatible = "cadence,gem";
143			reg = <0x30000 0x10000>;
144			interrupt-parent = <&vic0>;
145			interrupts = <31>;
146		};
147
148		dmac1: dmac@40000 {
149			compatible = "snps,dw-dmac";
150			reg = <0x40000 0x10000>;
151			interrupt-parent = <&vic0>;
152			interrupts = <25>;
153		};
154
155		dmac2: dmac@50000 {
156			compatible = "snps,dw-dmac";
157			reg = <0x50000 0x10000>;
158			interrupt-parent = <&vic0>;
159			interrupts = <26>;
160		};
161
162		vic0: interrupt-controller@60000 {
163			compatible = "arm,pl192-vic";
164			interrupt-controller;
165			reg = <0x60000 0x1000>;
166			#interrupt-cells = <1>;
167		};
168
169		vic1: interrupt-controller@64000 {
170			compatible = "arm,pl192-vic";
171			interrupt-controller;
172			reg = <0x64000 0x1000>;
173			#interrupt-cells = <1>;
174		};
175
176		fuse: picoxcell-fuse@80000 {
177			compatible = "picoxcell,fuse-pc3x3";
178			reg = <0x80000 0x10000>;
179		};
180
181		ssi: picoxcell-spi@90000 {
182			compatible = "picoxcell,spi";
183			reg = <0x90000 0x10000>;
184			interrupt-parent = <&vic0>;
185			interrupts = <10>;
186		};
187
188		ipsec: spacc@100000 {
189			compatible = "picochip,spacc-ipsec";
190			reg = <0x100000 0x10000>;
191			interrupt-parent = <&vic0>;
192			interrupts = <24>;
193			ref-clock = <&ipsec_clk>, "ref";
194		};
195
196		srtp: spacc@140000 {
197			compatible = "picochip,spacc-srtp";
198			reg = <0x140000 0x10000>;
199			interrupt-parent = <&vic0>;
200			interrupts = <23>;
201		};
202
203		l2_engine: spacc@180000 {
204			compatible = "picochip,spacc-l2";
205			reg = <0x180000 0x10000>;
206			interrupt-parent = <&vic0>;
207			interrupts = <22>;
208			ref-clock = <&l2_clk>, "ref";
209		};
210
211		apb {
212			compatible = "simple-bus";
213			#address-cells = <1>;
214			#size-cells = <1>;
215			ranges = <0 0x200000 0x80000>;
216
217			rtc0: rtc@0 {
218				compatible = "picochip,pc3x2-rtc";
219				clock-freq = <200000000>;
220				reg = <0x00000 0xf>;
221				interrupt-parent = <&vic0>;
222				interrupts = <8>;
223			};
224
225			timer0: timer@10000 {
226				compatible = "picochip,pc3x2-timer";
227				interrupt-parent = <&vic0>;
228				interrupts = <4>;
229				clock-freq = <200000000>;
230				reg = <0x10000 0x14>;
231			};
232
233			timer1: timer@10014 {
234				compatible = "picochip,pc3x2-timer";
235				interrupt-parent = <&vic0>;
236				interrupts = <5>;
237				clock-freq = <200000000>;
238				reg = <0x10014 0x14>;
239			};
240
241			gpio: gpio@20000 {
242				compatible = "snps,dw-apb-gpio";
243				reg = <0x20000 0x1000>;
244				#address-cells = <1>;
245				#size-cells = <0>;
246
247				banka: gpio-controller@0 {
248					compatible = "snps,dw-apb-gpio-bank";
249					gpio-controller;
250					#gpio-cells = <2>;
251					gpio-generic,nr-gpio = <8>;
252
253					regoffset-dat = <0x50>;
254					regoffset-set = <0x00>;
255					regoffset-dirout = <0x04>;
256				};
257
258				bankb: gpio-controller@1 {
259					compatible = "snps,dw-apb-gpio-bank";
260					gpio-controller;
261					#gpio-cells = <2>;
262					gpio-generic,nr-gpio = <16>;
263
264					regoffset-dat = <0x54>;
265					regoffset-set = <0x0c>;
266					regoffset-dirout = <0x10>;
267				};
268
269				bankd: gpio-controller@2 {
270					compatible = "snps,dw-apb-gpio-bank";
271					gpio-controller;
272					#gpio-cells = <2>;
273					gpio-generic,nr-gpio = <30>;
274
275					regoffset-dat = <0x5c>;
276					regoffset-set = <0x24>;
277					regoffset-dirout = <0x28>;
278				};
279			};
280
281			uart0: uart@30000 {
282				compatible = "snps,dw-apb-uart";
283				reg = <0x30000 0x1000>;
284				interrupt-parent = <&vic1>;
285				interrupts = <10>;
286				clock-frequency = <3686400>;
287				reg-shift = <2>;
288				reg-io-width = <4>;
289			};
290
291			uart1: uart@40000 {
292				compatible = "snps,dw-apb-uart";
293				reg = <0x40000 0x1000>;
294				interrupt-parent = <&vic1>;
295				interrupts = <9>;
296				clock-frequency = <3686400>;
297				reg-shift = <2>;
298				reg-io-width = <4>;
299			};
300
301			wdog: watchdog@50000 {
302				compatible = "snps,dw-apb-wdg";
303				reg = <0x50000 0x10000>;
304				interrupt-parent = <&vic0>;
305				interrupts = <11>;
306				bus-clock = <&pclk>, "bus";
307			};
308
309			timer2: timer@60000 {
310				compatible = "picochip,pc3x2-timer";
311				interrupt-parent = <&vic0>;
312				interrupts = <6>;
313				clock-freq = <200000000>;
314				reg = <0x60000 0x14>;
315			};
316
317			timer3: timer@60014 {
318				compatible = "picochip,pc3x2-timer";
319				interrupt-parent = <&vic0>;
320				interrupts = <7>;
321				clock-freq = <200000000>;
322				reg = <0x60014 0x14>;
323			};
324		};
325	};
326
327	rwid-axi {
328		#address-cells = <1>;
329		#size-cells = <1>;
330		compatible = "simple-bus";
331		ranges;
332
333		ebi@50000000 {
334			compatible = "simple-bus";
335			#address-cells = <2>;
336			#size-cells = <1>;
337			ranges = <0 0 0x40000000 0x08000000
338				  1 0 0x48000000 0x08000000
339				  2 0 0x50000000 0x08000000
340				  3 0 0x58000000 0x08000000>;
341		};
342
343		axi2pico@c0000000 {
344			compatible = "picochip,axi2pico-pc3x3";
345			reg = <0xc0000000 0x10000>;
346			interrupt-parent = <&vic0>;
347			interrupts = <13 14 15 16 17 18 19 20 21>;
348		};
349
350		otp@ffff8000 {
351			compatible = "picochip,otp-pc3x3";
352			reg = <0xffff8000 0x8000>;
353		};
354	};
355};
356