1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/mfd/qcom-rpm.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8960"; 13 compatible = "qcom,msm8960"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 interrupts = <1 14 0x304>; 20 21 cpu@0 { 22 compatible = "qcom,krait"; 23 enable-method = "qcom,kpss-acc-v1"; 24 device_type = "cpu"; 25 reg = <0>; 26 next-level-cache = <&L2>; 27 qcom,acc = <&acc0>; 28 qcom,saw = <&saw0>; 29 }; 30 31 cpu@1 { 32 compatible = "qcom,krait"; 33 enable-method = "qcom,kpss-acc-v1"; 34 device_type = "cpu"; 35 reg = <1>; 36 next-level-cache = <&L2>; 37 qcom,acc = <&acc1>; 38 qcom,saw = <&saw1>; 39 }; 40 41 L2: l2-cache { 42 compatible = "cache"; 43 cache-level = <2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x0 0x0>; 50 }; 51 52 cpu-pmu { 53 compatible = "qcom,krait-pmu"; 54 interrupts = <1 10 0x304>; 55 qcom,no-pc-write; 56 }; 57 58 clocks { 59 cxo_board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <19200000>; 63 clock-output-names = "cxo_board"; 64 }; 65 66 pxo_board { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "pxo_board"; 71 }; 72 73 sleep_clk { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <32768>; 77 clock-output-names = "sleep_clk"; 78 }; 79 }; 80 81 soc: soc { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 compatible = "simple-bus"; 86 87 intc: interrupt-controller@2000000 { 88 compatible = "qcom,msm-qgic2"; 89 interrupt-controller; 90 #interrupt-cells = <3>; 91 reg = <0x02000000 0x1000>, 92 <0x02002000 0x1000>; 93 }; 94 95 timer@200a000 { 96 compatible = "qcom,kpss-timer", 97 "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; 98 interrupts = <1 1 0x301>, 99 <1 2 0x301>, 100 <1 3 0x301>; 101 reg = <0x0200a000 0x100>; 102 clock-frequency = <27000000>, 103 <32768>; 104 cpu-offset = <0x80000>; 105 }; 106 107 msmgpio: pinctrl@800000 { 108 compatible = "qcom,msm8960-pinctrl"; 109 gpio-controller; 110 gpio-ranges = <&msmgpio 0 0 152>; 111 #gpio-cells = <2>; 112 interrupts = <0 16 0x4>; 113 interrupt-controller; 114 #interrupt-cells = <2>; 115 reg = <0x800000 0x4000>; 116 }; 117 118 gcc: clock-controller@900000 { 119 compatible = "qcom,gcc-msm8960"; 120 #clock-cells = <1>; 121 #reset-cells = <1>; 122 reg = <0x900000 0x4000>; 123 }; 124 125 lcc: clock-controller@28000000 { 126 compatible = "qcom,lcc-msm8960"; 127 reg = <0x28000000 0x1000>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 clock-controller@4000000 { 133 compatible = "qcom,mmcc-msm8960"; 134 reg = <0x4000000 0x1000>; 135 #clock-cells = <1>; 136 #reset-cells = <1>; 137 }; 138 139 l2cc: clock-controller@2011000 { 140 compatible = "syscon"; 141 reg = <0x2011000 0x1000>; 142 }; 143 144 rpm@108000 { 145 compatible = "qcom,rpm-msm8960"; 146 reg = <0x108000 0x1000>; 147 qcom,ipc = <&l2cc 0x8 2>; 148 149 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 150 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 151 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 152 interrupt-names = "ack", "err", "wakeup"; 153 154 regulators { 155 compatible = "qcom,rpm-pm8921-regulators"; 156 }; 157 }; 158 159 acc0: clock-controller@2088000 { 160 compatible = "qcom,kpss-acc-v1"; 161 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 162 }; 163 164 acc1: clock-controller@2098000 { 165 compatible = "qcom,kpss-acc-v1"; 166 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 167 }; 168 169 saw0: regulator@2089000 { 170 compatible = "qcom,saw2"; 171 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 172 regulator; 173 }; 174 175 saw1: regulator@2099000 { 176 compatible = "qcom,saw2"; 177 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 178 regulator; 179 }; 180 181 gsbi5: gsbi@16400000 { 182 compatible = "qcom,gsbi-v1.0.0"; 183 cell-index = <5>; 184 reg = <0x16400000 0x100>; 185 clocks = <&gcc GSBI5_H_CLK>; 186 clock-names = "iface"; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 ranges; 190 191 syscon-tcsr = <&tcsr>; 192 193 gsbi5_serial: serial@16440000 { 194 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 195 reg = <0x16440000 0x1000>, 196 <0x16400000 0x1000>; 197 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 199 clock-names = "core", "iface"; 200 status = "disabled"; 201 }; 202 }; 203 204 qcom,ssbi@500000 { 205 compatible = "qcom,ssbi"; 206 reg = <0x500000 0x1000>; 207 qcom,controller-type = "pmic-arbiter"; 208 209 pmicintc: pmic@0 { 210 compatible = "qcom,pm8921"; 211 interrupt-parent = <&msmgpio>; 212 interrupts = <104 8>; 213 #interrupt-cells = <2>; 214 interrupt-controller; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 218 pwrkey@1c { 219 compatible = "qcom,pm8921-pwrkey"; 220 reg = <0x1c>; 221 interrupt-parent = <&pmicintc>; 222 interrupts = <50 1>, <51 1>; 223 debounce = <15625>; 224 pull-up; 225 }; 226 227 keypad@148 { 228 compatible = "qcom,pm8921-keypad"; 229 reg = <0x148>; 230 interrupt-parent = <&pmicintc>; 231 interrupts = <74 1>, <75 1>; 232 debounce = <15>; 233 scan-delay = <32>; 234 row-hold = <91500>; 235 }; 236 237 rtc@11d { 238 compatible = "qcom,pm8921-rtc"; 239 interrupt-parent = <&pmicintc>; 240 interrupts = <39 1>; 241 reg = <0x11d>; 242 allow-set-time; 243 }; 244 }; 245 }; 246 247 rng@1a500000 { 248 compatible = "qcom,prng"; 249 reg = <0x1a500000 0x200>; 250 clocks = <&gcc PRNG_CLK>; 251 clock-names = "core"; 252 }; 253 254 /* Temporary fixed regulator */ 255 vsdcc_fixed: vsdcc-regulator { 256 compatible = "regulator-fixed"; 257 regulator-name = "SDCC Power"; 258 regulator-min-microvolt = <2700000>; 259 regulator-max-microvolt = <2700000>; 260 regulator-always-on; 261 }; 262 263 amba { 264 compatible = "simple-bus"; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 sdcc1: sdcc@12400000 { 269 status = "disabled"; 270 compatible = "arm,pl18x", "arm,primecell"; 271 arm,primecell-periphid = <0x00051180>; 272 reg = <0x12400000 0x8000>; 273 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 274 interrupt-names = "cmd_irq"; 275 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 276 clock-names = "mclk", "apb_pclk"; 277 bus-width = <8>; 278 max-frequency = <96000000>; 279 non-removable; 280 cap-sd-highspeed; 281 cap-mmc-highspeed; 282 vmmc-supply = <&vsdcc_fixed>; 283 }; 284 285 sdcc3: sdcc@12180000 { 286 compatible = "arm,pl18x", "arm,primecell"; 287 arm,primecell-periphid = <0x00051180>; 288 status = "disabled"; 289 reg = <0x12180000 0x8000>; 290 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-names = "cmd_irq"; 292 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 293 clock-names = "mclk", "apb_pclk"; 294 bus-width = <4>; 295 cap-sd-highspeed; 296 cap-mmc-highspeed; 297 max-frequency = <192000000>; 298 no-1-8-v; 299 vmmc-supply = <&vsdcc_fixed>; 300 }; 301 }; 302 303 tcsr: syscon@1a400000 { 304 compatible = "qcom,tcsr-msm8960", "syscon"; 305 reg = <0x1a400000 0x100>; 306 }; 307 308 gsbi@16000000 { 309 compatible = "qcom,gsbi-v1.0.0"; 310 cell-index = <1>; 311 reg = <0x16000000 0x100>; 312 clocks = <&gcc GSBI1_H_CLK>; 313 clock-names = "iface"; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 ranges; 317 318 spi@16080000 { 319 compatible = "qcom,spi-qup-v1.1.1"; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 reg = <0x16080000 0x1000>; 323 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 324 spi-max-frequency = <24000000>; 325 cs-gpios = <&msmgpio 8 0>; 326 327 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 328 clock-names = "core", "iface"; 329 status = "disabled"; 330 }; 331 }; 332 }; 333}; 334