1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11/ { 12 compatible = "nvidia,tegra124"; 13 interrupt-parent = <&lic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x0 0x80000000 0x0 0x0>; 20 }; 21 22 pcie@1003000 { 23 compatible = "nvidia,tegra124-pcie"; 24 device_type = "pci"; 25 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 26 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 27 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 28 reg-names = "pads", "afi", "cs"; 29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 31 interrupt-names = "intr", "msi"; 32 33 #interrupt-cells = <1>; 34 interrupt-map-mask = <0 0 0 0>; 35 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 36 37 bus-range = <0x00 0xff>; 38 #address-cells = <3>; 39 #size-cells = <2>; 40 41 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 42 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 43 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 44 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 45 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 46 47 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 48 <&tegra_car TEGRA124_CLK_AFI>, 49 <&tegra_car TEGRA124_CLK_PLL_E>, 50 <&tegra_car TEGRA124_CLK_CML0>; 51 clock-names = "pex", "afi", "pll_e", "cml"; 52 resets = <&tegra_car 70>, 53 <&tegra_car 72>, 54 <&tegra_car 74>; 55 reset-names = "pex", "afi", "pcie_x"; 56 status = "disabled"; 57 58 pci@1,0 { 59 device_type = "pci"; 60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 61 reg = <0x000800 0 0 0 0>; 62 bus-range = <0x00 0xff>; 63 status = "disabled"; 64 65 #address-cells = <3>; 66 #size-cells = <2>; 67 ranges; 68 69 nvidia,num-lanes = <2>; 70 }; 71 72 pci@2,0 { 73 device_type = "pci"; 74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 75 reg = <0x001000 0 0 0 0>; 76 bus-range = <0x00 0xff>; 77 status = "disabled"; 78 79 #address-cells = <3>; 80 #size-cells = <2>; 81 ranges; 82 83 nvidia,num-lanes = <1>; 84 }; 85 }; 86 87 host1x@50000000 { 88 compatible = "nvidia,tegra124-host1x"; 89 reg = <0x0 0x50000000 0x0 0x00034000>; 90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 92 interrupt-names = "syncpt", "host1x"; 93 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 94 clock-names = "host1x"; 95 resets = <&tegra_car 28>; 96 reset-names = "host1x"; 97 iommus = <&mc TEGRA_SWGROUP_HC>; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 103 104 dc@54200000 { 105 compatible = "nvidia,tegra124-dc"; 106 reg = <0x0 0x54200000 0x0 0x00040000>; 107 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 109 clock-names = "dc"; 110 resets = <&tegra_car 27>; 111 reset-names = "dc"; 112 113 iommus = <&mc TEGRA_SWGROUP_DC>; 114 115 nvidia,head = <0>; 116 }; 117 118 dc@54240000 { 119 compatible = "nvidia,tegra124-dc"; 120 reg = <0x0 0x54240000 0x0 0x00040000>; 121 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 123 clock-names = "dc"; 124 resets = <&tegra_car 26>; 125 reset-names = "dc"; 126 127 iommus = <&mc TEGRA_SWGROUP_DCB>; 128 129 nvidia,head = <1>; 130 }; 131 132 hdmi: hdmi@54280000 { 133 compatible = "nvidia,tegra124-hdmi"; 134 reg = <0x0 0x54280000 0x0 0x00040000>; 135 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 137 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 138 clock-names = "hdmi", "parent"; 139 resets = <&tegra_car 51>; 140 reset-names = "hdmi"; 141 status = "disabled"; 142 }; 143 144 vic@54340000 { 145 compatible = "nvidia,tegra124-vic"; 146 reg = <0x0 0x54340000 0x0 0x00040000>; 147 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&tegra_car TEGRA124_CLK_VIC03>; 149 clock-names = "vic"; 150 resets = <&tegra_car 178>; 151 reset-names = "vic"; 152 153 iommus = <&mc TEGRA_SWGROUP_VIC>; 154 }; 155 156 sor@54540000 { 157 compatible = "nvidia,tegra124-sor"; 158 reg = <0x0 0x54540000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 161 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 162 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 163 <&tegra_car TEGRA124_CLK_PLL_DP>, 164 <&tegra_car TEGRA124_CLK_CLK_M>; 165 clock-names = "sor", "out", "parent", "dp", "safe"; 166 resets = <&tegra_car 182>; 167 reset-names = "sor"; 168 status = "disabled"; 169 }; 170 171 dpaux: dpaux@545c0000 { 172 compatible = "nvidia,tegra124-dpaux"; 173 reg = <0x0 0x545c0000 0x0 0x00040000>; 174 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 176 <&tegra_car TEGRA124_CLK_PLL_DP>; 177 clock-names = "dpaux", "parent"; 178 resets = <&tegra_car 181>; 179 reset-names = "dpaux"; 180 status = "disabled"; 181 182 i2c-bus { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 }; 186 }; 187 }; 188 189 gic: interrupt-controller@50041000 { 190 compatible = "arm,cortex-a15-gic"; 191 #interrupt-cells = <3>; 192 interrupt-controller; 193 reg = <0x0 0x50041000 0x0 0x1000>, 194 <0x0 0x50042000 0x0 0x1000>, 195 <0x0 0x50044000 0x0 0x2000>, 196 <0x0 0x50046000 0x0 0x2000>; 197 interrupts = <GIC_PPI 9 198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 199 interrupt-parent = <&gic>; 200 }; 201 202 /* 203 * Please keep the following 0, notation in place as a former mainline 204 * U-Boot version was looking for that particular notation in order to 205 * perform required fix-ups on that GPU node. 206 */ 207 gpu@0,57000000 { 208 compatible = "nvidia,gk20a"; 209 reg = <0x0 0x57000000 0x0 0x01000000>, 210 <0x0 0x58000000 0x0 0x01000000>; 211 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "stall", "nonstall"; 214 clocks = <&tegra_car TEGRA124_CLK_GPU>, 215 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 216 clock-names = "gpu", "pwr"; 217 resets = <&tegra_car 184>; 218 reset-names = "gpu"; 219 220 iommus = <&mc TEGRA_SWGROUP_GPU>; 221 222 status = "disabled"; 223 }; 224 225 lic: interrupt-controller@60004000 { 226 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 227 reg = <0x0 0x60004000 0x0 0x100>, 228 <0x0 0x60004100 0x0 0x100>, 229 <0x0 0x60004200 0x0 0x100>, 230 <0x0 0x60004300 0x0 0x100>, 231 <0x0 0x60004400 0x0 0x100>; 232 interrupt-controller; 233 #interrupt-cells = <3>; 234 interrupt-parent = <&gic>; 235 }; 236 237 timer@60005000 { 238 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 239 reg = <0x0 0x60005000 0x0 0x400>; 240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 247 }; 248 249 tegra_car: clock@60006000 { 250 compatible = "nvidia,tegra124-car"; 251 reg = <0x0 0x60006000 0x0 0x1000>; 252 #clock-cells = <1>; 253 #reset-cells = <1>; 254 nvidia,external-memory-controller = <&emc>; 255 }; 256 257 flow-controller@60007000 { 258 compatible = "nvidia,tegra124-flowctrl"; 259 reg = <0x0 0x60007000 0x0 0x1000>; 260 }; 261 262 actmon@6000c800 { 263 compatible = "nvidia,tegra124-actmon"; 264 reg = <0x0 0x6000c800 0x0 0x400>; 265 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 267 <&tegra_car TEGRA124_CLK_EMC>; 268 clock-names = "actmon", "emc"; 269 resets = <&tegra_car 119>; 270 reset-names = "actmon"; 271 }; 272 273 gpio: gpio@6000d000 { 274 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 275 reg = <0x0 0x6000d000 0x0 0x1000>; 276 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 284 #gpio-cells = <2>; 285 gpio-controller; 286 #interrupt-cells = <2>; 287 interrupt-controller; 288 /* 289 gpio-ranges = <&pinmux 0 0 251>; 290 */ 291 }; 292 293 apbdma: dma@60020000 { 294 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 295 reg = <0x0 0x60020000 0x0 0x1400>; 296 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 329 resets = <&tegra_car 34>; 330 reset-names = "dma"; 331 #dma-cells = <1>; 332 }; 333 334 apbmisc@70000800 { 335 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 336 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 337 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 338 }; 339 340 pinmux: pinmux@70000868 { 341 compatible = "nvidia,tegra124-pinmux"; 342 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 343 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 344 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 345 }; 346 347 /* 348 * There are two serial driver i.e. 8250 based simple serial 349 * driver and APB DMA based serial driver for higher baudrate 350 * and performace. To enable the 8250 based driver, the compatible 351 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 352 * the APB DMA based serial driver, the compatible is 353 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 354 */ 355 uarta: serial@70006000 { 356 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 357 reg = <0x0 0x70006000 0x0 0x40>; 358 reg-shift = <2>; 359 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 361 resets = <&tegra_car 6>; 362 reset-names = "serial"; 363 dmas = <&apbdma 8>, <&apbdma 8>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 uartb: serial@70006040 { 369 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 370 reg = <0x0 0x70006040 0x0 0x40>; 371 reg-shift = <2>; 372 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 374 resets = <&tegra_car 7>; 375 reset-names = "serial"; 376 dmas = <&apbdma 9>, <&apbdma 9>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 uartc: serial@70006200 { 382 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 383 reg = <0x0 0x70006200 0x0 0x40>; 384 reg-shift = <2>; 385 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 387 resets = <&tegra_car 55>; 388 reset-names = "serial"; 389 dmas = <&apbdma 10>, <&apbdma 10>; 390 dma-names = "rx", "tx"; 391 status = "disabled"; 392 }; 393 394 uartd: serial@70006300 { 395 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 396 reg = <0x0 0x70006300 0x0 0x40>; 397 reg-shift = <2>; 398 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 400 resets = <&tegra_car 65>; 401 reset-names = "serial"; 402 dmas = <&apbdma 19>, <&apbdma 19>; 403 dma-names = "rx", "tx"; 404 status = "disabled"; 405 }; 406 407 pwm: pwm@7000a000 { 408 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 409 reg = <0x0 0x7000a000 0x0 0x100>; 410 #pwm-cells = <2>; 411 clocks = <&tegra_car TEGRA124_CLK_PWM>; 412 resets = <&tegra_car 17>; 413 reset-names = "pwm"; 414 status = "disabled"; 415 }; 416 417 i2c@7000c000 { 418 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 419 reg = <0x0 0x7000c000 0x0 0x100>; 420 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 424 clock-names = "div-clk"; 425 resets = <&tegra_car 12>; 426 reset-names = "i2c"; 427 dmas = <&apbdma 21>, <&apbdma 21>; 428 dma-names = "rx", "tx"; 429 status = "disabled"; 430 }; 431 432 i2c@7000c400 { 433 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 434 reg = <0x0 0x7000c400 0x0 0x100>; 435 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 439 clock-names = "div-clk"; 440 resets = <&tegra_car 54>; 441 reset-names = "i2c"; 442 dmas = <&apbdma 22>, <&apbdma 22>; 443 dma-names = "rx", "tx"; 444 status = "disabled"; 445 }; 446 447 i2c@7000c500 { 448 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 449 reg = <0x0 0x7000c500 0x0 0x100>; 450 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 454 clock-names = "div-clk"; 455 resets = <&tegra_car 67>; 456 reset-names = "i2c"; 457 dmas = <&apbdma 23>, <&apbdma 23>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 i2c@7000c700 { 463 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 464 reg = <0x0 0x7000c700 0x0 0x100>; 465 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 469 clock-names = "div-clk"; 470 resets = <&tegra_car 103>; 471 reset-names = "i2c"; 472 dmas = <&apbdma 26>, <&apbdma 26>; 473 dma-names = "rx", "tx"; 474 status = "disabled"; 475 }; 476 477 i2c@7000d000 { 478 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 479 reg = <0x0 0x7000d000 0x0 0x100>; 480 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 484 clock-names = "div-clk"; 485 resets = <&tegra_car 47>; 486 reset-names = "i2c"; 487 dmas = <&apbdma 24>, <&apbdma 24>; 488 dma-names = "rx", "tx"; 489 status = "disabled"; 490 }; 491 492 i2c@7000d100 { 493 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 494 reg = <0x0 0x7000d100 0x0 0x100>; 495 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 499 clock-names = "div-clk"; 500 resets = <&tegra_car 166>; 501 reset-names = "i2c"; 502 dmas = <&apbdma 30>, <&apbdma 30>; 503 dma-names = "rx", "tx"; 504 status = "disabled"; 505 }; 506 507 spi@7000d400 { 508 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 509 reg = <0x0 0x7000d400 0x0 0x200>; 510 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 514 clock-names = "spi"; 515 resets = <&tegra_car 41>; 516 reset-names = "spi"; 517 dmas = <&apbdma 15>, <&apbdma 15>; 518 dma-names = "rx", "tx"; 519 status = "disabled"; 520 }; 521 522 spi@7000d600 { 523 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 524 reg = <0x0 0x7000d600 0x0 0x200>; 525 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 529 clock-names = "spi"; 530 resets = <&tegra_car 44>; 531 reset-names = "spi"; 532 dmas = <&apbdma 16>, <&apbdma 16>; 533 dma-names = "rx", "tx"; 534 status = "disabled"; 535 }; 536 537 spi@7000d800 { 538 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 539 reg = <0x0 0x7000d800 0x0 0x200>; 540 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 544 clock-names = "spi"; 545 resets = <&tegra_car 46>; 546 reset-names = "spi"; 547 dmas = <&apbdma 17>, <&apbdma 17>; 548 dma-names = "rx", "tx"; 549 status = "disabled"; 550 }; 551 552 spi@7000da00 { 553 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 554 reg = <0x0 0x7000da00 0x0 0x200>; 555 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 559 clock-names = "spi"; 560 resets = <&tegra_car 68>; 561 reset-names = "spi"; 562 dmas = <&apbdma 18>, <&apbdma 18>; 563 dma-names = "rx", "tx"; 564 status = "disabled"; 565 }; 566 567 spi@7000dc00 { 568 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 569 reg = <0x0 0x7000dc00 0x0 0x200>; 570 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 574 clock-names = "spi"; 575 resets = <&tegra_car 104>; 576 reset-names = "spi"; 577 dmas = <&apbdma 27>, <&apbdma 27>; 578 dma-names = "rx", "tx"; 579 status = "disabled"; 580 }; 581 582 spi@7000de00 { 583 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 584 reg = <0x0 0x7000de00 0x0 0x200>; 585 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 589 clock-names = "spi"; 590 resets = <&tegra_car 105>; 591 reset-names = "spi"; 592 dmas = <&apbdma 28>, <&apbdma 28>; 593 dma-names = "rx", "tx"; 594 status = "disabled"; 595 }; 596 597 rtc@7000e000 { 598 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 599 reg = <0x0 0x7000e000 0x0 0x100>; 600 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&tegra_car TEGRA124_CLK_RTC>; 602 }; 603 604 tegra_pmc: pmc@7000e400 { 605 compatible = "nvidia,tegra124-pmc"; 606 reg = <0x0 0x7000e400 0x0 0x400>; 607 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 608 clock-names = "pclk", "clk32k_in"; 609 #clock-cells = <1>; 610 }; 611 612 fuse@7000f800 { 613 compatible = "nvidia,tegra124-efuse"; 614 reg = <0x0 0x7000f800 0x0 0x400>; 615 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 616 clock-names = "fuse"; 617 resets = <&tegra_car 39>; 618 reset-names = "fuse"; 619 }; 620 621 mc: memory-controller@70019000 { 622 compatible = "nvidia,tegra124-mc"; 623 reg = <0x0 0x70019000 0x0 0x1000>; 624 clocks = <&tegra_car TEGRA124_CLK_MC>; 625 clock-names = "mc"; 626 627 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 628 629 #iommu-cells = <1>; 630 #reset-cells = <1>; 631 }; 632 633 emc: external-memory-controller@7001b000 { 634 compatible = "nvidia,tegra124-emc"; 635 reg = <0x0 0x7001b000 0x0 0x1000>; 636 clocks = <&tegra_car TEGRA124_CLK_EMC>; 637 clock-names = "emc"; 638 639 nvidia,memory-controller = <&mc>; 640 }; 641 642 sata@70020000 { 643 compatible = "nvidia,tegra124-ahci"; 644 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 645 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 646 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&tegra_car TEGRA124_CLK_SATA>, 648 <&tegra_car TEGRA124_CLK_SATA_OOB>, 649 <&tegra_car TEGRA124_CLK_CML1>, 650 <&tegra_car TEGRA124_CLK_PLL_E>; 651 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 652 resets = <&tegra_car 124>, 653 <&tegra_car 123>, 654 <&tegra_car 129>; 655 reset-names = "sata", "sata-oob", "sata-cold"; 656 status = "disabled"; 657 }; 658 659 hda@70030000 { 660 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 661 reg = <0x0 0x70030000 0x0 0x10000>; 662 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&tegra_car TEGRA124_CLK_HDA>, 664 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 665 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 666 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 667 resets = <&tegra_car 125>, /* hda */ 668 <&tegra_car 128>, /* hda2hdmi */ 669 <&tegra_car 111>; /* hda2codec_2x */ 670 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 671 status = "disabled"; 672 }; 673 674 usb@70090000 { 675 compatible = "nvidia,tegra124-xusb"; 676 reg = <0x0 0x70090000 0x0 0x8000>, 677 <0x0 0x70098000 0x0 0x1000>, 678 <0x0 0x70099000 0x0 0x1000>; 679 reg-names = "hcd", "fpci", "ipfs"; 680 681 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 683 684 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 685 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 686 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 687 <&tegra_car TEGRA124_CLK_XUSB_SS>, 688 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 689 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 690 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 691 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 692 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 693 <&tegra_car TEGRA124_CLK_CLK_M>, 694 <&tegra_car TEGRA124_CLK_PLL_E>; 695 clock-names = "xusb_host", "xusb_host_src", 696 "xusb_falcon_src", "xusb_ss", 697 "xusb_ss_src", "xusb_ss_div2", 698 "xusb_hs_src", "xusb_fs_src", 699 "pll_u_480m", "clk_m", "pll_e"; 700 resets = <&tegra_car 89>, <&tegra_car 156>, 701 <&tegra_car 143>; 702 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 703 704 nvidia,xusb-padctl = <&padctl>; 705 706 status = "disabled"; 707 }; 708 709 padctl: padctl@7009f000 { 710 compatible = "nvidia,tegra124-xusb-padctl"; 711 reg = <0x0 0x7009f000 0x0 0x1000>; 712 resets = <&tegra_car 142>; 713 reset-names = "padctl"; 714 715 pads { 716 usb2 { 717 status = "disabled"; 718 719 lanes { 720 usb2-0 { 721 status = "disabled"; 722 #phy-cells = <0>; 723 }; 724 725 usb2-1 { 726 status = "disabled"; 727 #phy-cells = <0>; 728 }; 729 730 usb2-2 { 731 status = "disabled"; 732 #phy-cells = <0>; 733 }; 734 }; 735 }; 736 737 ulpi { 738 status = "disabled"; 739 740 lanes { 741 ulpi-0 { 742 status = "disabled"; 743 #phy-cells = <0>; 744 }; 745 }; 746 }; 747 748 hsic { 749 status = "disabled"; 750 751 lanes { 752 hsic-0 { 753 status = "disabled"; 754 #phy-cells = <0>; 755 }; 756 757 hsic-1 { 758 status = "disabled"; 759 #phy-cells = <0>; 760 }; 761 }; 762 }; 763 764 pcie { 765 status = "disabled"; 766 767 lanes { 768 pcie-0 { 769 status = "disabled"; 770 #phy-cells = <0>; 771 }; 772 773 pcie-1 { 774 status = "disabled"; 775 #phy-cells = <0>; 776 }; 777 778 pcie-2 { 779 status = "disabled"; 780 #phy-cells = <0>; 781 }; 782 783 pcie-3 { 784 status = "disabled"; 785 #phy-cells = <0>; 786 }; 787 788 pcie-4 { 789 status = "disabled"; 790 #phy-cells = <0>; 791 }; 792 }; 793 }; 794 795 sata { 796 status = "disabled"; 797 798 lanes { 799 sata-0 { 800 status = "disabled"; 801 #phy-cells = <0>; 802 }; 803 }; 804 }; 805 }; 806 807 ports { 808 usb2-0 { 809 status = "disabled"; 810 }; 811 812 usb2-1 { 813 status = "disabled"; 814 }; 815 816 usb2-2 { 817 status = "disabled"; 818 }; 819 820 ulpi-0 { 821 status = "disabled"; 822 }; 823 824 hsic-0 { 825 status = "disabled"; 826 }; 827 828 hsic-1 { 829 status = "disabled"; 830 }; 831 832 usb3-0 { 833 status = "disabled"; 834 }; 835 836 usb3-1 { 837 status = "disabled"; 838 }; 839 }; 840 }; 841 842 mmc@700b0000 { 843 compatible = "nvidia,tegra124-sdhci"; 844 reg = <0x0 0x700b0000 0x0 0x200>; 845 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 847 clock-names = "sdhci"; 848 resets = <&tegra_car 14>; 849 reset-names = "sdhci"; 850 status = "disabled"; 851 }; 852 853 mmc@700b0200 { 854 compatible = "nvidia,tegra124-sdhci"; 855 reg = <0x0 0x700b0200 0x0 0x200>; 856 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 858 clock-names = "sdhci"; 859 resets = <&tegra_car 9>; 860 reset-names = "sdhci"; 861 status = "disabled"; 862 }; 863 864 mmc@700b0400 { 865 compatible = "nvidia,tegra124-sdhci"; 866 reg = <0x0 0x700b0400 0x0 0x200>; 867 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 869 clock-names = "sdhci"; 870 resets = <&tegra_car 69>; 871 reset-names = "sdhci"; 872 status = "disabled"; 873 }; 874 875 mmc@700b0600 { 876 compatible = "nvidia,tegra124-sdhci"; 877 reg = <0x0 0x700b0600 0x0 0x200>; 878 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 880 clock-names = "sdhci"; 881 resets = <&tegra_car 15>; 882 reset-names = "sdhci"; 883 status = "disabled"; 884 }; 885 886 cec@70015000 { 887 compatible = "nvidia,tegra124-cec"; 888 reg = <0x0 0x70015000 0x0 0x00001000>; 889 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&tegra_car TEGRA124_CLK_CEC>; 891 clock-names = "cec"; 892 status = "disabled"; 893 hdmi-phandle = <&hdmi>; 894 }; 895 896 soctherm: thermal-sensor@700e2000 { 897 compatible = "nvidia,tegra124-soctherm"; 898 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 899 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 900 reg-names = "soctherm-reg", "car-reg"; 901 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 903 <&tegra_car TEGRA124_CLK_SOC_THERM>; 904 clock-names = "tsensor", "soctherm"; 905 resets = <&tegra_car 78>; 906 reset-names = "soctherm"; 907 #thermal-sensor-cells = <1>; 908 909 throttle-cfgs { 910 throttle_heavy: heavy { 911 nvidia,priority = <100>; 912 nvidia,cpu-throt-percent = <85>; 913 914 #cooling-cells = <2>; 915 }; 916 }; 917 }; 918 919 dfll: clock@70110000 { 920 compatible = "nvidia,tegra124-dfll"; 921 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 922 <0 0x70110000 0 0x100>, /* I2C output control */ 923 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 924 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 925 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 927 <&tegra_car TEGRA124_CLK_DFLL_REF>, 928 <&tegra_car TEGRA124_CLK_I2C5>; 929 clock-names = "soc", "ref", "i2c"; 930 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 931 reset-names = "dvco"; 932 #clock-cells = <0>; 933 clock-output-names = "dfllCPU_out"; 934 nvidia,sample-rate = <12500>; 935 nvidia,droop-ctrl = <0x00000f00>; 936 nvidia,force-mode = <1>; 937 nvidia,cf = <10>; 938 nvidia,ci = <0>; 939 nvidia,cg = <2>; 940 status = "disabled"; 941 }; 942 943 ahub@70300000 { 944 compatible = "nvidia,tegra124-ahub"; 945 reg = <0x0 0x70300000 0x0 0x200>, 946 <0x0 0x70300800 0x0 0x800>, 947 <0x0 0x70300200 0x0 0x600>; 948 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 950 <&tegra_car TEGRA124_CLK_APBIF>; 951 clock-names = "d_audio", "apbif"; 952 resets = <&tegra_car 106>, /* d_audio */ 953 <&tegra_car 107>, /* apbif */ 954 <&tegra_car 30>, /* i2s0 */ 955 <&tegra_car 11>, /* i2s1 */ 956 <&tegra_car 18>, /* i2s2 */ 957 <&tegra_car 101>, /* i2s3 */ 958 <&tegra_car 102>, /* i2s4 */ 959 <&tegra_car 108>, /* dam0 */ 960 <&tegra_car 109>, /* dam1 */ 961 <&tegra_car 110>, /* dam2 */ 962 <&tegra_car 10>, /* spdif */ 963 <&tegra_car 153>, /* amx */ 964 <&tegra_car 185>, /* amx1 */ 965 <&tegra_car 154>, /* adx */ 966 <&tegra_car 180>, /* adx1 */ 967 <&tegra_car 186>, /* afc0 */ 968 <&tegra_car 187>, /* afc1 */ 969 <&tegra_car 188>, /* afc2 */ 970 <&tegra_car 189>, /* afc3 */ 971 <&tegra_car 190>, /* afc4 */ 972 <&tegra_car 191>; /* afc5 */ 973 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 974 "i2s3", "i2s4", "dam0", "dam1", "dam2", 975 "spdif", "amx", "amx1", "adx", "adx1", 976 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 977 dmas = <&apbdma 1>, <&apbdma 1>, 978 <&apbdma 2>, <&apbdma 2>, 979 <&apbdma 3>, <&apbdma 3>, 980 <&apbdma 4>, <&apbdma 4>, 981 <&apbdma 6>, <&apbdma 6>, 982 <&apbdma 7>, <&apbdma 7>, 983 <&apbdma 12>, <&apbdma 12>, 984 <&apbdma 13>, <&apbdma 13>, 985 <&apbdma 14>, <&apbdma 14>, 986 <&apbdma 29>, <&apbdma 29>; 987 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 988 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 989 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 990 "rx9", "tx9"; 991 ranges; 992 #address-cells = <2>; 993 #size-cells = <2>; 994 995 tegra_i2s0: i2s@70301000 { 996 compatible = "nvidia,tegra124-i2s"; 997 reg = <0x0 0x70301000 0x0 0x100>; 998 nvidia,ahub-cif-ids = <4 4>; 999 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1000 resets = <&tegra_car 30>; 1001 reset-names = "i2s"; 1002 status = "disabled"; 1003 }; 1004 1005 tegra_i2s1: i2s@70301100 { 1006 compatible = "nvidia,tegra124-i2s"; 1007 reg = <0x0 0x70301100 0x0 0x100>; 1008 nvidia,ahub-cif-ids = <5 5>; 1009 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1010 resets = <&tegra_car 11>; 1011 reset-names = "i2s"; 1012 status = "disabled"; 1013 }; 1014 1015 tegra_i2s2: i2s@70301200 { 1016 compatible = "nvidia,tegra124-i2s"; 1017 reg = <0x0 0x70301200 0x0 0x100>; 1018 nvidia,ahub-cif-ids = <6 6>; 1019 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1020 resets = <&tegra_car 18>; 1021 reset-names = "i2s"; 1022 status = "disabled"; 1023 }; 1024 1025 tegra_i2s3: i2s@70301300 { 1026 compatible = "nvidia,tegra124-i2s"; 1027 reg = <0x0 0x70301300 0x0 0x100>; 1028 nvidia,ahub-cif-ids = <7 7>; 1029 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1030 resets = <&tegra_car 101>; 1031 reset-names = "i2s"; 1032 status = "disabled"; 1033 }; 1034 1035 tegra_i2s4: i2s@70301400 { 1036 compatible = "nvidia,tegra124-i2s"; 1037 reg = <0x0 0x70301400 0x0 0x100>; 1038 nvidia,ahub-cif-ids = <8 8>; 1039 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1040 resets = <&tegra_car 102>; 1041 reset-names = "i2s"; 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 usb@7d000000 { 1047 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1048 reg = <0x0 0x7d000000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1050 phy_type = "utmi"; 1051 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1052 resets = <&tegra_car 22>; 1053 reset-names = "usb"; 1054 nvidia,phy = <&phy1>; 1055 status = "disabled"; 1056 }; 1057 1058 phy1: usb-phy@7d000000 { 1059 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1060 reg = <0x0 0x7d000000 0x0 0x4000>, 1061 <0x0 0x7d000000 0x0 0x4000>; 1062 phy_type = "utmi"; 1063 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1064 <&tegra_car TEGRA124_CLK_PLL_U>, 1065 <&tegra_car TEGRA124_CLK_USBD>; 1066 clock-names = "reg", "pll_u", "utmi-pads"; 1067 resets = <&tegra_car 22>, <&tegra_car 22>; 1068 reset-names = "usb", "utmi-pads"; 1069 #phy-cells = <0>; 1070 nvidia,hssync-start-delay = <0>; 1071 nvidia,idle-wait-delay = <17>; 1072 nvidia,elastic-limit = <16>; 1073 nvidia,term-range-adj = <6>; 1074 nvidia,xcvr-setup = <9>; 1075 nvidia,xcvr-lsfslew = <0>; 1076 nvidia,xcvr-lsrslew = <3>; 1077 nvidia,hssquelch-level = <2>; 1078 nvidia,hsdiscon-level = <5>; 1079 nvidia,xcvr-hsslew = <12>; 1080 nvidia,has-utmi-pad-registers; 1081 status = "disabled"; 1082 }; 1083 1084 usb@7d004000 { 1085 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1086 reg = <0x0 0x7d004000 0x0 0x4000>; 1087 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1088 phy_type = "utmi"; 1089 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1090 resets = <&tegra_car 58>; 1091 reset-names = "usb"; 1092 nvidia,phy = <&phy2>; 1093 status = "disabled"; 1094 }; 1095 1096 phy2: usb-phy@7d004000 { 1097 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1098 reg = <0x0 0x7d004000 0x0 0x4000>, 1099 <0x0 0x7d000000 0x0 0x4000>; 1100 phy_type = "utmi"; 1101 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1102 <&tegra_car TEGRA124_CLK_PLL_U>, 1103 <&tegra_car TEGRA124_CLK_USBD>; 1104 clock-names = "reg", "pll_u", "utmi-pads"; 1105 resets = <&tegra_car 58>, <&tegra_car 22>; 1106 reset-names = "usb", "utmi-pads"; 1107 #phy-cells = <0>; 1108 nvidia,hssync-start-delay = <0>; 1109 nvidia,idle-wait-delay = <17>; 1110 nvidia,elastic-limit = <16>; 1111 nvidia,term-range-adj = <6>; 1112 nvidia,xcvr-setup = <9>; 1113 nvidia,xcvr-lsfslew = <0>; 1114 nvidia,xcvr-lsrslew = <3>; 1115 nvidia,hssquelch-level = <2>; 1116 nvidia,hsdiscon-level = <5>; 1117 nvidia,xcvr-hsslew = <12>; 1118 status = "disabled"; 1119 }; 1120 1121 usb@7d008000 { 1122 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 1123 reg = <0x0 0x7d008000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1125 phy_type = "utmi"; 1126 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1127 resets = <&tegra_car 59>; 1128 reset-names = "usb"; 1129 nvidia,phy = <&phy3>; 1130 status = "disabled"; 1131 }; 1132 1133 phy3: usb-phy@7d008000 { 1134 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1135 reg = <0x0 0x7d008000 0x0 0x4000>, 1136 <0x0 0x7d000000 0x0 0x4000>; 1137 phy_type = "utmi"; 1138 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1139 <&tegra_car TEGRA124_CLK_PLL_U>, 1140 <&tegra_car TEGRA124_CLK_USBD>; 1141 clock-names = "reg", "pll_u", "utmi-pads"; 1142 resets = <&tegra_car 59>, <&tegra_car 22>; 1143 reset-names = "usb", "utmi-pads"; 1144 #phy-cells = <0>; 1145 nvidia,hssync-start-delay = <0>; 1146 nvidia,idle-wait-delay = <17>; 1147 nvidia,elastic-limit = <16>; 1148 nvidia,term-range-adj = <6>; 1149 nvidia,xcvr-setup = <9>; 1150 nvidia,xcvr-lsfslew = <0>; 1151 nvidia,xcvr-lsrslew = <3>; 1152 nvidia,hssquelch-level = <2>; 1153 nvidia,hsdiscon-level = <5>; 1154 nvidia,xcvr-hsslew = <12>; 1155 status = "disabled"; 1156 }; 1157 1158 cpus { 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 1162 cpu@0 { 1163 device_type = "cpu"; 1164 compatible = "arm,cortex-a15"; 1165 reg = <0>; 1166 1167 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1168 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1169 <&tegra_car TEGRA124_CLK_PLL_X>, 1170 <&tegra_car TEGRA124_CLK_PLL_P>, 1171 <&dfll>; 1172 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1173 /* FIXME: what's the actual transition time? */ 1174 clock-latency = <300000>; 1175 }; 1176 1177 cpu@1 { 1178 device_type = "cpu"; 1179 compatible = "arm,cortex-a15"; 1180 reg = <1>; 1181 }; 1182 1183 cpu@2 { 1184 device_type = "cpu"; 1185 compatible = "arm,cortex-a15"; 1186 reg = <2>; 1187 }; 1188 1189 cpu@3 { 1190 device_type = "cpu"; 1191 compatible = "arm,cortex-a15"; 1192 reg = <3>; 1193 }; 1194 }; 1195 1196 pmu { 1197 compatible = "arm,cortex-a15-pmu"; 1198 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1202 interrupt-affinity = <&{/cpus/cpu@0}>, 1203 <&{/cpus/cpu@1}>, 1204 <&{/cpus/cpu@2}>, 1205 <&{/cpus/cpu@3}>; 1206 }; 1207 1208 thermal-zones { 1209 cpu { 1210 polling-delay-passive = <1000>; 1211 polling-delay = <1000>; 1212 1213 thermal-sensors = 1214 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1215 1216 trips { 1217 cpu-shutdown-trip { 1218 temperature = <103000>; 1219 hysteresis = <0>; 1220 type = "critical"; 1221 }; 1222 cpu_throttle_trip: throttle-trip { 1223 temperature = <100000>; 1224 hysteresis = <1000>; 1225 type = "hot"; 1226 }; 1227 }; 1228 1229 cooling-maps { 1230 map0 { 1231 trip = <&cpu_throttle_trip>; 1232 cooling-device = <&throttle_heavy 1 1>; 1233 }; 1234 }; 1235 }; 1236 1237 mem { 1238 polling-delay-passive = <1000>; 1239 polling-delay = <1000>; 1240 1241 thermal-sensors = 1242 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1243 1244 trips { 1245 mem-shutdown-trip { 1246 temperature = <103000>; 1247 hysteresis = <0>; 1248 type = "critical"; 1249 }; 1250 }; 1251 1252 cooling-maps { 1253 /* 1254 * There are currently no cooling maps, 1255 * because there are no cooling devices. 1256 */ 1257 }; 1258 }; 1259 1260 gpu { 1261 polling-delay-passive = <1000>; 1262 polling-delay = <1000>; 1263 1264 thermal-sensors = 1265 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1266 1267 trips { 1268 gpu-shutdown-trip { 1269 temperature = <101000>; 1270 hysteresis = <0>; 1271 type = "critical"; 1272 }; 1273 gpu_throttle_trip: throttle-trip { 1274 temperature = <99000>; 1275 hysteresis = <1000>; 1276 type = "hot"; 1277 }; 1278 }; 1279 1280 cooling-maps { 1281 map0 { 1282 trip = <&gpu_throttle_trip>; 1283 cooling-device = <&throttle_heavy 1 1>; 1284 }; 1285 }; 1286 }; 1287 1288 pllx { 1289 polling-delay-passive = <1000>; 1290 polling-delay = <1000>; 1291 1292 thermal-sensors = 1293 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1294 1295 trips { 1296 pllx-shutdown-trip { 1297 temperature = <103000>; 1298 hysteresis = <0>; 1299 type = "critical"; 1300 }; 1301 }; 1302 1303 cooling-maps { 1304 /* 1305 * There are currently no cooling maps, 1306 * because there are no cooling devices. 1307 */ 1308 }; 1309 }; 1310 }; 1311 1312 timer { 1313 compatible = "arm,armv7-timer"; 1314 interrupts = <GIC_PPI 13 1315 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1316 <GIC_PPI 14 1317 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1318 <GIC_PPI 11 1319 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1320 <GIC_PPI 10 1321 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1322 interrupt-parent = <&gic>; 1323 }; 1324}; 1325