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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/gpio-keys.h>
5#include <dt-bindings/input/input.h>
6#include <dt-bindings/thermal/thermal.h>
7
8#include "tegra20.dtsi"
9#include "tegra20-cpu-opp.dtsi"
10#include "tegra20-cpu-opp-microvolt.dtsi"
11
12/ {
13	model = "Acer Iconia Tab A500";
14	compatible = "acer,picasso", "nvidia,tegra20";
15
16	aliases {
17		mmc0 = &sdmmc4; /* eMMC */
18		mmc1 = &sdmmc3; /* MicroSD */
19		mmc2 = &sdmmc1; /* WiFi */
20
21		rtc0 = &pmic;
22		rtc1 = "/rtc@7000e000";
23
24		serial0 = &uartd; /* Docking station */
25		serial1 = &uartc; /* Bluetooth */
26		serial2 = &uartb; /* GPS */
27	};
28
29	/*
30	 * The decompressor and also some bootloaders rely on a
31	 * pre-existing /chosen node to be available to insert the
32	 * command line and merge other ATAGS info.
33	 */
34	chosen {};
35
36	memory@0 {
37		reg = <0x00000000 0x40000000>;
38	};
39
40	reserved-memory {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		ranges;
44
45		ramoops@2ffe0000 {
46			compatible = "ramoops";
47			reg = <0x2ffe0000 0x10000>;	/* 64kB */
48			console-size = <0x8000>;	/* 32kB */
49			record-size = <0x400>;		/*  1kB */
50			ecc-size = <16>;
51		};
52
53		linux,cma@30000000 {
54			compatible = "shared-dma-pool";
55			alloc-ranges = <0x30000000 0x10000000>;
56			size = <0x10000000>; /* 256MiB */
57			linux,cma-default;
58			reusable;
59		};
60	};
61
62	host1x@50000000 {
63		dc@54200000 {
64			rgb {
65				status = "okay";
66
67				port@0 {
68					lcd_output: endpoint {
69						remote-endpoint = <&lvds_encoder_input>;
70						bus-width = <18>;
71					};
72				};
73			};
74		};
75
76		hdmi@54280000 {
77			status = "okay";
78
79			vdd-supply = <&hdmi_vdd_reg>;
80			pll-supply = <&hdmi_pll_reg>;
81			hdmi-supply = <&vdd_5v0_sys>;
82
83			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
84			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
85				GPIO_ACTIVE_HIGH>;
86		};
87	};
88
89	pinmux@70000014 {
90		pinctrl-names = "default";
91		pinctrl-0 = <&state_default>;
92
93		state_default: pinmux {
94			ata {
95				nvidia,pins = "ata";
96				nvidia,function = "ide";
97			};
98			atb {
99				nvidia,pins = "atb", "gma", "gme";
100				nvidia,function = "sdio4";
101			};
102			atc {
103				nvidia,pins = "atc";
104				nvidia,function = "nand";
105			};
106			atd {
107				nvidia,pins = "atd", "ate", "gmb", "spia",
108					"spib", "spic";
109				nvidia,function = "gmi";
110			};
111			cdev1 {
112				nvidia,pins = "cdev1";
113				nvidia,function = "plla_out";
114			};
115			cdev2 {
116				nvidia,pins = "cdev2";
117				nvidia,function = "pllp_out4";
118			};
119			crtp {
120				nvidia,pins = "crtp", "lm1";
121				nvidia,function = "crt";
122			};
123			csus {
124				nvidia,pins = "csus";
125				nvidia,function = "vi_sensor_clk";
126			};
127			dap1 {
128				nvidia,pins = "dap1";
129				nvidia,function = "dap1";
130			};
131			dap2 {
132				nvidia,pins = "dap2";
133				nvidia,function = "dap2";
134			};
135			dap3 {
136				nvidia,pins = "dap3";
137				nvidia,function = "dap3";
138			};
139			dap4 {
140				nvidia,pins = "dap4";
141				nvidia,function = "dap4";
142			};
143			dta {
144				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
145				nvidia,function = "vi";
146			};
147			dtf {
148				nvidia,pins = "dtf";
149				nvidia,function = "i2c3";
150			};
151			gmc {
152				nvidia,pins = "gmc";
153				nvidia,function = "uartd";
154			};
155			gmd {
156				nvidia,pins = "gmd";
157				nvidia,function = "sflash";
158			};
159			gpu {
160				nvidia,pins = "gpu";
161				nvidia,function = "pwm";
162			};
163			gpu7 {
164				nvidia,pins = "gpu7";
165				nvidia,function = "rtck";
166			};
167			gpv {
168				nvidia,pins = "gpv", "slxa";
169				nvidia,function = "pcie";
170			};
171			hdint {
172				nvidia,pins = "hdint";
173				nvidia,function = "hdmi";
174			};
175			i2cp {
176				nvidia,pins = "i2cp";
177				nvidia,function = "i2cp";
178			};
179			irrx {
180				nvidia,pins = "irrx", "irtx";
181				nvidia,function = "uartb";
182			};
183			kbca {
184				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
185					"kbce", "kbcf";
186				nvidia,function = "kbc";
187			};
188			lcsn {
189				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
190					"lsdi", "lvp0";
191				nvidia,function = "rsvd4";
192			};
193			ld0 {
194				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
195					"ld5", "ld6", "ld7", "ld8", "ld9",
196					"ld10", "ld11", "ld12", "ld13", "ld14",
197					"ld15", "ld16", "ld17", "ldi", "lhp0",
198					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
199					"lsc1", "lsck", "lsda", "lspi", "lvp1",
200					"lvs";
201				nvidia,function = "displaya";
202			};
203			owc {
204				nvidia,pins = "owc", "spdi", "spdo", "uac";
205				nvidia,function = "rsvd2";
206			};
207			pmc {
208				nvidia,pins = "pmc";
209				nvidia,function = "pwr_on";
210			};
211			rm {
212				nvidia,pins = "rm";
213				nvidia,function = "i2c1";
214			};
215			sdb {
216				nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
217				nvidia,function = "sdio3";
218			};
219			sdio1 {
220				nvidia,pins = "sdio1";
221				nvidia,function = "sdio1";
222			};
223			slxd {
224				nvidia,pins = "slxd";
225				nvidia,function = "spdif";
226			};
227			spid {
228				nvidia,pins = "spid", "spie", "spif";
229				nvidia,function = "spi1";
230			};
231			spig {
232				nvidia,pins = "spig", "spih";
233				nvidia,function = "spi2_alt";
234			};
235			uaa {
236				nvidia,pins = "uaa", "uab", "uda";
237				nvidia,function = "ulpi";
238			};
239			uad {
240				nvidia,pins = "uad";
241				nvidia,function = "irda";
242			};
243			uca {
244				nvidia,pins = "uca", "ucb";
245				nvidia,function = "uartc";
246			};
247			conf_ata {
248				nvidia,pins = "ata", "atb", "atc", "atd",
249					"cdev1", "cdev2", "csus", "dap1",
250					"dap4", "dte", "dtf", "gma", "gmc",
251					"gme", "gpu", "gpu7", "gpv", "i2cp",
252					"irrx", "irtx", "pta", "rm",
253					"sdc", "sdd", "slxc", "slxd", "slxk",
254					"spdi", "spdo", "uac", "uad", "uda";
255				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256				nvidia,tristate = <TEGRA_PIN_DISABLE>;
257			};
258			conf_ate {
259				nvidia,pins = "ate", "dap2", "dap3",
260					"gmd", "owc", "spia", "spib", "spic",
261					"spid", "spie";
262				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263				nvidia,tristate = <TEGRA_PIN_ENABLE>;
264			};
265			conf_ck32 {
266				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
267					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
268				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269			};
270			conf_crtp {
271				nvidia,pins = "crtp", "gmb", "slxa", "spig",
272					"spih";
273				nvidia,pull = <TEGRA_PIN_PULL_UP>;
274				nvidia,tristate = <TEGRA_PIN_ENABLE>;
275			};
276			conf_dta {
277				nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
278				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
279				nvidia,tristate = <TEGRA_PIN_DISABLE>;
280			};
281			conf_dte {
282				nvidia,pins = "spif";
283				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284				nvidia,tristate = <TEGRA_PIN_ENABLE>;
285			};
286			conf_hdint {
287				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
288					"lpw1", "lsck", "lsda", "lsdi",
289					"lvp0";
290				nvidia,tristate = <TEGRA_PIN_ENABLE>;
291			};
292			conf_kbca {
293				nvidia,pins = "kbca", "kbcc", "kbcd",
294					"kbce", "kbcf", "sdio1", "uaa",
295					"uab", "uca", "ucb";
296				nvidia,pull = <TEGRA_PIN_PULL_UP>;
297				nvidia,tristate = <TEGRA_PIN_DISABLE>;
298			};
299			conf_lc {
300				nvidia,pins = "lc", "ls";
301				nvidia,pull = <TEGRA_PIN_PULL_UP>;
302			};
303			conf_ld0 {
304				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305					"ld5", "ld6", "ld7", "ld8", "ld9",
306					"ld10", "ld11", "ld12", "ld13", "ld14",
307					"ld15", "ld16", "ld17", "ldi", "lhp0",
308					"lhp1", "lhp2", "lhs", "lm0", "lpp",
309					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
310					"lvp1", "lvs", "pmc", "sdb";
311				nvidia,tristate = <TEGRA_PIN_DISABLE>;
312			};
313			conf_ld17_0 {
314				nvidia,pins = "ld17_0";
315				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316			};
317			drive_ddc {
318				nvidia,pins = "drive_ddc",
319						"drive_vi1",
320						"drive_sdio1";
321				nvidia,pull-up-strength = <31>;
322				nvidia,pull-down-strength = <31>;
323				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
324				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
325				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
326				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
327				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328			};
329			drive_dbg {
330				nvidia,pins = "drive_dbg",
331						"drive_vi2",
332						"drive_at1",
333						"drive_ao1";
334				nvidia,pull-up-strength = <31>;
335				nvidia,pull-down-strength = <31>;
336				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
337				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
338				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
339				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
340				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341			};
342		};
343
344		state_i2cmux_ddc: pinmux_i2cmux_ddc {
345			ddc {
346				nvidia,pins = "ddc";
347				nvidia,function = "i2c2";
348			};
349			pta {
350				nvidia,pins = "pta";
351				nvidia,function = "rsvd4";
352			};
353		};
354
355		state_i2cmux_pta: pinmux_i2cmux_pta {
356			ddc {
357				nvidia,pins = "ddc";
358				nvidia,function = "rsvd4";
359			};
360			pta {
361				nvidia,pins = "pta";
362				nvidia,function = "i2c2";
363			};
364		};
365
366		state_i2cmux_idle: pinmux_i2cmux_idle {
367			ddc {
368				nvidia,pins = "ddc";
369				nvidia,function = "rsvd4";
370			};
371			pta {
372				nvidia,pins = "pta";
373				nvidia,function = "rsvd4";
374			};
375		};
376	};
377
378	tegra_i2s1: i2s@70002800 {
379		status = "okay";
380	};
381
382	uartb: serial@70006040 {
383		compatible = "nvidia,tegra20-hsuart";
384		/* GPS BCM4751 */
385	};
386
387	uartc: serial@70006200 {
388		compatible = "nvidia,tegra20-hsuart";
389		status = "okay";
390
391		/* Azurewave AW-NH665 BCM4329B1 */
392		bluetooth {
393			compatible = "brcm,bcm4329-bt";
394
395			/* PLLP 216MHz / 16 / 4 */
396			max-speed = <3375000>;
397
398			clocks = <&rtc_32k_wifi>;
399			clock-names = "txco";
400
401			vbat-supply  = <&vdd_3v3_sys>;
402			vddio-supply = <&vdd_1v8_sys>;
403
404			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
405			host-wakeup-gpios =   <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
406			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
407		};
408	};
409
410	uartd: serial@70006300 {
411		/* Docking station */
412	};
413
414	i2c@7000c000 {
415		clock-frequency = <400000>;
416		status = "okay";
417
418		wm8903: audio-codec@1a {
419			compatible = "wlf,wm8903";
420			reg = <0x1a>;
421
422			interrupt-parent = <&gpio>;
423			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
424
425			gpio-controller;
426			#gpio-cells = <2>;
427
428			gpio-cfg = <
429				0x0000 /* MIC_LR_OUT#    GPIO, output, low */
430				0x0000 /* FM2018-enable  GPIO, output, low */
431				0x0000 /* Speaker-enable GPIO, output, low */
432				0x0200 /* Interrupt, output */
433				0x01a0 /* BCLK, input, active high */
434			>;
435
436			AVDD-supply  = <&vdd_1v8_sys>;
437			CPVDD-supply = <&vdd_1v8_sys>;
438			DBVDD-supply = <&vdd_1v8_sys>;
439			DCVDD-supply = <&vdd_1v8_sys>;
440		};
441
442		touchscreen@4c {
443			compatible = "atmel,maxtouch";
444			reg = <0x4c>;
445
446			interrupt-parent = <&gpio>;
447			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
448
449			reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
450
451			vdda-supply = <&vdd_3v3_sys>;
452			vdd-supply  = <&vdd_3v3_sys>;
453		};
454
455		gyroscope@68 {
456			compatible = "invensense,mpu3050";
457			reg = <0x68>;
458
459			interrupt-parent = <&gpio>;
460			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
461
462			vdd-supply    = <&vdd_3v3_sys>;
463			vlogic-supply = <&vdd_1v8_sys>;
464
465			mount-matrix =	 "0",  "1",  "0",
466					 "1",  "0",  "0",
467					 "0",  "0", "-1";
468
469			i2c-gate {
470				#address-cells = <1>;
471				#size-cells = <0>;
472
473				accelerometer@f {
474					compatible = "kionix,kxtf9";
475					reg = <0x0f>;
476
477					interrupt-parent = <&gpio>;
478					interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
479
480					mount-matrix =	 "0",  "1",  "0",
481							 "1",  "0",  "0",
482							 "0",  "0", "-1";
483				};
484			};
485		};
486	};
487
488	i2c@7000c400 {
489		clock-frequency = <10000>;
490		status = "okay";
491	};
492
493	i2cmux {
494		compatible = "i2c-mux-pinctrl";
495		#address-cells = <1>;
496		#size-cells = <0>;
497
498		i2c-parent = <&{/i2c@7000c400}>;
499
500		pinctrl-names = "ddc", "pta", "idle";
501		pinctrl-0 = <&state_i2cmux_ddc>;
502		pinctrl-1 = <&state_i2cmux_pta>;
503		pinctrl-2 = <&state_i2cmux_idle>;
504
505		hdmi_ddc: i2c@0 {
506			reg = <0>;
507			#address-cells = <1>;
508			#size-cells = <0>;
509		};
510
511		panel_ddc: i2c@1 {
512			reg = <1>;
513			#address-cells = <1>;
514			#size-cells = <0>;
515		};
516	};
517
518	pwm: pwm@7000a000 {
519		status = "okay";
520	};
521
522	i2c@7000d000 {
523		clock-frequency = <100000>;
524		status = "okay";
525
526		magnetometer@c {
527			compatible = "ak,ak8975";
528			reg = <0x0c>;
529
530			interrupt-parent = <&gpio>;
531			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
532
533			vdd-supply = <&vdd_3v3_sys>;
534			vid-supply = <&vdd_1v8_sys>;
535
536			mount-matrix =	"1",  "0",  "0",
537					"0", "-1",  "0",
538					"0",  "0", "-1";
539		};
540
541		pmic: pmic@34 {
542			compatible = "ti,tps6586x";
543			reg = <0x34>;
544
545			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
546
547			#gpio-cells = <2>;
548			gpio-controller;
549
550			sys-supply       = <&vdd_5v0_sys>;
551			vin-sm0-supply   = <&sys_reg>;
552			vin-sm1-supply   = <&sys_reg>;
553			vin-sm2-supply   = <&sys_reg>;
554			vinldo01-supply  = <&sm2_reg>;
555			vinldo23-supply  = <&sm2_reg>;
556			vinldo4-supply   = <&sm2_reg>;
557			vinldo678-supply = <&sm2_reg>;
558			vinldo9-supply   = <&sm2_reg>;
559
560			regulators {
561				sys_reg: sys {
562					regulator-name = "vdd_sys";
563					regulator-always-on;
564				};
565
566				vdd_core: sm0 {
567					regulator-name = "vdd_sm0,vdd_core";
568					regulator-min-microvolt = <1200000>;
569					regulator-max-microvolt = <1300000>;
570					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
571					regulator-coupled-max-spread = <170000 550000>;
572					regulator-always-on;
573					regulator-boot-on;
574
575					nvidia,tegra-core-regulator;
576				};
577
578				vdd_cpu: sm1 {
579					regulator-name = "vdd_sm1,vdd_cpu";
580					regulator-min-microvolt = <750000>;
581					regulator-max-microvolt = <1125000>;
582					regulator-coupled-with = <&vdd_core &rtc_vdd>;
583					regulator-coupled-max-spread = <550000 550000>;
584					regulator-always-on;
585					regulator-boot-on;
586
587					nvidia,tegra-cpu-regulator;
588				};
589
590				sm2_reg: sm2 {
591					regulator-name = "vdd_sm2,vin_ldo*";
592					regulator-min-microvolt = <3700000>;
593					regulator-max-microvolt = <3700000>;
594					regulator-always-on;
595				};
596
597				/* LDO0 is not connected to anything */
598
599				ldo1 {
600					regulator-name = "vdd_ldo1,avdd_pll*";
601					regulator-min-microvolt = <1100000>;
602					regulator-max-microvolt = <1100000>;
603					regulator-always-on;
604					regulator-boot-on;
605				};
606
607				rtc_vdd: ldo2 {
608					regulator-name = "vdd_ldo2,vdd_rtc";
609					regulator-min-microvolt = <1200000>;
610					regulator-max-microvolt = <1300000>;
611					regulator-coupled-with = <&vdd_core &vdd_cpu>;
612					regulator-coupled-max-spread = <170000 550000>;
613					regulator-always-on;
614					regulator-boot-on;
615
616					nvidia,tegra-rtc-regulator;
617				};
618
619				ldo3 {
620					regulator-name = "vdd_ldo3,avdd_usb*";
621					regulator-min-microvolt = <3300000>;
622					regulator-max-microvolt = <3300000>;
623					regulator-always-on;
624				};
625
626				ldo4 {
627					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
628					regulator-min-microvolt = <1800000>;
629					regulator-max-microvolt = <1800000>;
630					regulator-always-on;
631					regulator-boot-on;
632				};
633
634				vcore_emmc: ldo5 {
635					regulator-name = "vdd_ldo5,vcore_mmc";
636					regulator-min-microvolt = <2850000>;
637					regulator-max-microvolt = <2850000>;
638					regulator-always-on;
639				};
640
641				avdd_vdac_reg: ldo6 {
642					regulator-name = "vdd_ldo6,avdd_vdac";
643					regulator-min-microvolt = <2850000>;
644					regulator-max-microvolt = <2850000>;
645				};
646
647				hdmi_vdd_reg: ldo7 {
648					regulator-name = "vdd_ldo7,avdd_hdmi";
649					regulator-min-microvolt = <3300000>;
650					regulator-max-microvolt = <3300000>;
651				};
652
653				hdmi_pll_reg: ldo8 {
654					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
655					regulator-min-microvolt = <1800000>;
656					regulator-max-microvolt = <1800000>;
657				};
658
659				ldo9 {
660					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
661					regulator-min-microvolt = <2850000>;
662					regulator-max-microvolt = <2850000>;
663					regulator-always-on;
664					regulator-boot-on;
665				};
666
667				ldo_rtc {
668					regulator-name = "vdd_rtc_out,vdd_cell";
669					regulator-min-microvolt = <3300000>;
670					regulator-max-microvolt = <3300000>;
671					regulator-always-on;
672					regulator-boot-on;
673				};
674			};
675		};
676
677		nct1008: temperature-sensor@4c {
678			compatible = "onnn,nct1008";
679			reg = <0x4c>;
680			vcc-supply = <&vdd_3v3_sys>;
681			#thermal-sensor-cells = <1>;
682		};
683	};
684
685	pmc@7000e400 {
686		nvidia,invert-interrupt;
687		nvidia,suspend-mode = <1>;
688		nvidia,cpu-pwr-good-time = <2000>;
689		nvidia,cpu-pwr-off-time = <100>;
690		nvidia,core-pwr-good-time = <3845 3845>;
691		nvidia,core-pwr-off-time = <458>;
692		nvidia,sys-clock-req-active-high;
693	};
694
695	usb@c5000000 {
696		compatible = "nvidia,tegra20-udc";
697		status = "okay";
698		dr_mode = "peripheral";
699	};
700
701	usb-phy@c5000000 {
702		status = "okay";
703		dr_mode = "peripheral";
704		nvidia,xcvr-setup-use-fuses;
705		nvidia,xcvr-lsfslew = <2>;
706		nvidia,xcvr-lsrslew = <2>;
707	};
708
709	usb@c5008000 {
710		status = "okay";
711	};
712
713	usb-phy@c5008000 {
714		status = "okay";
715		nvidia,xcvr-setup-use-fuses;
716		nvidia,xcvr-lsfslew = <2>;
717		nvidia,xcvr-lsrslew = <2>;
718		vbus-supply = <&vdd_5v0_sys>;
719	};
720
721	brcm_wifi_pwrseq: wifi-pwrseq {
722		compatible = "mmc-pwrseq-simple";
723
724		clocks = <&rtc_32k_wifi>;
725		clock-names = "ext_clock";
726
727		reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
728		post-power-on-delay-ms = <300>;
729		power-off-delay-us = <300>;
730	};
731
732	sdmmc1: mmc@c8000000 {
733		status = "okay";
734
735		#address-cells = <1>;
736		#size-cells = <0>;
737
738		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
739		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
740		assigned-clock-rates = <50000000>;
741
742		max-frequency = <50000000>;
743		keep-power-in-suspend;
744		bus-width = <4>;
745		non-removable;
746
747		mmc-pwrseq = <&brcm_wifi_pwrseq>;
748		vmmc-supply = <&vdd_3v3_sys>;
749		vqmmc-supply = <&vdd_3v3_sys>;
750
751		/* Azurewave AW-NH611 BCM4329 */
752		wifi@1 {
753			reg = <1>;
754			compatible = "brcm,bcm4329-fmac";
755			interrupt-parent = <&gpio>;
756			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
757			interrupt-names = "host-wake";
758		};
759	};
760
761	sdmmc3: mmc@c8000400 {
762		status = "okay";
763		bus-width = <4>;
764		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
765		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
766		vmmc-supply = <&vdd_3v3_sys>;
767		vqmmc-supply = <&vdd_3v3_sys>;
768	};
769
770	sdmmc4: mmc@c8000600 {
771		status = "okay";
772		bus-width = <8>;
773		vmmc-supply = <&vcore_emmc>;
774		vqmmc-supply = <&vdd_3v3_sys>;
775		non-removable;
776	};
777
778	mains: ac-adapter-detect {
779		compatible = "gpio-charger";
780		charger-type = "mains";
781		gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
782	};
783
784	backlight: backlight {
785		compatible = "pwm-backlight";
786
787		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
788		power-supply = <&vdd_3v3_sys>;
789		pwms = <&pwm 2 41667>;
790
791		brightness-levels = <7 255>;
792		num-interpolated-steps = <248>;
793		default-brightness-level = <20>;
794	};
795
796	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
797	clk32k_in: clock@0 {
798		compatible = "fixed-clock";
799		#clock-cells = <0>;
800		clock-frequency = <32768>;
801		clock-output-names = "tps658621-out32k";
802	};
803
804	/*
805	 * This standalone onboard fixed-clock always-ON 32KHz
806	 * oscillator is used as a reference clock-source by the
807	 * Azurewave WiFi/BT module.
808	 */
809	rtc_32k_wifi: clock@1 {
810		compatible = "fixed-clock";
811		#clock-cells = <0>;
812		clock-frequency = <32768>;
813		clock-output-names = "kk3270032";
814	};
815
816	cpus {
817		cpu0: cpu@0 {
818			cpu-supply = <&vdd_cpu>;
819			operating-points-v2 = <&cpu0_opp_table>;
820			#cooling-cells = <2>;
821		};
822
823		cpu@1 {
824			cpu-supply = <&vdd_cpu>;
825			operating-points-v2 = <&cpu0_opp_table>;
826		};
827	};
828
829	display-panel {
830		compatible = "auo,b101ew05", "panel-lvds";
831
832		ddc-i2c-bus = <&panel_ddc>;
833		power-supply = <&vdd_pnl>;
834		backlight = <&backlight>;
835
836		width-mm = <218>;
837		height-mm = <135>;
838
839		data-mapping = "jeida-18";
840
841		panel-timing {
842			clock-frequency = <71200000>;
843			hactive = <1280>;
844			vactive = <800>;
845			hfront-porch = <8>;
846			hback-porch = <18>;
847			hsync-len = <184>;
848			vsync-len = <3>;
849			vfront-porch = <4>;
850			vback-porch = <8>;
851		};
852
853		port {
854			panel_input: endpoint {
855				remote-endpoint = <&lvds_encoder_output>;
856			};
857		};
858	};
859
860	gpio-keys {
861		compatible = "gpio-keys";
862
863		power {
864			label = "Power";
865			gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
866			linux,code = <KEY_POWER>;
867			debounce-interval = <10>;
868			wakeup-event-action = <EV_ACT_ASSERTED>;
869			wakeup-source;
870		};
871
872		rotation-lock {
873			label = "Rotate-lock";
874			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
875			linux,code = <SW_ROTATE_LOCK>;
876			linux,input-type = <EV_SW>;
877			debounce-interval = <10>;
878		};
879
880		volume-up {
881			label = "Volume Up";
882			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
883			linux,code = <KEY_VOLUMEUP>;
884			debounce-interval = <10>;
885			wakeup-event-action = <EV_ACT_ASSERTED>;
886			wakeup-source;
887		};
888
889		volume-down {
890			label = "Volume Down";
891			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
892			linux,code = <KEY_VOLUMEDOWN>;
893			debounce-interval = <10>;
894			wakeup-event-action = <EV_ACT_ASSERTED>;
895			wakeup-source;
896		};
897	};
898
899	haptic-feedback {
900		compatible = "gpio-vibrator";
901		enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
902		vcc-supply = <&vdd_3v3_sys>;
903	};
904
905	lvds-encoder {
906		compatible = "ti,sn75lvds83", "lvds-encoder";
907
908		powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
909
910		ports {
911			#address-cells = <1>;
912			#size-cells = <0>;
913
914			port@0 {
915				reg = <0>;
916
917				lvds_encoder_input: endpoint {
918					remote-endpoint = <&lcd_output>;
919				};
920			};
921
922			port@1 {
923				reg = <1>;
924
925				lvds_encoder_output: endpoint {
926					remote-endpoint = <&panel_input>;
927				};
928			};
929		};
930	};
931
932	vdd_5v0_sys: regulator@0 {
933		compatible = "regulator-fixed";
934		regulator-name = "vdd_5v0";
935		regulator-min-microvolt = <5000000>;
936		regulator-max-microvolt = <5000000>;
937		regulator-always-on;
938	};
939
940	vdd_3v3_sys: regulator@1 {
941		compatible = "regulator-fixed";
942		regulator-name = "vdd_3v3_vs";
943		regulator-min-microvolt = <3300000>;
944		regulator-max-microvolt = <3300000>;
945		regulator-always-on;
946		vin-supply = <&vdd_5v0_sys>;
947	};
948
949	vdd_1v8_sys: regulator@2 {
950		compatible = "regulator-fixed";
951		regulator-name = "vdd_1v8_vs";
952		regulator-min-microvolt = <1800000>;
953		regulator-max-microvolt = <1800000>;
954		regulator-always-on;
955		vin-supply = <&vdd_5v0_sys>;
956	};
957
958	vdd_pnl: regulator@3 {
959		compatible = "regulator-fixed";
960		regulator-name = "vdd_panel";
961		regulator-min-microvolt = <3300000>;
962		regulator-max-microvolt = <3300000>;
963		regulator-enable-ramp-delay = <300000>;
964		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
965		enable-active-high;
966		vin-supply = <&vdd_5v0_sys>;
967	};
968
969	sound {
970		compatible = "nvidia,tegra-audio-wm8903-picasso",
971			     "nvidia,tegra-audio-wm8903";
972		nvidia,model = "Acer Iconia Tab A500 WM8903";
973
974		nvidia,audio-routing =
975			"Headphone Jack", "HPOUTR",
976			"Headphone Jack", "HPOUTL",
977			"Int Spk", "LINEOUTL",
978			"Int Spk", "LINEOUTR",
979			"Mic Jack", "MICBIAS",
980			"IN2L", "Mic Jack",
981			"IN2R", "Mic Jack",
982			"IN1L", "Int Mic",
983			"IN1R", "Int Mic";
984
985		nvidia,i2s-controller = <&tegra_i2s1>;
986		nvidia,audio-codec = <&wm8903>;
987
988		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
989		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
990		nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
991		nvidia,headset;
992
993		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
994			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
995			 <&tegra_car TEGRA20_CLK_CDEV1>;
996		clock-names = "pll_a", "pll_a_out0", "mclk";
997	};
998
999	thermal-zones {
1000		nct1008-local {
1001			polling-delay-passive = <1000>; /* milliseconds */
1002			polling-delay = <0>; /* milliseconds */
1003
1004			thermal-sensors = <&nct1008 0>;
1005		};
1006
1007		nct1008-remote {
1008			polling-delay-passive = <1000>; /* milliseconds */
1009			polling-delay = <5000>; /* milliseconds */
1010
1011			thermal-sensors = <&nct1008 1>;
1012
1013			trips {
1014				trip0: cpu-alert0 {
1015					/* start throttling at 50C */
1016					temperature = <50000>;
1017					hysteresis = <3000>;
1018					type = "passive";
1019				};
1020
1021				trip1: cpu-crit {
1022					/* shut down at 60C */
1023					temperature = <60000>;
1024					hysteresis = <2000>;
1025					type = "critical";
1026				};
1027			};
1028
1029			cooling-maps {
1030				map0 {
1031					trip = <&trip0>;
1032					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1033				};
1034			};
1035		};
1036	};
1037
1038	memory-controller@7000f400 {
1039		nvidia,use-ram-code;
1040
1041		emc-tables@0 {
1042			nvidia,ram-code = <0>; /* elpida-8gb */
1043
1044			#address-cells = <1>;
1045			#size-cells = <0>;
1046
1047			emc-table@25000 {
1048				reg = <25000>;
1049				compatible = "nvidia,tegra20-emc-table";
1050				clock-frequency = <25000>;
1051				nvidia,emc-registers = <0x00000002 0x00000006
1052					0x00000003 0x00000003 0x00000006 0x00000004
1053					0x00000002 0x00000009 0x00000003 0x00000003
1054					0x00000002 0x00000002 0x00000002 0x00000004
1055					0x00000003 0x00000008 0x0000000b 0x0000004d
1056					0x00000000 0x00000003 0x00000003 0x00000003
1057					0x00000008 0x00000001 0x0000000a 0x00000004
1058					0x00000003 0x00000008 0x00000004 0x00000006
1059					0x00000002 0x00000068 0x00000000 0x00000003
1060					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1061					0x00070000 0x00000000 0x00000000 0x00000003
1062					0x00000000 0x00000000 0x00000000 0x00000000>;
1063			};
1064
1065			emc-table@50000 {
1066				reg = <50000>;
1067				compatible = "nvidia,tegra20-emc-table";
1068				clock-frequency = <50000>;
1069				nvidia,emc-registers = <0x00000003 0x00000007
1070					0x00000003 0x00000003 0x00000006 0x00000004
1071					0x00000002 0x00000009 0x00000003 0x00000003
1072					0x00000002 0x00000002 0x00000002 0x00000005
1073					0x00000003 0x00000008 0x0000000b 0x0000009f
1074					0x00000000 0x00000003 0x00000003 0x00000003
1075					0x00000008 0x00000001 0x0000000a 0x00000007
1076					0x00000003 0x00000008 0x00000004 0x00000006
1077					0x00000002 0x000000d0 0x00000000 0x00000000
1078					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1079					0x00070000 0x00000000 0x00000000 0x00000005
1080					0x00000000 0x00000000 0x00000000 0x00000000>;
1081			};
1082
1083			emc-table@75000 {
1084				reg = <75000>;
1085				compatible = "nvidia,tegra20-emc-table";
1086				clock-frequency = <75000>;
1087				nvidia,emc-registers = <0x00000005 0x0000000a
1088					0x00000004 0x00000003 0x00000006 0x00000004
1089					0x00000002 0x00000009 0x00000003 0x00000003
1090					0x00000002 0x00000002 0x00000002 0x00000005
1091					0x00000003 0x00000008 0x0000000b 0x000000ff
1092					0x00000000 0x00000003 0x00000003 0x00000003
1093					0x00000008 0x00000001 0x0000000a 0x0000000b
1094					0x00000003 0x00000008 0x00000004 0x00000006
1095					0x00000002 0x00000138 0x00000000 0x00000000
1096					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1097					0x00070000 0x00000000 0x00000000 0x00000007
1098					0x00000000 0x00000000 0x00000000 0x00000000>;
1099			};
1100
1101			emc-table@150000 {
1102				reg = <150000>;
1103				compatible = "nvidia,tegra20-emc-table";
1104				clock-frequency = <150000>;
1105				nvidia,emc-registers = <0x00000009 0x00000014
1106					0x00000007 0x00000003 0x00000006 0x00000004
1107					0x00000002 0x00000009 0x00000003 0x00000003
1108					0x00000002 0x00000002 0x00000002 0x00000005
1109					0x00000003 0x00000008 0x0000000b 0x0000021f
1110					0x00000000 0x00000003 0x00000003 0x00000003
1111					0x00000008 0x00000001 0x0000000a 0x00000015
1112					0x00000003 0x00000008 0x00000004 0x00000006
1113					0x00000002 0x00000270 0x00000000 0x00000001
1114					0x00000000 0x00000000 0x00000282 0xa07c04ae
1115					0x007dd510 0x00000000 0x00000000 0x0000000e
1116					0x00000000 0x00000000 0x00000000 0x00000000>;
1117			};
1118
1119			emc-table@300000 {
1120				reg = <300000>;
1121				compatible = "nvidia,tegra20-emc-table";
1122				clock-frequency = <300000>;
1123				nvidia,emc-registers = <0x00000012 0x00000027
1124					0x0000000d 0x00000006 0x00000007 0x00000005
1125					0x00000003 0x00000009 0x00000006 0x00000006
1126					0x00000003 0x00000003 0x00000002 0x00000006
1127					0x00000003 0x00000009 0x0000000c 0x0000045f
1128					0x00000000 0x00000004 0x00000004 0x00000006
1129					0x00000008 0x00000001 0x0000000e 0x0000002a
1130					0x00000003 0x0000000f 0x00000007 0x00000005
1131					0x00000002 0x000004e1 0x00000005 0x00000002
1132					0x00000000 0x00000000 0x00000282 0xe059048b
1133					0x007e1510 0x00000000 0x00000000 0x0000001b
1134					0x00000000 0x00000000 0x00000000 0x00000000>;
1135			};
1136		};
1137
1138		emc-tables@1 {
1139			nvidia,ram-code = <1>; /* elpida-4gb */
1140
1141			#address-cells = <1>;
1142			#size-cells = <0>;
1143
1144			emc-table@25000 {
1145				reg = <25000>;
1146				compatible = "nvidia,tegra20-emc-table";
1147				clock-frequency = <25000>;
1148				nvidia,emc-registers = <0x00000002 0x00000006
1149					0x00000003 0x00000003 0x00000006 0x00000004
1150					0x00000002 0x00000009 0x00000003 0x00000003
1151					0x00000002 0x00000002 0x00000002 0x00000004
1152					0x00000003 0x00000008 0x0000000b 0x0000004d
1153					0x00000000 0x00000003 0x00000003 0x00000003
1154					0x00000008 0x00000001 0x0000000a 0x00000004
1155					0x00000003 0x00000008 0x00000004 0x00000006
1156					0x00000002 0x00000068 0x00000000 0x00000003
1157					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1158					0x0007c000 0x00000000 0x00000000 0x00000003
1159					0x00000000 0x00000000 0x00000000 0x00000000>;
1160			};
1161
1162			emc-table@50000 {
1163				reg = <50000>;
1164				compatible = "nvidia,tegra20-emc-table";
1165				clock-frequency = <50000>;
1166				nvidia,emc-registers = <0x00000003 0x00000007
1167					0x00000003 0x00000003 0x00000006 0x00000004
1168					0x00000002 0x00000009 0x00000003 0x00000003
1169					0x00000002 0x00000002 0x00000002 0x00000005
1170					0x00000003 0x00000008 0x0000000b 0x0000009f
1171					0x00000000 0x00000003 0x00000003 0x00000003
1172					0x00000008 0x00000001 0x0000000a 0x00000007
1173					0x00000003 0x00000008 0x00000004 0x00000006
1174					0x00000002 0x000000d0 0x00000000 0x00000000
1175					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1176					0x0007c000 0x00000000 0x00000000 0x00000005
1177					0x00000000 0x00000000 0x00000000 0x00000000>;
1178			};
1179
1180			emc-table@75000 {
1181				reg = <75000>;
1182				compatible = "nvidia,tegra20-emc-table";
1183				clock-frequency = <75000>;
1184				nvidia,emc-registers = <0x00000005 0x0000000a
1185					0x00000004 0x00000003 0x00000006 0x00000004
1186					0x00000002 0x00000009 0x00000003 0x00000003
1187					0x00000002 0x00000002 0x00000002 0x00000005
1188					0x00000003 0x00000008 0x0000000b 0x000000ff
1189					0x00000000 0x00000003 0x00000003 0x00000003
1190					0x00000008 0x00000001 0x0000000a 0x0000000b
1191					0x00000003 0x00000008 0x00000004 0x00000006
1192					0x00000002 0x00000138 0x00000000 0x00000000
1193					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1194					0x0007c000 0x00000000 0x00000000 0x00000007
1195					0x00000000 0x00000000 0x00000000 0x00000000>;
1196			};
1197
1198			emc-table@150000 {
1199				reg = <150000>;
1200				compatible = "nvidia,tegra20-emc-table";
1201				clock-frequency = <150000>;
1202				nvidia,emc-registers = <0x00000009 0x00000014
1203					0x00000007 0x00000003 0x00000006 0x00000004
1204					0x00000002 0x00000009 0x00000003 0x00000003
1205					0x00000002 0x00000002 0x00000002 0x00000005
1206					0x00000003 0x00000008 0x0000000b 0x0000021f
1207					0x00000000 0x00000003 0x00000003 0x00000003
1208					0x00000008 0x00000001 0x0000000a 0x00000015
1209					0x00000003 0x00000008 0x00000004 0x00000006
1210					0x00000002 0x00000270 0x00000000 0x00000001
1211					0x00000000 0x00000000 0x00000282 0xa07c04ae
1212					0x007e4010 0x00000000 0x00000000 0x0000000e
1213					0x00000000 0x00000000 0x00000000 0x00000000>;
1214			};
1215
1216			emc-table@300000 {
1217				reg = <300000>;
1218				compatible = "nvidia,tegra20-emc-table";
1219				clock-frequency = <300000>;
1220				nvidia,emc-registers = <0x00000012 0x00000027
1221					0x0000000d 0x00000006 0x00000007 0x00000005
1222					0x00000003 0x00000009 0x00000006 0x00000006
1223					0x00000003 0x00000003 0x00000002 0x00000006
1224					0x00000003 0x00000009 0x0000000c 0x0000045f
1225					0x00000000 0x00000004 0x00000004 0x00000006
1226					0x00000008 0x00000001 0x0000000e 0x0000002a
1227					0x00000003 0x0000000f 0x00000007 0x00000005
1228					0x00000002 0x000004e1 0x00000005 0x00000002
1229					0x00000000 0x00000000 0x00000282 0xe059048b
1230					0x007e0010 0x00000000 0x00000000 0x0000001b
1231					0x00000000 0x00000000 0x00000000 0x00000000>;
1232			};
1233		};
1234
1235		emc-tables@2 {
1236			nvidia,ram-code = <2>; /* hynix-8gb */
1237
1238			#address-cells = <1>;
1239			#size-cells = <0>;
1240
1241			emc-table@25000 {
1242				reg = <25000>;
1243				compatible = "nvidia,tegra20-emc-table";
1244				clock-frequency = <25000>;
1245				nvidia,emc-registers = <0x00000002 0x00000006
1246					0x00000003 0x00000003 0x00000006 0x00000004
1247					0x00000002 0x00000009 0x00000003 0x00000003
1248					0x00000002 0x00000002 0x00000002 0x00000004
1249					0x00000003 0x00000008 0x0000000b 0x0000004d
1250					0x00000000 0x00000003 0x00000003 0x00000003
1251					0x00000008 0x00000001 0x0000000a 0x00000004
1252					0x00000003 0x00000008 0x00000004 0x00000006
1253					0x00000002 0x00000068 0x00000000 0x00000003
1254					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1255					0x00070000 0x00000000 0x00000000 0x00000003
1256					0x00000000 0x00000000 0x00000000 0x00000000>;
1257			};
1258
1259			emc-table@50000 {
1260				reg = <50000>;
1261				compatible = "nvidia,tegra20-emc-table";
1262				clock-frequency = <50000>;
1263				nvidia,emc-registers = <0x00000003 0x00000007
1264					0x00000003 0x00000003 0x00000006 0x00000004
1265					0x00000002 0x00000009 0x00000003 0x00000003
1266					0x00000002 0x00000002 0x00000002 0x00000005
1267					0x00000003 0x00000008 0x0000000b 0x0000009f
1268					0x00000000 0x00000003 0x00000003 0x00000003
1269					0x00000008 0x00000001 0x0000000a 0x00000007
1270					0x00000003 0x00000008 0x00000004 0x00000006
1271					0x00000002 0x000000d0 0x00000000 0x00000000
1272					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1273					0x00070000 0x00000000 0x00000000 0x00000005
1274					0x00000000 0x00000000 0x00000000 0x00000000>;
1275			};
1276
1277			emc-table@75000 {
1278				reg = <75000>;
1279				compatible = "nvidia,tegra20-emc-table";
1280				clock-frequency = <75000>;
1281				nvidia,emc-registers = <0x00000005 0x0000000a
1282					0x00000004 0x00000003 0x00000006 0x00000004
1283					0x00000002 0x00000009 0x00000003 0x00000003
1284					0x00000002 0x00000002 0x00000002 0x00000005
1285					0x00000003 0x00000008 0x0000000b 0x000000ff
1286					0x00000000 0x00000003 0x00000003 0x00000003
1287					0x00000008 0x00000001 0x0000000a 0x0000000b
1288					0x00000003 0x00000008 0x00000004 0x00000006
1289					0x00000002 0x00000138 0x00000000 0x00000000
1290					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1291					0x00070000 0x00000000 0x00000000 0x00000007
1292					0x00000000 0x00000000 0x00000000 0x00000000>;
1293			};
1294
1295			emc-table@150000 {
1296				reg = <150000>;
1297				compatible = "nvidia,tegra20-emc-table";
1298				clock-frequency = <150000>;
1299				nvidia,emc-registers = <0x00000009 0x00000014
1300					0x00000007 0x00000003 0x00000006 0x00000004
1301					0x00000002 0x00000009 0x00000003 0x00000003
1302					0x00000002 0x00000002 0x00000002 0x00000005
1303					0x00000003 0x00000008 0x0000000b 0x0000021f
1304					0x00000000 0x00000003 0x00000003 0x00000003
1305					0x00000008 0x00000001 0x0000000a 0x00000015
1306					0x00000003 0x00000008 0x00000004 0x00000006
1307					0x00000002 0x00000270 0x00000000 0x00000001
1308					0x00000000 0x00000000 0x00000282 0xa07c04ae
1309					0x007dd010 0x00000000 0x00000000 0x0000000e
1310					0x00000000 0x00000000 0x00000000 0x00000000>;
1311			};
1312
1313			emc-table@300000 {
1314				reg = <300000>;
1315				compatible = "nvidia,tegra20-emc-table";
1316				clock-frequency = <300000>;
1317				nvidia,emc-registers = <0x00000012 0x00000027
1318					0x0000000d 0x00000006 0x00000007 0x00000005
1319					0x00000003 0x00000009 0x00000006 0x00000006
1320					0x00000003 0x00000003 0x00000002 0x00000006
1321					0x00000003 0x00000009 0x0000000c 0x0000045f
1322					0x00000000 0x00000004 0x00000004 0x00000006
1323					0x00000008 0x00000001 0x0000000e 0x0000002a
1324					0x00000003 0x0000000f 0x00000007 0x00000005
1325					0x00000002 0x000004e1 0x00000005 0x00000002
1326					0x00000000 0x00000000 0x00000282 0xe059048b
1327					0x007e2010 0x00000000 0x00000000 0x0000001b
1328					0x00000000 0x00000000 0x00000000 0x00000000>;
1329			};
1330		};
1331
1332		emc-tables@3 {
1333			nvidia,ram-code = <3>; /* hynix-4gb */
1334
1335			#address-cells = <1>;
1336			#size-cells = <0>;
1337
1338			emc-table@25000 {
1339				reg = <25000>;
1340				compatible = "nvidia,tegra20-emc-table";
1341				clock-frequency = <25000>;
1342				nvidia,emc-registers = <0x00000002 0x00000006
1343					0x00000003 0x00000003 0x00000006 0x00000004
1344					0x00000002 0x00000009 0x00000003 0x00000003
1345					0x00000002 0x00000002 0x00000002 0x00000004
1346					0x00000003 0x00000008 0x0000000b 0x0000004d
1347					0x00000000 0x00000003 0x00000003 0x00000003
1348					0x00000008 0x00000001 0x0000000a 0x00000004
1349					0x00000003 0x00000008 0x00000004 0x00000006
1350					0x00000002 0x00000068 0x00000000 0x00000003
1351					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1352					0x0007c000 0x00000000 0x00000000 0x00000003
1353					0x00000000 0x00000000 0x00000000 0x00000000>;
1354			};
1355
1356			emc-table@50000 {
1357				reg = <50000>;
1358				compatible = "nvidia,tegra20-emc-table";
1359				clock-frequency = <50000>;
1360				nvidia,emc-registers = <0x00000003 0x00000007
1361					0x00000003 0x00000003 0x00000006 0x00000004
1362					0x00000002 0x00000009 0x00000003 0x00000003
1363					0x00000002 0x00000002 0x00000002 0x00000005
1364					0x00000003 0x00000008 0x0000000b 0x0000009f
1365					0x00000000 0x00000003 0x00000003 0x00000003
1366					0x00000008 0x00000001 0x0000000a 0x00000007
1367					0x00000003 0x00000008 0x00000004 0x00000006
1368					0x00000002 0x000000d0 0x00000000 0x00000000
1369					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1370					0x0007c000 0x00078000 0x00000000 0x00000005
1371					0x00000000 0x00000000 0x00000000 0x00000000>;
1372			};
1373
1374			emc-table@75000 {
1375				reg = <75000>;
1376				compatible = "nvidia,tegra20-emc-table";
1377				clock-frequency = <75000>;
1378				nvidia,emc-registers = <0x00000005 0x0000000a
1379					0x00000004 0x00000003 0x00000006 0x00000004
1380					0x00000002 0x00000009 0x00000003 0x00000003
1381					0x00000002 0x00000002 0x00000002 0x00000005
1382					0x00000003 0x00000008 0x0000000b 0x000000ff
1383					0x00000000 0x00000003 0x00000003 0x00000003
1384					0x00000008 0x00000001 0x0000000a 0x0000000b
1385					0x00000003 0x00000008 0x00000004 0x00000006
1386					0x00000002 0x00000138 0x00000000 0x00000000
1387					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1388					0x0007c000 0x00000000 0x00000000 0x00000007
1389					0x00000000 0x00000000 0x00000000 0x00000000>;
1390			};
1391
1392			emc-table@150000 {
1393				reg = <150000>;
1394				compatible = "nvidia,tegra20-emc-table";
1395				clock-frequency = <150000>;
1396				nvidia,emc-registers = <0x00000009 0x00000014
1397					0x00000007 0x00000003 0x00000006 0x00000004
1398					0x00000002 0x00000009 0x00000003 0x00000003
1399					0x00000002 0x00000002 0x00000002 0x00000005
1400					0x00000003 0x00000008 0x0000000b 0x0000021f
1401					0x00000000 0x00000003 0x00000003 0x00000003
1402					0x00000008 0x00000001 0x0000000a 0x00000015
1403					0x00000003 0x00000008 0x00000004 0x00000006
1404					0x00000002 0x00000270 0x00000000 0x00000001
1405					0x00000000 0x00000000 0x00000282 0xa07c04ae
1406					0x007e4010 0x00000000 0x00000000 0x0000000e
1407					0x00000000 0x00000000 0x00000000 0x00000000>;
1408			};
1409
1410			emc-table@300000 {
1411				reg = <300000>;
1412				compatible = "nvidia,tegra20-emc-table";
1413				clock-frequency = <300000>;
1414				nvidia,emc-registers = <0x00000012 0x00000027
1415					0x0000000d 0x00000006 0x00000007 0x00000005
1416					0x00000003 0x00000009 0x00000006 0x00000006
1417					0x00000003 0x00000003 0x00000002 0x00000006
1418					0x00000003 0x00000009 0x0000000c 0x0000045f
1419					0x00000000 0x00000004 0x00000004 0x00000006
1420					0x00000008 0x00000001 0x0000000e 0x0000002a
1421					0x00000003 0x0000000f 0x00000007 0x00000005
1422					0x00000002 0x000004e1 0x00000005 0x00000002
1423					0x00000000 0x00000000 0x00000282 0xe059048b
1424					0x007e0010 0x00000000 0x00000000 0x0000001b
1425					0x00000000 0x00000000 0x00000000 0x00000000>;
1426			};
1427		};
1428	};
1429};
1430