• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  linux/arch/arm/mm/cache-v7.S
4 *
5 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
6 *  Copyright (C) 2005 ARM Ltd.
7 *
8 *  This is the "shell" of the ARMv7 processor support.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12#include <asm/assembler.h>
13#include <asm/errno.h>
14#include <asm/unwind.h>
15#include <asm/hardware/cache-b15-rac.h>
16
17#include "proc-macros.S"
18
19#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
20.globl icache_size
21	.data
22	.align	2
23icache_size:
24	.long	64
25	.text
26#endif
27/*
28 * The secondary kernel init calls v7_flush_dcache_all before it enables
29 * the L1; however, the L1 comes out of reset in an undefined state, so
30 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
31 * of cache lines with uninitialized data and uninitialized tags to get
32 * written out to memory, which does really unpleasant things to the main
33 * processor.  We fix this by performing an invalidate, rather than a
34 * clean + invalidate, before jumping into the kernel.
35 *
36 * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
37 * to be called for both secondary cores startup and primary core resume
38 * procedures.
39 */
40ENTRY(v7_invalidate_l1)
41	mov	r0, #0
42	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
43	isb
44	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
45
46       movw    r1, #0x7fff
47       and     r2, r1, r0, lsr #13
48
49       movw    r1, #0x3ff
50
51       and     r3, r1, r0, lsr #3      @ NumWays - 1
52       add     r2, r2, #1              @ NumSets
53
54       and     r0, r0, #0x7
55       add     r0, r0, #4      @ SetShift
56
57       clz     r1, r3          @ WayShift
58       add     r4, r3, #1      @ NumWays
591:     sub     r2, r2, #1      @ NumSets--
60       mov     r3, r4          @ Temp = NumWays
612:     subs    r3, r3, #1      @ Temp--
62       mov     r5, r3, lsl r1
63       mov     r6, r2, lsl r0
64       orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
65       mcr     p15, 0, r5, c7, c6, 2
66       bgt     2b
67       cmp     r2, #0
68       bgt     1b
69       dsb     st
70       isb
71       ret     lr
72ENDPROC(v7_invalidate_l1)
73
74/*
75 *	v7_flush_icache_all()
76 *
77 *	Flush the whole I-cache.
78 *
79 *	Registers:
80 *	r0 - set to 0
81 */
82ENTRY(v7_flush_icache_all)
83	mov	r0, #0
84	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
85	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
86	ret	lr
87ENDPROC(v7_flush_icache_all)
88
89 /*
90 *     v7_flush_dcache_louis()
91 *
92 *     Flush the D-cache up to the Level of Unification Inner Shareable
93 *
94 *     Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
95 */
96
97ENTRY(v7_flush_dcache_louis)
98	dmb					@ ensure ordering with previous memory accesses
99	mrc	p15, 1, r0, c0, c0, 1		@ read clidr, r0 = clidr
100ALT_SMP(mov	r3, r0, lsr #20)		@ move LoUIS into position
101ALT_UP(	mov	r3, r0, lsr #26)		@ move LoUU into position
102	ands	r3, r3, #7 << 1 		@ extract LoU*2 field from clidr
103	bne	start_flush_levels		@ LoU != 0, start flushing
104#ifdef CONFIG_ARM_ERRATA_643719
105ALT_SMP(mrc	p15, 0, r2, c0, c0, 0)		@ read main ID register
106ALT_UP(	ret	lr)				@ LoUU is zero, so nothing to do
107	movw	r1, #:lower16:(0x410fc090 >> 4)	@ ID of ARM Cortex A9 r0p?
108	movt	r1, #:upper16:(0x410fc090 >> 4)
109	teq	r1, r2, lsr #4			@ test for errata affected core and if so...
110	moveq	r3, #1 << 1			@   fix LoUIS value
111	beq	start_flush_levels		@   start flushing cache levels
112#endif
113	ret	lr
114ENDPROC(v7_flush_dcache_louis)
115
116/*
117 *	v7_flush_dcache_all()
118 *
119 *	Flush the whole D-cache.
120 *
121 *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
122 *
123 *	- mm    - mm_struct describing address space
124 */
125ENTRY(v7_flush_dcache_all)
126	dmb					@ ensure ordering with previous memory accesses
127	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
128	mov	r3, r0, lsr #23			@ move LoC into position
129	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
130	beq	finished			@ if loc is 0, then no need to clean
131start_flush_levels:
132	mov	r10, #0				@ start clean at cache level 0
133flush_levels:
134	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
135	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
136	and	r1, r1, #7			@ mask of the bits for current cache only
137	cmp	r1, #2				@ see what cache we have at this level
138	blt	skip				@ skip if no cache, or just i-cache
139#ifdef CONFIG_PREEMPTION
140	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic
141#endif
142	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
143	isb					@ isb to sych the new cssr&csidr
144	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
145#ifdef CONFIG_PREEMPTION
146	restore_irqs_notrace r9
147#endif
148	and	r2, r1, #7			@ extract the length of the cache lines
149	add	r2, r2, #4			@ add 4 (line length offset)
150	movw	r4, #0x3ff
151	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
152	clz	r5, r4				@ find bit position of way size increment
153	movw	r7, #0x7fff
154	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
155loop1:
156	mov	r9, r7				@ create working copy of max index
157loop2:
158 ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
159 THUMB(	lsl	r6, r4, r5		)
160 THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
161 ARM(	orr	r11, r11, r9, lsl r2	)	@ factor index number into r11
162 THUMB(	lsl	r6, r9, r2		)
163 THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
164	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
165	subs	r9, r9, #1			@ decrement the index
166	bge	loop2
167	subs	r4, r4, #1			@ decrement the way
168	bge	loop1
169skip:
170	add	r10, r10, #2			@ increment cache number
171	cmp	r3, r10
172#ifdef CONFIG_ARM_ERRATA_814220
173	dsb
174#endif
175	bgt	flush_levels
176finished:
177	mov	r10, #0				@ switch back to cache level 0
178	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
179	dsb	st
180	isb
181	ret	lr
182ENDPROC(v7_flush_dcache_all)
183
184/*
185 *	v7_flush_cache_all()
186 *
187 *	Flush the entire cache system.
188 *  The data cache flush is now achieved using atomic clean / invalidates
189 *  working outwards from L1 cache. This is done using Set/Way based cache
190 *  maintenance instructions.
191 *  The instruction cache can still be invalidated back to the point of
192 *  unification in a single instruction.
193 *
194 */
195ENTRY(v7_flush_kern_cache_all)
196 ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
197 THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
198	bl	v7_flush_dcache_all
199	mov	r0, #0
200	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
201	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)	@ I+BTB cache invalidate
202 ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
203 THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
204	ret	lr
205ENDPROC(v7_flush_kern_cache_all)
206
207 /*
208 *     v7_flush_kern_cache_louis(void)
209 *
210 *     Flush the data cache up to Level of Unification Inner Shareable.
211 *     Invalidate the I-cache to the point of unification.
212 */
213ENTRY(v7_flush_kern_cache_louis)
214 ARM(	stmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
215 THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
216	bl	v7_flush_dcache_louis
217	mov	r0, #0
218	ALT_SMP(mcr	p15, 0, r0, c7, c1, 0)	@ invalidate I-cache inner shareable
219	ALT_UP(mcr	p15, 0, r0, c7, c5, 0)	@ I+BTB cache invalidate
220 ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
221 THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
222	ret	lr
223ENDPROC(v7_flush_kern_cache_louis)
224
225/*
226 *	v7_flush_cache_all()
227 *
228 *	Flush all TLB entries in a particular address space
229 *
230 *	- mm    - mm_struct describing address space
231 */
232ENTRY(v7_flush_user_cache_all)
233	/*FALLTHROUGH*/
234
235/*
236 *	v7_flush_cache_range(start, end, flags)
237 *
238 *	Flush a range of TLB entries in the specified address space.
239 *
240 *	- start - start address (may not be aligned)
241 *	- end   - end address (exclusive, may not be aligned)
242 *	- flags	- vm_area_struct flags describing address space
243 *
244 *	It is assumed that:
245 *	- we have a VIPT cache.
246 */
247ENTRY(v7_flush_user_cache_range)
248	ret	lr
249ENDPROC(v7_flush_user_cache_all)
250ENDPROC(v7_flush_user_cache_range)
251
252/*
253 *	v7_coherent_kern_range(start,end)
254 *
255 *	Ensure that the I and D caches are coherent within specified
256 *	region.  This is typically used when code has been written to
257 *	a memory region, and will be executed.
258 *
259 *	- start   - virtual start address of region
260 *	- end     - virtual end address of region
261 *
262 *	It is assumed that:
263 *	- the Icache does not read data from the write buffer
264 */
265ENTRY(v7_coherent_kern_range)
266	/* FALLTHROUGH */
267
268/*
269 *	v7_coherent_user_range(start,end)
270 *
271 *	Ensure that the I and D caches are coherent within specified
272 *	region.  This is typically used when code has been written to
273 *	a memory region, and will be executed.
274 *
275 *	- start   - virtual start address of region
276 *	- end     - virtual end address of region
277 *
278 *	It is assumed that:
279 *	- the Icache does not read data from the write buffer
280 */
281ENTRY(v7_coherent_user_range)
282 UNWIND(.fnstart		)
283	dcache_line_size r2, r3
284	sub	r3, r2, #1
285	bic	r12, r0, r3
286#ifdef CONFIG_ARM_ERRATA_764369
287	ALT_SMP(W(dsb))
288	ALT_UP(W(nop))
289#endif
2901:
291 USER(	mcr	p15, 0, r12, c7, c11, 1	)	@ clean D line to the point of unification
292	add	r12, r12, r2
293	cmp	r12, r1
294	blo	1b
295	dsb	ishst
296#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
297	ldr	r3, =icache_size
298	ldr	r2, [r3, #0]
299#else
300	icache_line_size r2, r3
301#endif
302	sub	r3, r2, #1
303	bic	r12, r0, r3
3042:
305 USER(	mcr	p15, 0, r12, c7, c5, 1	)	@ invalidate I line
306	add	r12, r12, r2
307	cmp	r12, r1
308	blo	2b
309	mov	r0, #0
310	ALT_SMP(mcr	p15, 0, r0, c7, c1, 6)	@ invalidate BTB Inner Shareable
311	ALT_UP(mcr	p15, 0, r0, c7, c5, 6)	@ invalidate BTB
312	dsb	ishst
313	isb
314	ret	lr
315
316/*
317 * Fault handling for the cache operation above. If the virtual address in r0
318 * isn't mapped, fail with -EFAULT.
319 */
3209001:
321#ifdef CONFIG_ARM_ERRATA_775420
322	dsb
323#endif
324	mov	r0, #-EFAULT
325	ret	lr
326 UNWIND(.fnend		)
327ENDPROC(v7_coherent_kern_range)
328ENDPROC(v7_coherent_user_range)
329
330/*
331 *	v7_flush_kern_dcache_area(void *addr, size_t size)
332 *
333 *	Ensure that the data held in the page kaddr is written back
334 *	to the page in question.
335 *
336 *	- addr	- kernel address
337 *	- size	- region size
338 */
339ENTRY(v7_flush_kern_dcache_area)
340	dcache_line_size r2, r3
341	add	r1, r0, r1
342	sub	r3, r2, #1
343	bic	r0, r0, r3
344#ifdef CONFIG_ARM_ERRATA_764369
345	ALT_SMP(W(dsb))
346	ALT_UP(W(nop))
347#endif
3481:
349	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D line / unified line
350	add	r0, r0, r2
351	cmp	r0, r1
352	blo	1b
353	dsb	st
354	ret	lr
355ENDPROC(v7_flush_kern_dcache_area)
356
357/*
358 *	v7_dma_inv_range(start,end)
359 *
360 *	Invalidate the data cache within the specified region; we will
361 *	be performing a DMA operation in this region and we want to
362 *	purge old data in the cache.
363 *
364 *	- start   - virtual start address of region
365 *	- end     - virtual end address of region
366 */
367v7_dma_inv_range:
368	dcache_line_size r2, r3
369	sub	r3, r2, #1
370	tst	r0, r3
371	bic	r0, r0, r3
372#ifdef CONFIG_ARM_ERRATA_764369
373	ALT_SMP(W(dsb))
374	ALT_UP(W(nop))
375#endif
376	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line
377	addne	r0, r0, r2
378
379	tst	r1, r3
380	bic	r1, r1, r3
381	mcrne	p15, 0, r1, c7, c14, 1		@ clean & invalidate D / U line
382	cmp	r0, r1
3831:
384	mcrlo	p15, 0, r0, c7, c6, 1		@ invalidate D / U line
385	addlo	r0, r0, r2
386	cmplo	r0, r1
387	blo	1b
388	dsb	st
389	ret	lr
390ENDPROC(v7_dma_inv_range)
391
392/*
393 *	v7_dma_clean_range(start,end)
394 *	- start   - virtual start address of region
395 *	- end     - virtual end address of region
396 */
397v7_dma_clean_range:
398	dcache_line_size r2, r3
399	sub	r3, r2, #1
400	bic	r0, r0, r3
401#ifdef CONFIG_ARM_ERRATA_764369
402	ALT_SMP(W(dsb))
403	ALT_UP(W(nop))
404#endif
4051:
406	mcr	p15, 0, r0, c7, c10, 1		@ clean D / U line
407	add	r0, r0, r2
408	cmp	r0, r1
409	blo	1b
410	dsb	st
411	ret	lr
412ENDPROC(v7_dma_clean_range)
413
414/*
415 *	v7_dma_flush_range(start,end)
416 *	- start   - virtual start address of region
417 *	- end     - virtual end address of region
418 */
419ENTRY(v7_dma_flush_range)
420	dcache_line_size r2, r3
421	sub	r3, r2, #1
422	bic	r0, r0, r3
423#ifdef CONFIG_ARM_ERRATA_764369
424	ALT_SMP(W(dsb))
425	ALT_UP(W(nop))
426#endif
4271:
428	mcr	p15, 0, r0, c7, c14, 1		@ clean & invalidate D / U line
429	add	r0, r0, r2
430	cmp	r0, r1
431	blo	1b
432	dsb	st
433	ret	lr
434ENDPROC(v7_dma_flush_range)
435
436/*
437 *	dma_map_area(start, size, dir)
438 *	- start	- kernel virtual start address
439 *	- size	- size of region
440 *	- dir	- DMA direction
441 */
442ENTRY(v7_dma_map_area)
443	add	r1, r1, r0
444	teq	r2, #DMA_FROM_DEVICE
445	beq	v7_dma_inv_range
446	b	v7_dma_clean_range
447ENDPROC(v7_dma_map_area)
448
449/*
450 *	dma_unmap_area(start, size, dir)
451 *	- start	- kernel virtual start address
452 *	- size	- size of region
453 *	- dir	- DMA direction
454 */
455ENTRY(v7_dma_unmap_area)
456	add	r1, r1, r0
457	teq	r2, #DMA_TO_DEVICE
458	bne	v7_dma_inv_range
459	ret	lr
460ENDPROC(v7_dma_unmap_area)
461
462	__INITDATA
463
464	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
465	define_cache_functions v7
466
467	/* The Broadcom Brahma-B15 read-ahead cache requires some modifications
468	 * to the v7_cache_fns, we only override the ones we need
469	 */
470#ifndef CONFIG_CACHE_B15_RAC
471	globl_equ	b15_flush_kern_cache_all,	v7_flush_kern_cache_all
472#endif
473	globl_equ	b15_flush_icache_all,		v7_flush_icache_all
474	globl_equ	b15_flush_kern_cache_louis,	v7_flush_kern_cache_louis
475	globl_equ	b15_flush_user_cache_all,	v7_flush_user_cache_all
476	globl_equ	b15_flush_user_cache_range,	v7_flush_user_cache_range
477	globl_equ	b15_coherent_kern_range,	v7_coherent_kern_range
478	globl_equ	b15_coherent_user_range,	v7_coherent_user_range
479	globl_equ	b15_flush_kern_dcache_area,	v7_flush_kern_dcache_area
480
481	globl_equ	b15_dma_map_area,		v7_dma_map_area
482	globl_equ	b15_dma_unmap_area,		v7_dma_unmap_area
483	globl_equ	b15_dma_flush_range,		v7_dma_flush_range
484
485	define_cache_functions b15
486