1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1046a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 fman0 = &fman0; 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 ethernet3 = &enet3; 27 ethernet4 = &enet4; 28 ethernet5 = &enet5; 29 ethernet6 = &enet6; 30 ethernet7 = &enet7; 31 rtc1 = &ftm_alarm0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a72"; 41 reg = <0x0>; 42 clocks = <&clockgen 1 0>; 43 next-level-cache = <&l2>; 44 cpu-idle-states = <&CPU_PH20>; 45 #cooling-cells = <2>; 46 }; 47 48 cpu1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a72"; 51 reg = <0x1>; 52 clocks = <&clockgen 1 0>; 53 next-level-cache = <&l2>; 54 cpu-idle-states = <&CPU_PH20>; 55 #cooling-cells = <2>; 56 }; 57 58 cpu2: cpu@2 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a72"; 61 reg = <0x2>; 62 clocks = <&clockgen 1 0>; 63 next-level-cache = <&l2>; 64 cpu-idle-states = <&CPU_PH20>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a72"; 71 reg = <0x3>; 72 clocks = <&clockgen 1 0>; 73 next-level-cache = <&l2>; 74 cpu-idle-states = <&CPU_PH20>; 75 #cooling-cells = <2>; 76 }; 77 78 l2: l2-cache { 79 compatible = "cache"; 80 }; 81 }; 82 83 idle-states { 84 /* 85 * PSCI node is not added default, U-boot will add missing 86 * parts if it determines to use PSCI. 87 */ 88 entry-method = "psci"; 89 90 CPU_PH20: cpu-ph20 { 91 compatible = "arm,idle-state"; 92 idle-state-name = "PH20"; 93 arm,psci-suspend-param = <0x0>; 94 entry-latency-us = <1000>; 95 exit-latency-us = <1000>; 96 min-residency-us = <3000>; 97 }; 98 }; 99 100 memory@80000000 { 101 device_type = "memory"; 102 /* Real size will be filled by bootloader */ 103 reg = <0x0 0x80000000 0x0 0x0>; 104 }; 105 106 sysclk: sysclk { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <100000000>; 110 clock-output-names = "sysclk"; 111 }; 112 113 reboot { 114 compatible ="syscon-reboot"; 115 regmap = <&dcfg>; 116 offset = <0xb0>; 117 mask = <0x02>; 118 }; 119 120 thermal-zones { 121 ddr-controller { 122 polling-delay-passive = <1000>; 123 polling-delay = <5000>; 124 thermal-sensors = <&tmu 0>; 125 126 trips { 127 ddr-ctrler-alert { 128 temperature = <85000>; 129 hysteresis = <2000>; 130 type = "passive"; 131 }; 132 133 ddr-ctrler-crit { 134 temperature = <95000>; 135 hysteresis = <2000>; 136 type = "critical"; 137 }; 138 }; 139 }; 140 141 serdes { 142 polling-delay-passive = <1000>; 143 polling-delay = <5000>; 144 thermal-sensors = <&tmu 1>; 145 146 trips { 147 serdes-alert { 148 temperature = <85000>; 149 hysteresis = <2000>; 150 type = "passive"; 151 }; 152 153 serdes-crit { 154 temperature = <95000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 fman { 162 polling-delay-passive = <1000>; 163 polling-delay = <5000>; 164 thermal-sensors = <&tmu 2>; 165 166 trips { 167 fman-alert { 168 temperature = <85000>; 169 hysteresis = <2000>; 170 type = "passive"; 171 }; 172 173 fman-crit { 174 temperature = <95000>; 175 hysteresis = <2000>; 176 type = "critical"; 177 }; 178 }; 179 }; 180 181 core-cluster { 182 polling-delay-passive = <1000>; 183 polling-delay = <5000>; 184 thermal-sensors = <&tmu 3>; 185 186 trips { 187 core_cluster_alert: core-cluster-alert { 188 temperature = <85000>; 189 hysteresis = <2000>; 190 type = "passive"; 191 }; 192 193 core_cluster_crit: core-cluster-crit { 194 temperature = <95000>; 195 hysteresis = <2000>; 196 type = "critical"; 197 }; 198 }; 199 200 cooling-maps { 201 map0 { 202 trip = <&core_cluster_alert>; 203 cooling-device = 204 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 205 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 208 }; 209 }; 210 }; 211 212 sec { 213 polling-delay-passive = <1000>; 214 polling-delay = <5000>; 215 thermal-sensors = <&tmu 4>; 216 217 trips { 218 sec-alert { 219 temperature = <85000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 224 sec-crit { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "critical"; 228 }; 229 }; 230 }; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 236 IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 238 IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 240 IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 242 IRQ_TYPE_LEVEL_LOW)>; 243 }; 244 245 pmu { 246 compatible = "arm,cortex-a72-pmu"; 247 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 251 interrupt-affinity = <&cpu0>, 252 <&cpu1>, 253 <&cpu2>, 254 <&cpu3>; 255 }; 256 257 gic: interrupt-controller@1400000 { 258 compatible = "arm,gic-400"; 259 #interrupt-cells = <3>; 260 interrupt-controller; 261 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 262 <0x0 0x1420000 0 0x20000>, /* GICC */ 263 <0x0 0x1440000 0 0x20000>, /* GICH */ 264 <0x0 0x1460000 0 0x20000>; /* GICV */ 265 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 266 IRQ_TYPE_LEVEL_LOW)>; 267 }; 268 269 soc: soc { 270 compatible = "simple-bus"; 271 #address-cells = <2>; 272 #size-cells = <2>; 273 ranges; 274 275 ddr: memory-controller@1080000 { 276 compatible = "fsl,qoriq-memory-controller"; 277 reg = <0x0 0x1080000 0x0 0x1000>; 278 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 279 big-endian; 280 }; 281 282 ifc: ifc@1530000 { 283 compatible = "fsl,ifc", "simple-bus"; 284 reg = <0x0 0x1530000 0x0 0x10000>; 285 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 286 status = "disabled"; 287 }; 288 289 qspi: spi@1550000 { 290 compatible = "fsl,ls1021a-qspi"; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 reg = <0x0 0x1550000 0x0 0x10000>, 294 <0x0 0x40000000 0x0 0x10000000>; 295 reg-names = "QuadSPI", "QuadSPI-memory"; 296 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 297 clock-names = "qspi_en", "qspi"; 298 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 299 status = "disabled"; 300 }; 301 302 esdhc: esdhc@1560000 { 303 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 304 reg = <0x0 0x1560000 0x0 0x10000>; 305 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clockgen 2 1>; 307 voltage-ranges = <1800 1800 3300 3300>; 308 sdhci,auto-cmd12; 309 big-endian; 310 bus-width = <4>; 311 }; 312 313 scfg: scfg@1570000 { 314 compatible = "fsl,ls1046a-scfg", "syscon"; 315 reg = <0x0 0x1570000 0x0 0x10000>; 316 big-endian; 317 }; 318 319 crypto: crypto@1700000 { 320 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 321 "fsl,sec-v4.0"; 322 fsl,sec-era = <8>; 323 #address-cells = <1>; 324 #size-cells = <1>; 325 ranges = <0x0 0x00 0x1700000 0x100000>; 326 reg = <0x00 0x1700000 0x0 0x100000>; 327 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 328 dma-coherent; 329 330 sec_jr0: jr@10000 { 331 compatible = "fsl,sec-v5.4-job-ring", 332 "fsl,sec-v5.0-job-ring", 333 "fsl,sec-v4.0-job-ring"; 334 reg = <0x10000 0x10000>; 335 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 336 }; 337 338 sec_jr1: jr@20000 { 339 compatible = "fsl,sec-v5.4-job-ring", 340 "fsl,sec-v5.0-job-ring", 341 "fsl,sec-v4.0-job-ring"; 342 reg = <0x20000 0x10000>; 343 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 344 }; 345 346 sec_jr2: jr@30000 { 347 compatible = "fsl,sec-v5.4-job-ring", 348 "fsl,sec-v5.0-job-ring", 349 "fsl,sec-v4.0-job-ring"; 350 reg = <0x30000 0x10000>; 351 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 352 }; 353 354 sec_jr3: jr@40000 { 355 compatible = "fsl,sec-v5.4-job-ring", 356 "fsl,sec-v5.0-job-ring", 357 "fsl,sec-v4.0-job-ring"; 358 reg = <0x40000 0x10000>; 359 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 360 }; 361 }; 362 363 qman: qman@1880000 { 364 compatible = "fsl,qman"; 365 reg = <0x0 0x1880000 0x0 0x10000>; 366 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 367 memory-region = <&qman_fqd &qman_pfdr>; 368 369 }; 370 371 bman: bman@1890000 { 372 compatible = "fsl,bman"; 373 reg = <0x0 0x1890000 0x0 0x10000>; 374 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 375 memory-region = <&bman_fbpr>; 376 377 }; 378 379 qportals: qman-portals@500000000 { 380 ranges = <0x0 0x5 0x00000000 0x8000000>; 381 }; 382 383 bportals: bman-portals@508000000 { 384 ranges = <0x0 0x5 0x08000000 0x8000000>; 385 }; 386 387 dcfg: dcfg@1ee0000 { 388 compatible = "fsl,ls1046a-dcfg", "syscon"; 389 reg = <0x0 0x1ee0000 0x0 0x1000>; 390 big-endian; 391 }; 392 393 clockgen: clocking@1ee1000 { 394 compatible = "fsl,ls1046a-clockgen"; 395 reg = <0x0 0x1ee1000 0x0 0x1000>; 396 #clock-cells = <2>; 397 clocks = <&sysclk>; 398 }; 399 400 tmu: tmu@1f00000 { 401 compatible = "fsl,qoriq-tmu"; 402 reg = <0x0 0x1f00000 0x0 0x10000>; 403 interrupts = <0 33 0x4>; 404 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 405 fsl,tmu-calibration = 406 /* Calibration data group 1 */ 407 <0x00000000 0x00000026 408 0x00000001 0x0000002d 409 0x00000002 0x00000032 410 0x00000003 0x00000039 411 0x00000004 0x0000003f 412 0x00000005 0x00000046 413 0x00000006 0x0000004d 414 0x00000007 0x00000054 415 0x00000008 0x0000005a 416 0x00000009 0x00000061 417 0x0000000a 0x0000006a 418 0x0000000b 0x00000071 419 /* Calibration data group 2 */ 420 0x00010000 0x00000025 421 0x00010001 0x0000002c 422 0x00010002 0x00000035 423 0x00010003 0x0000003d 424 0x00010004 0x00000045 425 0x00010005 0x0000004e 426 0x00010006 0x00000057 427 0x00010007 0x00000061 428 0x00010008 0x0000006b 429 0x00010009 0x00000076 430 /* Calibration data group 3 */ 431 0x00020000 0x00000029 432 0x00020001 0x00000033 433 0x00020002 0x0000003d 434 0x00020003 0x00000049 435 0x00020004 0x00000056 436 0x00020005 0x00000061 437 0x00020006 0x0000006d 438 /* Calibration data group 4 */ 439 0x00030000 0x00000021 440 0x00030001 0x0000002a 441 0x00030002 0x0000003c 442 0x00030003 0x0000004e>; 443 big-endian; 444 #thermal-sensor-cells = <1>; 445 }; 446 447 dspi: spi@2100000 { 448 compatible = "fsl,ls1021a-v1.0-dspi"; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 reg = <0x0 0x2100000 0x0 0x10000>; 452 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 453 clock-names = "dspi"; 454 clocks = <&clockgen 4 1>; 455 spi-num-chipselects = <5>; 456 big-endian; 457 status = "disabled"; 458 }; 459 460 i2c0: i2c@2180000 { 461 compatible = "fsl,vf610-i2c"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x0 0x2180000 0x0 0x10000>; 465 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clockgen 4 1>; 467 dmas = <&edma0 1 39>, 468 <&edma0 1 38>; 469 dma-names = "tx", "rx"; 470 status = "disabled"; 471 }; 472 473 i2c1: i2c@2190000 { 474 compatible = "fsl,vf610-i2c"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <0x0 0x2190000 0x0 0x10000>; 478 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clockgen 4 1>; 480 status = "disabled"; 481 }; 482 483 i2c2: i2c@21a0000 { 484 compatible = "fsl,vf610-i2c"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 reg = <0x0 0x21a0000 0x0 0x10000>; 488 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clockgen 4 1>; 490 status = "disabled"; 491 }; 492 493 i2c3: i2c@21b0000 { 494 compatible = "fsl,vf610-i2c"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0x0 0x21b0000 0x0 0x10000>; 498 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clockgen 4 1>; 500 status = "disabled"; 501 }; 502 503 duart0: serial@21c0500 { 504 compatible = "fsl,ns16550", "ns16550a"; 505 reg = <0x00 0x21c0500 0x0 0x100>; 506 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clockgen 4 1>; 508 status = "disabled"; 509 }; 510 511 duart1: serial@21c0600 { 512 compatible = "fsl,ns16550", "ns16550a"; 513 reg = <0x00 0x21c0600 0x0 0x100>; 514 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clockgen 4 1>; 516 status = "disabled"; 517 }; 518 519 duart2: serial@21d0500 { 520 compatible = "fsl,ns16550", "ns16550a"; 521 reg = <0x0 0x21d0500 0x0 0x100>; 522 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clockgen 4 1>; 524 status = "disabled"; 525 }; 526 527 duart3: serial@21d0600 { 528 compatible = "fsl,ns16550", "ns16550a"; 529 reg = <0x0 0x21d0600 0x0 0x100>; 530 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clockgen 4 1>; 532 status = "disabled"; 533 }; 534 535 gpio0: gpio@2300000 { 536 compatible = "fsl,qoriq-gpio"; 537 reg = <0x0 0x2300000 0x0 0x10000>; 538 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 }; 544 545 gpio1: gpio@2310000 { 546 compatible = "fsl,qoriq-gpio"; 547 reg = <0x0 0x2310000 0x0 0x10000>; 548 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 555 gpio2: gpio@2320000 { 556 compatible = "fsl,qoriq-gpio"; 557 reg = <0x0 0x2320000 0x0 0x10000>; 558 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 565 gpio3: gpio@2330000 { 566 compatible = "fsl,qoriq-gpio"; 567 reg = <0x0 0x2330000 0x0 0x10000>; 568 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 }; 574 575 lpuart0: serial@2950000 { 576 compatible = "fsl,ls1021a-lpuart"; 577 reg = <0x0 0x2950000 0x0 0x1000>; 578 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clockgen 4 0>; 580 clock-names = "ipg"; 581 status = "disabled"; 582 }; 583 584 lpuart1: serial@2960000 { 585 compatible = "fsl,ls1021a-lpuart"; 586 reg = <0x0 0x2960000 0x0 0x1000>; 587 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clockgen 4 1>; 589 clock-names = "ipg"; 590 status = "disabled"; 591 }; 592 593 lpuart2: serial@2970000 { 594 compatible = "fsl,ls1021a-lpuart"; 595 reg = <0x0 0x2970000 0x0 0x1000>; 596 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&clockgen 4 1>; 598 clock-names = "ipg"; 599 status = "disabled"; 600 }; 601 602 lpuart3: serial@2980000 { 603 compatible = "fsl,ls1021a-lpuart"; 604 reg = <0x0 0x2980000 0x0 0x1000>; 605 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clockgen 4 1>; 607 clock-names = "ipg"; 608 status = "disabled"; 609 }; 610 611 lpuart4: serial@2990000 { 612 compatible = "fsl,ls1021a-lpuart"; 613 reg = <0x0 0x2990000 0x0 0x1000>; 614 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clockgen 4 1>; 616 clock-names = "ipg"; 617 status = "disabled"; 618 }; 619 620 lpuart5: serial@29a0000 { 621 compatible = "fsl,ls1021a-lpuart"; 622 reg = <0x0 0x29a0000 0x0 0x1000>; 623 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clockgen 4 1>; 625 clock-names = "ipg"; 626 status = "disabled"; 627 }; 628 629 wdog0: watchdog@2ad0000 { 630 compatible = "fsl,imx21-wdt"; 631 reg = <0x0 0x2ad0000 0x0 0x10000>; 632 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&clockgen 4 1>; 634 big-endian; 635 }; 636 637 edma0: edma@2c00000 { 638 #dma-cells = <2>; 639 compatible = "fsl,vf610-edma"; 640 reg = <0x0 0x2c00000 0x0 0x10000>, 641 <0x0 0x2c10000 0x0 0x10000>, 642 <0x0 0x2c20000 0x0 0x10000>; 643 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "edma-tx", "edma-err"; 646 dma-channels = <32>; 647 big-endian; 648 clock-names = "dmamux0", "dmamux1"; 649 clocks = <&clockgen 4 1>, 650 <&clockgen 4 1>; 651 }; 652 653 usb0: usb@2f00000 { 654 compatible = "snps,dwc3"; 655 reg = <0x0 0x2f00000 0x0 0x10000>; 656 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 657 dr_mode = "host"; 658 snps,quirk-frame-length-adjustment = <0x20>; 659 snps,dis_rxdet_inp3_quirk; 660 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 661 }; 662 663 usb1: usb@3000000 { 664 compatible = "snps,dwc3"; 665 reg = <0x0 0x3000000 0x0 0x10000>; 666 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 667 dr_mode = "host"; 668 snps,quirk-frame-length-adjustment = <0x20>; 669 snps,dis_rxdet_inp3_quirk; 670 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 671 }; 672 673 usb2: usb@3100000 { 674 compatible = "snps,dwc3"; 675 reg = <0x0 0x3100000 0x0 0x10000>; 676 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 677 dr_mode = "host"; 678 snps,quirk-frame-length-adjustment = <0x20>; 679 snps,dis_rxdet_inp3_quirk; 680 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 681 }; 682 683 sata: sata@3200000 { 684 compatible = "fsl,ls1046a-ahci"; 685 reg = <0x0 0x3200000 0x0 0x10000>, 686 <0x0 0x20140520 0x0 0x4>; 687 reg-names = "ahci", "sata-ecc"; 688 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clockgen 4 1>; 690 }; 691 692 msi1: msi-controller@1580000 { 693 compatible = "fsl,ls1046a-msi"; 694 msi-controller; 695 reg = <0x0 0x1580000 0x0 0x10000>; 696 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 700 }; 701 702 msi2: msi-controller@1590000 { 703 compatible = "fsl,ls1046a-msi"; 704 msi-controller; 705 reg = <0x0 0x1590000 0x0 0x10000>; 706 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 710 }; 711 712 msi3: msi-controller@15a0000 { 713 compatible = "fsl,ls1046a-msi"; 714 msi-controller; 715 reg = <0x0 0x15a0000 0x0 0x10000>; 716 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 720 }; 721 722 pcie1: pcie@3400000 { 723 compatible = "fsl,ls1046a-pcie"; 724 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 725 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 726 reg-names = "regs", "config"; 727 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 728 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 729 interrupt-names = "aer", "pme"; 730 #address-cells = <3>; 731 #size-cells = <2>; 732 device_type = "pci"; 733 dma-coherent; 734 num-viewport = <8>; 735 bus-range = <0x0 0xff>; 736 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 737 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 738 msi-parent = <&msi1>, <&msi2>, <&msi3>; 739 #interrupt-cells = <1>; 740 interrupt-map-mask = <0 0 0 7>; 741 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 742 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 743 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 744 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 745 status = "disabled"; 746 }; 747 748 pcie_ep1: pcie_ep@3400000 { 749 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 750 reg = <0x00 0x03400000 0x0 0x00100000 751 0x40 0x00000000 0x8 0x00000000>; 752 reg-names = "regs", "addr_space"; 753 num-ib-windows = <6>; 754 num-ob-windows = <8>; 755 status = "disabled"; 756 }; 757 758 pcie2: pcie@3500000 { 759 compatible = "fsl,ls1046a-pcie"; 760 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 761 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 762 reg-names = "regs", "config"; 763 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 764 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 765 interrupt-names = "aer", "pme"; 766 #address-cells = <3>; 767 #size-cells = <2>; 768 device_type = "pci"; 769 dma-coherent; 770 num-viewport = <8>; 771 bus-range = <0x0 0xff>; 772 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 773 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 774 msi-parent = <&msi2>, <&msi3>, <&msi1>; 775 #interrupt-cells = <1>; 776 interrupt-map-mask = <0 0 0 7>; 777 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 778 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 779 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 780 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 781 status = "disabled"; 782 }; 783 784 pcie_ep2: pcie_ep@3500000 { 785 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 786 reg = <0x00 0x03500000 0x0 0x00100000 787 0x48 0x00000000 0x8 0x00000000>; 788 reg-names = "regs", "addr_space"; 789 num-ib-windows = <6>; 790 num-ob-windows = <8>; 791 status = "disabled"; 792 }; 793 794 pcie3: pcie@3600000 { 795 compatible = "fsl,ls1046a-pcie"; 796 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 797 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 798 reg-names = "regs", "config"; 799 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 800 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 801 interrupt-names = "aer", "pme"; 802 #address-cells = <3>; 803 #size-cells = <2>; 804 device_type = "pci"; 805 dma-coherent; 806 num-viewport = <8>; 807 bus-range = <0x0 0xff>; 808 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 809 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 810 msi-parent = <&msi3>, <&msi1>, <&msi2>; 811 #interrupt-cells = <1>; 812 interrupt-map-mask = <0 0 0 7>; 813 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 814 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 815 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 816 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 817 status = "disabled"; 818 }; 819 820 pcie_ep3: pcie_ep@3600000 { 821 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 822 reg = <0x00 0x03600000 0x0 0x00100000 823 0x50 0x00000000 0x8 0x00000000>; 824 reg-names = "regs", "addr_space"; 825 num-ib-windows = <6>; 826 num-ob-windows = <8>; 827 status = "disabled"; 828 }; 829 830 qdma: dma-controller@8380000 { 831 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 832 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 833 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 834 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 835 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "qdma-error", "qdma-queue0", 841 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 842 dma-channels = <8>; 843 block-number = <1>; 844 block-offset = <0x10000>; 845 fsl,dma-queues = <2>; 846 status-sizes = <64>; 847 queue-sizes = <64 64>; 848 big-endian; 849 }; 850 851 rcpm: power-controller@1ee2140 { 852 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 853 reg = <0x0 0x1ee2140 0x0 0x4>; 854 #fsl,rcpm-wakeup-cells = <1>; 855 }; 856 857 ftm_alarm0: timer@29d0000 { 858 compatible = "fsl,ls1046a-ftm-alarm"; 859 reg = <0x0 0x29d0000 0x0 0x10000>; 860 fsl,rcpm-wakeup = <&rcpm 0x20000>; 861 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 862 big-endian; 863 }; 864 }; 865 866 reserved-memory { 867 #address-cells = <2>; 868 #size-cells = <2>; 869 ranges; 870 871 bman_fbpr: bman-fbpr { 872 compatible = "shared-dma-pool"; 873 size = <0 0x1000000>; 874 alignment = <0 0x1000000>; 875 no-map; 876 }; 877 878 qman_fqd: qman-fqd { 879 compatible = "shared-dma-pool"; 880 size = <0 0x800000>; 881 alignment = <0 0x800000>; 882 no-map; 883 }; 884 885 qman_pfdr: qman-pfdr { 886 compatible = "shared-dma-pool"; 887 size = <0 0x2000000>; 888 alignment = <0 0x2000000>; 889 no-map; 890 }; 891 }; 892 893 firmware { 894 optee { 895 compatible = "linaro,optee-tz"; 896 method = "smc"; 897 }; 898 }; 899}; 900 901#include "qoriq-qman-portals.dtsi" 902#include "qoriq-bman-portals.dtsi" 903