1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 qcom,msm-id = <292 0x0>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 memory { 22 device_type = "memory"; 23 /* We expect the bootloader to fill in the reg */ 24 reg = <0 0 0 0>; 25 }; 26 27 reserved-memory { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 hyp_mem: memory@85800000 { 33 reg = <0x0 0x85800000 0x0 0x600000>; 34 no-map; 35 }; 36 37 xbl_mem: memory@85e00000 { 38 reg = <0x0 0x85e00000 0x0 0x100000>; 39 no-map; 40 }; 41 42 smem_mem: smem-mem@86000000 { 43 reg = <0x0 0x86000000 0x0 0x200000>; 44 no-map; 45 }; 46 47 tz_mem: memory@86200000 { 48 reg = <0x0 0x86200000 0x0 0x2d00000>; 49 no-map; 50 }; 51 52 rmtfs_mem: memory@88f00000 { 53 compatible = "qcom,rmtfs-mem"; 54 reg = <0x0 0x88f00000 0x0 0x200000>; 55 no-map; 56 57 qcom,client-id = <1>; 58 qcom,vmid = <15>; 59 }; 60 61 spss_mem: memory@8ab00000 { 62 reg = <0x0 0x8ab00000 0x0 0x700000>; 63 no-map; 64 }; 65 66 adsp_mem: memory@8b200000 { 67 reg = <0x0 0x8b200000 0x0 0x1a00000>; 68 no-map; 69 }; 70 71 mpss_mem: memory@8cc00000 { 72 reg = <0x0 0x8cc00000 0x0 0x7000000>; 73 no-map; 74 }; 75 76 venus_mem: memory@93c00000 { 77 reg = <0x0 0x93c00000 0x0 0x500000>; 78 no-map; 79 }; 80 81 mba_mem: memory@94100000 { 82 reg = <0x0 0x94100000 0x0 0x200000>; 83 no-map; 84 }; 85 86 slpi_mem: memory@94300000 { 87 reg = <0x0 0x94300000 0x0 0xf00000>; 88 no-map; 89 }; 90 91 ipa_fw_mem: memory@95200000 { 92 reg = <0x0 0x95200000 0x0 0x10000>; 93 no-map; 94 }; 95 96 ipa_gsi_mem: memory@95210000 { 97 reg = <0x0 0x95210000 0x0 0x5000>; 98 no-map; 99 }; 100 101 gpu_mem: memory@95600000 { 102 reg = <0x0 0x95600000 0x0 0x100000>; 103 no-map; 104 }; 105 106 wlan_msa_mem: memory@95700000 { 107 reg = <0x0 0x95700000 0x0 0x100000>; 108 no-map; 109 }; 110 }; 111 112 clocks { 113 xo: xo-board { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <19200000>; 117 clock-output-names = "xo_board"; 118 }; 119 120 sleep_clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <32764>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo280"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 137 next-level-cache = <&L2_0>; 138 L2_0: l2-cache { 139 compatible = "arm,arch-cache"; 140 cache-level = <2>; 141 }; 142 L1_I_0: l1-icache { 143 compatible = "arm,arch-cache"; 144 }; 145 L1_D_0: l1-dcache { 146 compatible = "arm,arch-cache"; 147 }; 148 }; 149 150 CPU1: cpu@1 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo280"; 153 reg = <0x0 0x1>; 154 enable-method = "psci"; 155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 156 next-level-cache = <&L2_0>; 157 L1_I_1: l1-icache { 158 compatible = "arm,arch-cache"; 159 }; 160 L1_D_1: l1-dcache { 161 compatible = "arm,arch-cache"; 162 }; 163 }; 164 165 CPU2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo280"; 168 reg = <0x0 0x2>; 169 enable-method = "psci"; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 171 next-level-cache = <&L2_0>; 172 L1_I_2: l1-icache { 173 compatible = "arm,arch-cache"; 174 }; 175 L1_D_2: l1-dcache { 176 compatible = "arm,arch-cache"; 177 }; 178 }; 179 180 CPU3: cpu@3 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo280"; 183 reg = <0x0 0x3>; 184 enable-method = "psci"; 185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 186 next-level-cache = <&L2_0>; 187 L1_I_3: l1-icache { 188 compatible = "arm,arch-cache"; 189 }; 190 L1_D_3: l1-dcache { 191 compatible = "arm,arch-cache"; 192 }; 193 }; 194 195 CPU4: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo280"; 198 reg = <0x0 0x100>; 199 enable-method = "psci"; 200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 201 next-level-cache = <&L2_1>; 202 L2_1: l2-cache { 203 compatible = "arm,arch-cache"; 204 cache-level = <2>; 205 }; 206 L1_I_100: l1-icache { 207 compatible = "arm,arch-cache"; 208 }; 209 L1_D_100: l1-dcache { 210 compatible = "arm,arch-cache"; 211 }; 212 }; 213 214 CPU5: cpu@101 { 215 device_type = "cpu"; 216 compatible = "qcom,kryo280"; 217 reg = <0x0 0x101>; 218 enable-method = "psci"; 219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 220 next-level-cache = <&L2_1>; 221 L1_I_101: l1-icache { 222 compatible = "arm,arch-cache"; 223 }; 224 L1_D_101: l1-dcache { 225 compatible = "arm,arch-cache"; 226 }; 227 }; 228 229 CPU6: cpu@102 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo280"; 232 reg = <0x0 0x102>; 233 enable-method = "psci"; 234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 235 next-level-cache = <&L2_1>; 236 L1_I_102: l1-icache { 237 compatible = "arm,arch-cache"; 238 }; 239 L1_D_102: l1-dcache { 240 compatible = "arm,arch-cache"; 241 }; 242 }; 243 244 CPU7: cpu@103 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo280"; 247 reg = <0x0 0x103>; 248 enable-method = "psci"; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 250 next-level-cache = <&L2_1>; 251 L1_I_103: l1-icache { 252 compatible = "arm,arch-cache"; 253 }; 254 L1_D_103: l1-dcache { 255 compatible = "arm,arch-cache"; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&CPU0>; 263 }; 264 265 core1 { 266 cpu = <&CPU1>; 267 }; 268 269 core2 { 270 cpu = <&CPU2>; 271 }; 272 273 core3 { 274 cpu = <&CPU3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&CPU4>; 281 }; 282 283 core1 { 284 cpu = <&CPU5>; 285 }; 286 287 core2 { 288 cpu = <&CPU6>; 289 }; 290 291 core3 { 292 cpu = <&CPU7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "little-retention"; 303 /* CPU Retention (C2D), L2 Active */ 304 arm,psci-suspend-param = <0x00000002>; 305 entry-latency-us = <81>; 306 exit-latency-us = <86>; 307 min-residency-us = <504>; 308 }; 309 310 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "little-power-collapse"; 313 /* CPU + L2 Power Collapse (C3, D4) */ 314 arm,psci-suspend-param = <0x40000003>; 315 entry-latency-us = <814>; 316 exit-latency-us = <4562>; 317 min-residency-us = <9183>; 318 local-timer-stop; 319 }; 320 321 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "big-retention"; 324 /* CPU Retention (C2D), L2 Active */ 325 arm,psci-suspend-param = <0x00000002>; 326 entry-latency-us = <79>; 327 exit-latency-us = <82>; 328 min-residency-us = <1302>; 329 }; 330 331 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "big-power-collapse"; 334 /* CPU + L2 Power Collapse (C3, D4) */ 335 arm,psci-suspend-param = <0x40000003>; 336 entry-latency-us = <724>; 337 exit-latency-us = <2027>; 338 min-residency-us = <9419>; 339 local-timer-stop; 340 }; 341 }; 342 }; 343 344 firmware { 345 scm { 346 compatible = "qcom,scm-msm8998", "qcom,scm"; 347 }; 348 }; 349 350 tcsr_mutex: hwlock { 351 compatible = "qcom,tcsr-mutex"; 352 syscon = <&tcsr_mutex_regs 0 0x1000>; 353 #hwlock-cells = <1>; 354 }; 355 356 psci { 357 compatible = "arm,psci-1.0"; 358 method = "smc"; 359 }; 360 361 rpm-glink { 362 compatible = "qcom,glink-rpm"; 363 364 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 365 qcom,rpm-msg-ram = <&rpm_msg_ram>; 366 mboxes = <&apcs_glb 0>; 367 368 rpm_requests: rpm-requests { 369 compatible = "qcom,rpm-msm8998"; 370 qcom,glink-channels = "rpm_requests"; 371 372 rpmcc: clock-controller { 373 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 374 #clock-cells = <1>; 375 }; 376 377 rpmpd: power-controller { 378 compatible = "qcom,msm8998-rpmpd"; 379 #power-domain-cells = <1>; 380 operating-points-v2 = <&rpmpd_opp_table>; 381 382 rpmpd_opp_table: opp-table { 383 compatible = "operating-points-v2"; 384 385 rpmpd_opp_ret: opp1 { 386 opp-level = <16>; 387 }; 388 389 rpmpd_opp_ret_plus: opp2 { 390 opp-level = <32>; 391 }; 392 393 rpmpd_opp_min_svs: opp3 { 394 opp-level = <48>; 395 }; 396 397 rpmpd_opp_low_svs: opp4 { 398 opp-level = <64>; 399 }; 400 401 rpmpd_opp_svs: opp5 { 402 opp-level = <128>; 403 }; 404 405 rpmpd_opp_svs_plus: opp6 { 406 opp-level = <192>; 407 }; 408 409 rpmpd_opp_nom: opp7 { 410 opp-level = <256>; 411 }; 412 413 rpmpd_opp_nom_plus: opp8 { 414 opp-level = <320>; 415 }; 416 417 rpmpd_opp_turbo: opp9 { 418 opp-level = <384>; 419 }; 420 421 rpmpd_opp_turbo_plus: opp10 { 422 opp-level = <512>; 423 }; 424 }; 425 }; 426 }; 427 }; 428 429 smem { 430 compatible = "qcom,smem"; 431 memory-region = <&smem_mem>; 432 hwlocks = <&tcsr_mutex 3>; 433 }; 434 435 smp2p-lpass { 436 compatible = "qcom,smp2p"; 437 qcom,smem = <443>, <429>; 438 439 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 440 441 mboxes = <&apcs_glb 10>; 442 443 qcom,local-pid = <0>; 444 qcom,remote-pid = <2>; 445 446 adsp_smp2p_out: master-kernel { 447 qcom,entry-name = "master-kernel"; 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 adsp_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smp2p-mpss { 460 compatible = "qcom,smp2p"; 461 qcom,smem = <435>, <428>; 462 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 463 mboxes = <&apcs_glb 14>; 464 qcom,local-pid = <0>; 465 qcom,remote-pid = <1>; 466 467 modem_smp2p_out: master-kernel { 468 qcom,entry-name = "master-kernel"; 469 #qcom,smem-state-cells = <1>; 470 }; 471 472 modem_smp2p_in: slave-kernel { 473 qcom,entry-name = "slave-kernel"; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 }; 477 }; 478 479 smp2p-slpi { 480 compatible = "qcom,smp2p"; 481 qcom,smem = <481>, <430>; 482 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 483 mboxes = <&apcs_glb 26>; 484 qcom,local-pid = <0>; 485 qcom,remote-pid = <3>; 486 487 slpi_smp2p_out: master-kernel { 488 qcom,entry-name = "master-kernel"; 489 #qcom,smem-state-cells = <1>; 490 }; 491 492 slpi_smp2p_in: slave-kernel { 493 qcom,entry-name = "slave-kernel"; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 }; 497 }; 498 499 thermal-zones { 500 cpu0-thermal { 501 polling-delay-passive = <250>; 502 polling-delay = <1000>; 503 504 thermal-sensors = <&tsens0 1>; 505 506 trips { 507 cpu0_alert0: trip-point0 { 508 temperature = <75000>; 509 hysteresis = <2000>; 510 type = "passive"; 511 }; 512 513 cpu0_crit: cpu_crit { 514 temperature = <110000>; 515 hysteresis = <2000>; 516 type = "critical"; 517 }; 518 }; 519 }; 520 521 cpu1-thermal { 522 polling-delay-passive = <250>; 523 polling-delay = <1000>; 524 525 thermal-sensors = <&tsens0 2>; 526 527 trips { 528 cpu1_alert0: trip-point0 { 529 temperature = <75000>; 530 hysteresis = <2000>; 531 type = "passive"; 532 }; 533 534 cpu1_crit: cpu_crit { 535 temperature = <110000>; 536 hysteresis = <2000>; 537 type = "critical"; 538 }; 539 }; 540 }; 541 542 cpu2-thermal { 543 polling-delay-passive = <250>; 544 polling-delay = <1000>; 545 546 thermal-sensors = <&tsens0 3>; 547 548 trips { 549 cpu2_alert0: trip-point0 { 550 temperature = <75000>; 551 hysteresis = <2000>; 552 type = "passive"; 553 }; 554 555 cpu2_crit: cpu_crit { 556 temperature = <110000>; 557 hysteresis = <2000>; 558 type = "critical"; 559 }; 560 }; 561 }; 562 563 cpu3-thermal { 564 polling-delay-passive = <250>; 565 polling-delay = <1000>; 566 567 thermal-sensors = <&tsens0 4>; 568 569 trips { 570 cpu3_alert0: trip-point0 { 571 temperature = <75000>; 572 hysteresis = <2000>; 573 type = "passive"; 574 }; 575 576 cpu3_crit: cpu_crit { 577 temperature = <110000>; 578 hysteresis = <2000>; 579 type = "critical"; 580 }; 581 }; 582 }; 583 584 cpu4-thermal { 585 polling-delay-passive = <250>; 586 polling-delay = <1000>; 587 588 thermal-sensors = <&tsens0 7>; 589 590 trips { 591 cpu4_alert0: trip-point0 { 592 temperature = <75000>; 593 hysteresis = <2000>; 594 type = "passive"; 595 }; 596 597 cpu4_crit: cpu_crit { 598 temperature = <110000>; 599 hysteresis = <2000>; 600 type = "critical"; 601 }; 602 }; 603 }; 604 605 cpu5-thermal { 606 polling-delay-passive = <250>; 607 polling-delay = <1000>; 608 609 thermal-sensors = <&tsens0 8>; 610 611 trips { 612 cpu5_alert0: trip-point0 { 613 temperature = <75000>; 614 hysteresis = <2000>; 615 type = "passive"; 616 }; 617 618 cpu5_crit: cpu_crit { 619 temperature = <110000>; 620 hysteresis = <2000>; 621 type = "critical"; 622 }; 623 }; 624 }; 625 626 cpu6-thermal { 627 polling-delay-passive = <250>; 628 polling-delay = <1000>; 629 630 thermal-sensors = <&tsens0 9>; 631 632 trips { 633 cpu6_alert0: trip-point0 { 634 temperature = <75000>; 635 hysteresis = <2000>; 636 type = "passive"; 637 }; 638 639 cpu6_crit: cpu_crit { 640 temperature = <110000>; 641 hysteresis = <2000>; 642 type = "critical"; 643 }; 644 }; 645 }; 646 647 cpu7-thermal { 648 polling-delay-passive = <250>; 649 polling-delay = <1000>; 650 651 thermal-sensors = <&tsens0 10>; 652 653 trips { 654 cpu7_alert0: trip-point0 { 655 temperature = <75000>; 656 hysteresis = <2000>; 657 type = "passive"; 658 }; 659 660 cpu7_crit: cpu_crit { 661 temperature = <110000>; 662 hysteresis = <2000>; 663 type = "critical"; 664 }; 665 }; 666 }; 667 668 gpu-thermal-bottom { 669 polling-delay-passive = <250>; 670 polling-delay = <1000>; 671 672 thermal-sensors = <&tsens0 12>; 673 674 trips { 675 gpu1_alert0: trip-point0 { 676 temperature = <90000>; 677 hysteresis = <2000>; 678 type = "hot"; 679 }; 680 }; 681 }; 682 683 gpu-thermal-top { 684 polling-delay-passive = <250>; 685 polling-delay = <1000>; 686 687 thermal-sensors = <&tsens0 13>; 688 689 trips { 690 gpu2_alert0: trip-point0 { 691 temperature = <90000>; 692 hysteresis = <2000>; 693 type = "hot"; 694 }; 695 }; 696 }; 697 698 clust0-mhm-thermal { 699 polling-delay-passive = <250>; 700 polling-delay = <1000>; 701 702 thermal-sensors = <&tsens0 5>; 703 704 trips { 705 cluster0_mhm_alert0: trip-point0 { 706 temperature = <90000>; 707 hysteresis = <2000>; 708 type = "hot"; 709 }; 710 }; 711 }; 712 713 clust1-mhm-thermal { 714 polling-delay-passive = <250>; 715 polling-delay = <1000>; 716 717 thermal-sensors = <&tsens0 6>; 718 719 trips { 720 cluster1_mhm_alert0: trip-point0 { 721 temperature = <90000>; 722 hysteresis = <2000>; 723 type = "hot"; 724 }; 725 }; 726 }; 727 728 cluster1-l2-thermal { 729 polling-delay-passive = <250>; 730 polling-delay = <1000>; 731 732 thermal-sensors = <&tsens0 11>; 733 734 trips { 735 cluster1_l2_alert0: trip-point0 { 736 temperature = <90000>; 737 hysteresis = <2000>; 738 type = "hot"; 739 }; 740 }; 741 }; 742 743 modem-thermal { 744 polling-delay-passive = <250>; 745 polling-delay = <1000>; 746 747 thermal-sensors = <&tsens1 1>; 748 749 trips { 750 modem_alert0: trip-point0 { 751 temperature = <90000>; 752 hysteresis = <2000>; 753 type = "hot"; 754 }; 755 }; 756 }; 757 758 mem-thermal { 759 polling-delay-passive = <250>; 760 polling-delay = <1000>; 761 762 thermal-sensors = <&tsens1 2>; 763 764 trips { 765 mem_alert0: trip-point0 { 766 temperature = <90000>; 767 hysteresis = <2000>; 768 type = "hot"; 769 }; 770 }; 771 }; 772 773 wlan-thermal { 774 polling-delay-passive = <250>; 775 polling-delay = <1000>; 776 777 thermal-sensors = <&tsens1 3>; 778 779 trips { 780 wlan_alert0: trip-point0 { 781 temperature = <90000>; 782 hysteresis = <2000>; 783 type = "hot"; 784 }; 785 }; 786 }; 787 788 q6-dsp-thermal { 789 polling-delay-passive = <250>; 790 polling-delay = <1000>; 791 792 thermal-sensors = <&tsens1 4>; 793 794 trips { 795 q6_dsp_alert0: trip-point0 { 796 temperature = <90000>; 797 hysteresis = <2000>; 798 type = "hot"; 799 }; 800 }; 801 }; 802 803 camera-thermal { 804 polling-delay-passive = <250>; 805 polling-delay = <1000>; 806 807 thermal-sensors = <&tsens1 5>; 808 809 trips { 810 camera_alert0: trip-point0 { 811 temperature = <90000>; 812 hysteresis = <2000>; 813 type = "hot"; 814 }; 815 }; 816 }; 817 818 multimedia-thermal { 819 polling-delay-passive = <250>; 820 polling-delay = <1000>; 821 822 thermal-sensors = <&tsens1 6>; 823 824 trips { 825 multimedia_alert0: trip-point0 { 826 temperature = <90000>; 827 hysteresis = <2000>; 828 type = "hot"; 829 }; 830 }; 831 }; 832 }; 833 834 timer { 835 compatible = "arm,armv8-timer"; 836 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 837 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 838 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 839 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 840 }; 841 842 soc: soc { 843 #address-cells = <1>; 844 #size-cells = <1>; 845 ranges = <0 0 0 0xffffffff>; 846 compatible = "simple-bus"; 847 848 gcc: clock-controller@100000 { 849 compatible = "qcom,gcc-msm8998"; 850 #clock-cells = <1>; 851 #reset-cells = <1>; 852 #power-domain-cells = <1>; 853 reg = <0x00100000 0xb0000>; 854 }; 855 856 rpm_msg_ram: memory@778000 { 857 compatible = "qcom,rpm-msg-ram"; 858 reg = <0x00778000 0x7000>; 859 }; 860 861 qfprom: qfprom@780000 { 862 compatible = "qcom,qfprom"; 863 reg = <0x00780000 0x621c>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 867 qusb2_hstx_trim: hstx-trim@423a { 868 reg = <0x423a 0x1>; 869 bits = <0 4>; 870 }; 871 }; 872 873 tsens0: thermal@10ab000 { 874 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 875 reg = <0x010ab000 0x1000>, /* TM */ 876 <0x010aa000 0x1000>; /* SROT */ 877 #qcom,sensors = <14>; 878 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "uplow", "critical"; 881 #thermal-sensor-cells = <1>; 882 }; 883 884 tsens1: thermal@10ae000 { 885 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 886 reg = <0x010ae000 0x1000>, /* TM */ 887 <0x010ad000 0x1000>; /* SROT */ 888 #qcom,sensors = <8>; 889 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "uplow", "critical"; 892 #thermal-sensor-cells = <1>; 893 }; 894 895 anoc1_smmu: iommu@1680000 { 896 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 897 reg = <0x01680000 0x10000>; 898 #iommu-cells = <1>; 899 900 #global-interrupts = <0>; 901 interrupts = 902 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 908 }; 909 910 anoc2_smmu: iommu@16c0000 { 911 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 912 reg = <0x016c0000 0x40000>; 913 #iommu-cells = <1>; 914 915 #global-interrupts = <0>; 916 interrupts = 917 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 918 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 919 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 920 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 921 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 922 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 923 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 924 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 925 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 926 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 927 }; 928 929 pcie0: pci@1c00000 { 930 compatible = "qcom,pcie-msm8996"; 931 reg = <0x01c00000 0x2000>, 932 <0x1b000000 0xf1d>, 933 <0x1b000f20 0xa8>, 934 <0x1b100000 0x100000>; 935 reg-names = "parf", "dbi", "elbi", "config"; 936 device_type = "pci"; 937 linux,pci-domain = <0>; 938 bus-range = <0x00 0xff>; 939 #address-cells = <3>; 940 #size-cells = <2>; 941 num-lanes = <1>; 942 phys = <&pciephy>; 943 phy-names = "pciephy"; 944 945 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 946 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 947 948 #interrupt-cells = <1>; 949 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "msi"; 951 interrupt-map-mask = <0 0 0 0x7>; 952 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 953 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 954 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 955 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 956 957 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 958 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 959 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 960 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 961 <&gcc GCC_PCIE_0_AUX_CLK>; 962 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 963 964 power-domains = <&gcc PCIE_0_GDSC>; 965 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 966 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 967 }; 968 969 phy@1c06000 { 970 compatible = "qcom,msm8998-qmp-pcie-phy"; 971 reg = <0x01c06000 0x18c>; 972 #address-cells = <1>; 973 #size-cells = <1>; 974 ranges; 975 976 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 977 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 978 <&gcc GCC_PCIE_CLKREF_CLK>; 979 clock-names = "aux", "cfg_ahb", "ref"; 980 981 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 982 reset-names = "phy", "common"; 983 984 vdda-phy-supply = <&vreg_l1a_0p875>; 985 vdda-pll-supply = <&vreg_l2a_1p2>; 986 987 pciephy: lane@1c06800 { 988 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 989 #phy-cells = <0>; 990 991 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 992 clock-names = "pipe0"; 993 clock-output-names = "pcie_0_pipe_clk_src"; 994 #clock-cells = <0>; 995 }; 996 }; 997 998 ufshc: ufshc@1da4000 { 999 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1000 reg = <0x01da4000 0x2500>; 1001 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1002 phys = <&ufsphy_lanes>; 1003 phy-names = "ufsphy"; 1004 lanes-per-direction = <2>; 1005 power-domains = <&gcc UFS_GDSC>; 1006 #reset-cells = <1>; 1007 1008 clock-names = 1009 "core_clk", 1010 "bus_aggr_clk", 1011 "iface_clk", 1012 "core_clk_unipro", 1013 "ref_clk", 1014 "tx_lane0_sync_clk", 1015 "rx_lane0_sync_clk", 1016 "rx_lane1_sync_clk"; 1017 clocks = 1018 <&gcc GCC_UFS_AXI_CLK>, 1019 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1020 <&gcc GCC_UFS_AHB_CLK>, 1021 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1022 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1023 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1024 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1025 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1026 freq-table-hz = 1027 <50000000 200000000>, 1028 <0 0>, 1029 <0 0>, 1030 <37500000 150000000>, 1031 <0 0>, 1032 <0 0>, 1033 <0 0>, 1034 <0 0>; 1035 1036 resets = <&gcc GCC_UFS_BCR>; 1037 reset-names = "rst"; 1038 }; 1039 1040 ufsphy: phy@1da7000 { 1041 compatible = "qcom,msm8998-qmp-ufs-phy"; 1042 reg = <0x01da7000 0x18c>; 1043 #address-cells = <1>; 1044 #size-cells = <1>; 1045 ranges; 1046 1047 clock-names = 1048 "ref", 1049 "ref_aux"; 1050 clocks = 1051 <&gcc GCC_UFS_CLKREF_CLK>, 1052 <&gcc GCC_UFS_PHY_AUX_CLK>; 1053 1054 reset-names = "ufsphy"; 1055 resets = <&ufshc 0>; 1056 1057 ufsphy_lanes: lanes@1da7400 { 1058 reg = <0x01da7400 0x128>, 1059 <0x01da7600 0x1fc>, 1060 <0x01da7c00 0x1dc>, 1061 <0x01da7800 0x128>, 1062 <0x01da7a00 0x1fc>; 1063 #phy-cells = <0>; 1064 }; 1065 }; 1066 1067 tcsr_mutex_regs: syscon@1f40000 { 1068 compatible = "syscon"; 1069 reg = <0x01f40000 0x40000>; 1070 }; 1071 1072 tlmm: pinctrl@3400000 { 1073 compatible = "qcom,msm8998-pinctrl"; 1074 reg = <0x03400000 0xc00000>; 1075 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1076 gpio-controller; 1077 #gpio-cells = <0x2>; 1078 interrupt-controller; 1079 #interrupt-cells = <0x2>; 1080 }; 1081 1082 remoteproc_mss: remoteproc@4080000 { 1083 compatible = "qcom,msm8998-mss-pil"; 1084 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1085 reg-names = "qdsp6", "rmb"; 1086 1087 interrupts-extended = 1088 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1089 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1090 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1091 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1092 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1093 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1094 interrupt-names = "wdog", "fatal", "ready", 1095 "handover", "stop-ack", 1096 "shutdown-ack"; 1097 1098 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1099 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1100 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1101 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1102 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1103 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1104 <&rpmcc RPM_SMD_QDSS_CLK>, 1105 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1106 clock-names = "iface", "bus", "mem", "gpll0_mss", 1107 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1108 1109 qcom,smem-states = <&modem_smp2p_out 0>; 1110 qcom,smem-state-names = "stop"; 1111 1112 resets = <&gcc GCC_MSS_RESTART>; 1113 reset-names = "mss_restart"; 1114 1115 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1116 1117 power-domains = <&rpmpd MSM8998_VDDCX>, 1118 <&rpmpd MSM8998_VDDMX>; 1119 power-domain-names = "cx", "mx"; 1120 1121 mba { 1122 memory-region = <&mba_mem>; 1123 }; 1124 1125 mpss { 1126 memory-region = <&mpss_mem>; 1127 }; 1128 1129 glink-edge { 1130 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1131 label = "modem"; 1132 qcom,remote-pid = <1>; 1133 mboxes = <&apcs_glb 15>; 1134 }; 1135 }; 1136 1137 gpucc: clock-controller@5065000 { 1138 compatible = "qcom,msm8998-gpucc"; 1139 #clock-cells = <1>; 1140 #reset-cells = <1>; 1141 #power-domain-cells = <1>; 1142 reg = <0x05065000 0x9000>; 1143 1144 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1145 <&gcc GPLL0_OUT_MAIN>; 1146 clock-names = "xo", 1147 "gpll0"; 1148 }; 1149 1150 remoteproc_slpi: remoteproc@5800000 { 1151 compatible = "qcom,msm8998-slpi-pas"; 1152 reg = <0x05800000 0x4040>; 1153 1154 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1155 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1156 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1157 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1158 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1159 interrupt-names = "wdog", "fatal", "ready", 1160 "handover", "stop-ack"; 1161 1162 px-supply = <&vreg_lvs2a_1p8>; 1163 1164 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1165 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1166 clock-names = "xo", "aggre2"; 1167 1168 memory-region = <&slpi_mem>; 1169 1170 qcom,smem-states = <&slpi_smp2p_out 0>; 1171 qcom,smem-state-names = "stop"; 1172 1173 power-domains = <&rpmpd MSM8998_SSCCX>; 1174 power-domain-names = "ssc_cx"; 1175 1176 status = "disabled"; 1177 1178 glink-edge { 1179 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1180 label = "dsps"; 1181 qcom,remote-pid = <3>; 1182 mboxes = <&apcs_glb 27>; 1183 }; 1184 }; 1185 1186 stm: stm@6002000 { 1187 compatible = "arm,coresight-stm", "arm,primecell"; 1188 reg = <0x06002000 0x1000>, 1189 <0x16280000 0x180000>; 1190 reg-names = "stm-base", "stm-data-base"; 1191 status = "disabled"; 1192 1193 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1194 clock-names = "apb_pclk", "atclk"; 1195 1196 out-ports { 1197 port { 1198 stm_out: endpoint { 1199 remote-endpoint = <&funnel0_in7>; 1200 }; 1201 }; 1202 }; 1203 }; 1204 1205 funnel1: funnel@6041000 { 1206 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1207 reg = <0x06041000 0x1000>; 1208 status = "disabled"; 1209 1210 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1211 clock-names = "apb_pclk", "atclk"; 1212 1213 out-ports { 1214 port { 1215 funnel0_out: endpoint { 1216 remote-endpoint = 1217 <&merge_funnel_in0>; 1218 }; 1219 }; 1220 }; 1221 1222 in-ports { 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 1226 port@7 { 1227 reg = <7>; 1228 funnel0_in7: endpoint { 1229 remote-endpoint = <&stm_out>; 1230 }; 1231 }; 1232 }; 1233 }; 1234 1235 funnel2: funnel@6042000 { 1236 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1237 reg = <0x06042000 0x1000>; 1238 status = "disabled"; 1239 1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1241 clock-names = "apb_pclk", "atclk"; 1242 1243 out-ports { 1244 port { 1245 funnel1_out: endpoint { 1246 remote-endpoint = 1247 <&merge_funnel_in1>; 1248 }; 1249 }; 1250 }; 1251 1252 in-ports { 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 1256 port@6 { 1257 reg = <6>; 1258 funnel1_in6: endpoint { 1259 remote-endpoint = 1260 <&apss_merge_funnel_out>; 1261 }; 1262 }; 1263 }; 1264 }; 1265 1266 funnel3: funnel@6045000 { 1267 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1268 reg = <0x06045000 0x1000>; 1269 status = "disabled"; 1270 1271 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1272 clock-names = "apb_pclk", "atclk"; 1273 1274 out-ports { 1275 port { 1276 merge_funnel_out: endpoint { 1277 remote-endpoint = 1278 <&etf_in>; 1279 }; 1280 }; 1281 }; 1282 1283 in-ports { 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 port@0 { 1288 reg = <0>; 1289 merge_funnel_in0: endpoint { 1290 remote-endpoint = 1291 <&funnel0_out>; 1292 }; 1293 }; 1294 1295 port@1 { 1296 reg = <1>; 1297 merge_funnel_in1: endpoint { 1298 remote-endpoint = 1299 <&funnel1_out>; 1300 }; 1301 }; 1302 }; 1303 }; 1304 1305 replicator1: replicator@6046000 { 1306 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1307 reg = <0x06046000 0x1000>; 1308 status = "disabled"; 1309 1310 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1311 clock-names = "apb_pclk", "atclk"; 1312 1313 out-ports { 1314 port { 1315 replicator_out: endpoint { 1316 remote-endpoint = <&etr_in>; 1317 }; 1318 }; 1319 }; 1320 1321 in-ports { 1322 port { 1323 replicator_in: endpoint { 1324 remote-endpoint = <&etf_out>; 1325 }; 1326 }; 1327 }; 1328 }; 1329 1330 etf: etf@6047000 { 1331 compatible = "arm,coresight-tmc", "arm,primecell"; 1332 reg = <0x06047000 0x1000>; 1333 status = "disabled"; 1334 1335 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1336 clock-names = "apb_pclk", "atclk"; 1337 1338 out-ports { 1339 port { 1340 etf_out: endpoint { 1341 remote-endpoint = 1342 <&replicator_in>; 1343 }; 1344 }; 1345 }; 1346 1347 in-ports { 1348 port { 1349 etf_in: endpoint { 1350 remote-endpoint = 1351 <&merge_funnel_out>; 1352 }; 1353 }; 1354 }; 1355 }; 1356 1357 etr: etr@6048000 { 1358 compatible = "arm,coresight-tmc", "arm,primecell"; 1359 reg = <0x06048000 0x1000>; 1360 status = "disabled"; 1361 1362 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1363 clock-names = "apb_pclk", "atclk"; 1364 arm,scatter-gather; 1365 1366 in-ports { 1367 port { 1368 etr_in: endpoint { 1369 remote-endpoint = 1370 <&replicator_out>; 1371 }; 1372 }; 1373 }; 1374 }; 1375 1376 etm1: etm@7840000 { 1377 compatible = "arm,coresight-etm4x", "arm,primecell"; 1378 reg = <0x07840000 0x1000>; 1379 status = "disabled"; 1380 1381 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1382 clock-names = "apb_pclk", "atclk"; 1383 1384 cpu = <&CPU0>; 1385 1386 out-ports { 1387 port { 1388 etm0_out: endpoint { 1389 remote-endpoint = 1390 <&apss_funnel_in0>; 1391 }; 1392 }; 1393 }; 1394 }; 1395 1396 etm2: etm@7940000 { 1397 compatible = "arm,coresight-etm4x", "arm,primecell"; 1398 reg = <0x07940000 0x1000>; 1399 status = "disabled"; 1400 1401 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1402 clock-names = "apb_pclk", "atclk"; 1403 1404 cpu = <&CPU1>; 1405 1406 out-ports { 1407 port { 1408 etm1_out: endpoint { 1409 remote-endpoint = 1410 <&apss_funnel_in1>; 1411 }; 1412 }; 1413 }; 1414 }; 1415 1416 etm3: etm@7a40000 { 1417 compatible = "arm,coresight-etm4x", "arm,primecell"; 1418 reg = <0x07a40000 0x1000>; 1419 status = "disabled"; 1420 1421 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1422 clock-names = "apb_pclk", "atclk"; 1423 1424 cpu = <&CPU2>; 1425 1426 out-ports { 1427 port { 1428 etm2_out: endpoint { 1429 remote-endpoint = 1430 <&apss_funnel_in2>; 1431 }; 1432 }; 1433 }; 1434 }; 1435 1436 etm4: etm@7b40000 { 1437 compatible = "arm,coresight-etm4x", "arm,primecell"; 1438 reg = <0x07b40000 0x1000>; 1439 status = "disabled"; 1440 1441 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1442 clock-names = "apb_pclk", "atclk"; 1443 1444 cpu = <&CPU3>; 1445 1446 out-ports { 1447 port { 1448 etm3_out: endpoint { 1449 remote-endpoint = 1450 <&apss_funnel_in3>; 1451 }; 1452 }; 1453 }; 1454 }; 1455 1456 funnel4: funnel@7b60000 { /* APSS Funnel */ 1457 compatible = "arm,coresight-etm4x", "arm,primecell"; 1458 reg = <0x07b60000 0x1000>; 1459 status = "disabled"; 1460 1461 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1462 clock-names = "apb_pclk", "atclk"; 1463 1464 out-ports { 1465 port { 1466 apss_funnel_out: endpoint { 1467 remote-endpoint = 1468 <&apss_merge_funnel_in>; 1469 }; 1470 }; 1471 }; 1472 1473 in-ports { 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 1477 port@0 { 1478 reg = <0>; 1479 apss_funnel_in0: endpoint { 1480 remote-endpoint = 1481 <&etm0_out>; 1482 }; 1483 }; 1484 1485 port@1 { 1486 reg = <1>; 1487 apss_funnel_in1: endpoint { 1488 remote-endpoint = 1489 <&etm1_out>; 1490 }; 1491 }; 1492 1493 port@2 { 1494 reg = <2>; 1495 apss_funnel_in2: endpoint { 1496 remote-endpoint = 1497 <&etm2_out>; 1498 }; 1499 }; 1500 1501 port@3 { 1502 reg = <3>; 1503 apss_funnel_in3: endpoint { 1504 remote-endpoint = 1505 <&etm3_out>; 1506 }; 1507 }; 1508 1509 port@4 { 1510 reg = <4>; 1511 apss_funnel_in4: endpoint { 1512 remote-endpoint = 1513 <&etm4_out>; 1514 }; 1515 }; 1516 1517 port@5 { 1518 reg = <5>; 1519 apss_funnel_in5: endpoint { 1520 remote-endpoint = 1521 <&etm5_out>; 1522 }; 1523 }; 1524 1525 port@6 { 1526 reg = <6>; 1527 apss_funnel_in6: endpoint { 1528 remote-endpoint = 1529 <&etm6_out>; 1530 }; 1531 }; 1532 1533 port@7 { 1534 reg = <7>; 1535 apss_funnel_in7: endpoint { 1536 remote-endpoint = 1537 <&etm7_out>; 1538 }; 1539 }; 1540 }; 1541 }; 1542 1543 funnel5: funnel@7b70000 { 1544 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1545 reg = <0x07b70000 0x1000>; 1546 status = "disabled"; 1547 1548 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1549 clock-names = "apb_pclk", "atclk"; 1550 1551 out-ports { 1552 port { 1553 apss_merge_funnel_out: endpoint { 1554 remote-endpoint = 1555 <&funnel1_in6>; 1556 }; 1557 }; 1558 }; 1559 1560 in-ports { 1561 port { 1562 apss_merge_funnel_in: endpoint { 1563 remote-endpoint = 1564 <&apss_funnel_out>; 1565 }; 1566 }; 1567 }; 1568 }; 1569 1570 etm5: etm@7c40000 { 1571 compatible = "arm,coresight-etm4x", "arm,primecell"; 1572 reg = <0x07c40000 0x1000>; 1573 status = "disabled"; 1574 1575 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1576 clock-names = "apb_pclk", "atclk"; 1577 1578 cpu = <&CPU4>; 1579 1580 port{ 1581 etm4_out: endpoint { 1582 remote-endpoint = <&apss_funnel_in4>; 1583 }; 1584 }; 1585 }; 1586 1587 etm6: etm@7d40000 { 1588 compatible = "arm,coresight-etm4x", "arm,primecell"; 1589 reg = <0x07d40000 0x1000>; 1590 status = "disabled"; 1591 1592 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1593 clock-names = "apb_pclk", "atclk"; 1594 1595 cpu = <&CPU5>; 1596 1597 port{ 1598 etm5_out: endpoint { 1599 remote-endpoint = <&apss_funnel_in5>; 1600 }; 1601 }; 1602 }; 1603 1604 etm7: etm@7e40000 { 1605 compatible = "arm,coresight-etm4x", "arm,primecell"; 1606 reg = <0x07e40000 0x1000>; 1607 status = "disabled"; 1608 1609 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1610 clock-names = "apb_pclk", "atclk"; 1611 1612 cpu = <&CPU6>; 1613 1614 port{ 1615 etm6_out: endpoint { 1616 remote-endpoint = <&apss_funnel_in6>; 1617 }; 1618 }; 1619 }; 1620 1621 etm8: etm@7f40000 { 1622 compatible = "arm,coresight-etm4x", "arm,primecell"; 1623 reg = <0x07f40000 0x1000>; 1624 status = "disabled"; 1625 1626 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1627 clock-names = "apb_pclk", "atclk"; 1628 1629 cpu = <&CPU7>; 1630 1631 port{ 1632 etm7_out: endpoint { 1633 remote-endpoint = <&apss_funnel_in7>; 1634 }; 1635 }; 1636 }; 1637 1638 spmi_bus: spmi@800f000 { 1639 compatible = "qcom,spmi-pmic-arb"; 1640 reg = <0x0800f000 0x1000>, 1641 <0x08400000 0x1000000>, 1642 <0x09400000 0x1000000>, 1643 <0x0a400000 0x220000>, 1644 <0x0800a000 0x3000>; 1645 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1646 interrupt-names = "periph_irq"; 1647 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1648 qcom,ee = <0>; 1649 qcom,channel = <0>; 1650 #address-cells = <2>; 1651 #size-cells = <0>; 1652 interrupt-controller; 1653 #interrupt-cells = <4>; 1654 cell-index = <0>; 1655 }; 1656 1657 usb3: usb@a8f8800 { 1658 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1659 reg = <0x0a8f8800 0x400>; 1660 status = "disabled"; 1661 #address-cells = <1>; 1662 #size-cells = <1>; 1663 ranges; 1664 1665 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1666 <&gcc GCC_USB30_MASTER_CLK>, 1667 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1668 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1669 <&gcc GCC_USB30_SLEEP_CLK>; 1670 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1671 "sleep"; 1672 1673 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1674 <&gcc GCC_USB30_MASTER_CLK>; 1675 assigned-clock-rates = <19200000>, <120000000>; 1676 1677 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1679 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1680 1681 power-domains = <&gcc USB_30_GDSC>; 1682 1683 resets = <&gcc GCC_USB_30_BCR>; 1684 1685 usb3_dwc3: dwc3@a800000 { 1686 compatible = "snps,dwc3"; 1687 reg = <0x0a800000 0xcd00>; 1688 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1689 snps,dis_u2_susphy_quirk; 1690 snps,dis_enblslpm_quirk; 1691 phys = <&qusb2phy>, <&usb1_ssphy>; 1692 phy-names = "usb2-phy", "usb3-phy"; 1693 snps,has-lpm-erratum; 1694 snps,hird-threshold = /bits/ 8 <0x10>; 1695 }; 1696 }; 1697 1698 usb3phy: phy@c010000 { 1699 compatible = "qcom,msm8998-qmp-usb3-phy"; 1700 reg = <0x0c010000 0x18c>; 1701 status = "disabled"; 1702 #clock-cells = <1>; 1703 #address-cells = <1>; 1704 #size-cells = <1>; 1705 ranges; 1706 1707 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1708 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1709 <&gcc GCC_USB3_CLKREF_CLK>; 1710 clock-names = "aux", "cfg_ahb", "ref"; 1711 1712 resets = <&gcc GCC_USB3_PHY_BCR>, 1713 <&gcc GCC_USB3PHY_PHY_BCR>; 1714 reset-names = "phy", "common"; 1715 1716 usb1_ssphy: lane@c010200 { 1717 reg = <0xc010200 0x128>, 1718 <0xc010400 0x200>, 1719 <0xc010c00 0x20c>, 1720 <0xc010600 0x128>, 1721 <0xc010800 0x200>; 1722 #phy-cells = <0>; 1723 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1724 clock-names = "pipe0"; 1725 clock-output-names = "usb3_phy_pipe_clk_src"; 1726 }; 1727 }; 1728 1729 qusb2phy: phy@c012000 { 1730 compatible = "qcom,msm8998-qusb2-phy"; 1731 reg = <0x0c012000 0x2a8>; 1732 status = "disabled"; 1733 #phy-cells = <0>; 1734 1735 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1736 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1737 clock-names = "cfg_ahb", "ref"; 1738 1739 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1740 1741 nvmem-cells = <&qusb2_hstx_trim>; 1742 }; 1743 1744 sdhc2: sdhci@c0a4900 { 1745 compatible = "qcom,sdhci-msm-v4"; 1746 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 1747 reg-names = "hc_mem", "core_mem"; 1748 1749 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1751 interrupt-names = "hc_irq", "pwr_irq"; 1752 1753 clock-names = "iface", "core", "xo"; 1754 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1755 <&gcc GCC_SDCC2_APPS_CLK>, 1756 <&xo>; 1757 bus-width = <4>; 1758 status = "disabled"; 1759 }; 1760 1761 blsp1_dma: dma@c144000 { 1762 compatible = "qcom,bam-v1.7.0"; 1763 reg = <0x0c144000 0x25000>; 1764 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1766 clock-names = "bam_clk"; 1767 #dma-cells = <1>; 1768 qcom,ee = <0>; 1769 qcom,controlled-remotely; 1770 num-channels = <18>; 1771 qcom,num-ees = <4>; 1772 }; 1773 1774 blsp1_uart3: serial@c171000 { 1775 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1776 reg = <0x0c171000 0x1000>; 1777 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1778 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 1779 <&gcc GCC_BLSP1_AHB_CLK>; 1780 clock-names = "core", "iface"; 1781 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1782 dma-names = "tx", "rx"; 1783 pinctrl-names = "default"; 1784 pinctrl-0 = <&blsp1_uart3_on>; 1785 status = "disabled"; 1786 }; 1787 1788 blsp1_i2c1: i2c@c175000 { 1789 compatible = "qcom,i2c-qup-v2.2.1"; 1790 reg = <0x0c175000 0x600>; 1791 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1792 1793 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1794 <&gcc GCC_BLSP1_AHB_CLK>; 1795 clock-names = "core", "iface"; 1796 clock-frequency = <400000>; 1797 1798 status = "disabled"; 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 }; 1802 1803 blsp1_i2c2: i2c@c176000 { 1804 compatible = "qcom,i2c-qup-v2.2.1"; 1805 reg = <0x0c176000 0x600>; 1806 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1807 1808 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1809 <&gcc GCC_BLSP1_AHB_CLK>; 1810 clock-names = "core", "iface"; 1811 clock-frequency = <400000>; 1812 1813 status = "disabled"; 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 }; 1817 1818 blsp1_i2c3: i2c@c177000 { 1819 compatible = "qcom,i2c-qup-v2.2.1"; 1820 reg = <0x0c177000 0x600>; 1821 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1822 1823 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1824 <&gcc GCC_BLSP1_AHB_CLK>; 1825 clock-names = "core", "iface"; 1826 clock-frequency = <400000>; 1827 1828 status = "disabled"; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 }; 1832 1833 blsp1_i2c4: i2c@c178000 { 1834 compatible = "qcom,i2c-qup-v2.2.1"; 1835 reg = <0x0c178000 0x600>; 1836 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1837 1838 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1839 <&gcc GCC_BLSP1_AHB_CLK>; 1840 clock-names = "core", "iface"; 1841 clock-frequency = <400000>; 1842 1843 status = "disabled"; 1844 #address-cells = <1>; 1845 #size-cells = <0>; 1846 }; 1847 1848 blsp1_i2c5: i2c@c179000 { 1849 compatible = "qcom,i2c-qup-v2.2.1"; 1850 reg = <0x0c179000 0x600>; 1851 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1852 1853 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1854 <&gcc GCC_BLSP1_AHB_CLK>; 1855 clock-names = "core", "iface"; 1856 clock-frequency = <400000>; 1857 1858 status = "disabled"; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 }; 1862 1863 blsp1_i2c6: i2c@c17a000 { 1864 compatible = "qcom,i2c-qup-v2.2.1"; 1865 reg = <0x0c17a000 0x600>; 1866 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1867 1868 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1869 <&gcc GCC_BLSP1_AHB_CLK>; 1870 clock-names = "core", "iface"; 1871 clock-frequency = <400000>; 1872 1873 status = "disabled"; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 }; 1877 1878 blsp2_uart1: serial@c1b0000 { 1879 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1880 reg = <0x0c1b0000 0x1000>; 1881 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1882 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1883 <&gcc GCC_BLSP2_AHB_CLK>; 1884 clock-names = "core", "iface"; 1885 status = "disabled"; 1886 }; 1887 1888 blsp2_i2c0: i2c@c1b5000 { 1889 compatible = "qcom,i2c-qup-v2.2.1"; 1890 reg = <0x0c1b5000 0x600>; 1891 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1892 1893 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1894 <&gcc GCC_BLSP2_AHB_CLK>; 1895 clock-names = "core", "iface"; 1896 clock-frequency = <400000>; 1897 1898 status = "disabled"; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 }; 1902 1903 blsp2_i2c1: i2c@c1b6000 { 1904 compatible = "qcom,i2c-qup-v2.2.1"; 1905 reg = <0x0c1b6000 0x600>; 1906 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1907 1908 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1909 <&gcc GCC_BLSP2_AHB_CLK>; 1910 clock-names = "core", "iface"; 1911 clock-frequency = <400000>; 1912 1913 status = "disabled"; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 }; 1917 1918 blsp2_i2c2: i2c@c1b7000 { 1919 compatible = "qcom,i2c-qup-v2.2.1"; 1920 reg = <0x0c1b7000 0x600>; 1921 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1922 1923 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1924 <&gcc GCC_BLSP2_AHB_CLK>; 1925 clock-names = "core", "iface"; 1926 clock-frequency = <400000>; 1927 1928 status = "disabled"; 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 }; 1932 1933 blsp2_i2c3: i2c@c1b8000 { 1934 compatible = "qcom,i2c-qup-v2.2.1"; 1935 reg = <0x0c1b8000 0x600>; 1936 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1937 1938 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1939 <&gcc GCC_BLSP2_AHB_CLK>; 1940 clock-names = "core", "iface"; 1941 clock-frequency = <400000>; 1942 1943 status = "disabled"; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 }; 1947 1948 blsp2_i2c4: i2c@c1b9000 { 1949 compatible = "qcom,i2c-qup-v2.2.1"; 1950 reg = <0x0c1b9000 0x600>; 1951 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1952 1953 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1954 <&gcc GCC_BLSP2_AHB_CLK>; 1955 clock-names = "core", "iface"; 1956 clock-frequency = <400000>; 1957 1958 status = "disabled"; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 }; 1962 1963 blsp2_i2c5: i2c@c1ba000 { 1964 compatible = "qcom,i2c-qup-v2.2.1"; 1965 reg = <0x0c1ba000 0x600>; 1966 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1967 1968 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1969 <&gcc GCC_BLSP2_AHB_CLK>; 1970 clock-names = "core", "iface"; 1971 clock-frequency = <400000>; 1972 1973 status = "disabled"; 1974 #address-cells = <1>; 1975 #size-cells = <0>; 1976 }; 1977 1978 remoteproc_adsp: remoteproc@17300000 { 1979 compatible = "qcom,msm8998-adsp-pas"; 1980 reg = <0x17300000 0x4040>; 1981 1982 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1983 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1984 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1985 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1986 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1987 interrupt-names = "wdog", "fatal", "ready", 1988 "handover", "stop-ack"; 1989 1990 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1991 clock-names = "xo"; 1992 1993 memory-region = <&adsp_mem>; 1994 1995 qcom,smem-states = <&adsp_smp2p_out 0>; 1996 qcom,smem-state-names = "stop"; 1997 1998 power-domains = <&rpmpd MSM8998_VDDCX>; 1999 power-domain-names = "cx"; 2000 2001 status = "disabled"; 2002 2003 glink-edge { 2004 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2005 label = "lpass"; 2006 qcom,remote-pid = <2>; 2007 mboxes = <&apcs_glb 9>; 2008 }; 2009 }; 2010 2011 apcs_glb: mailbox@17911000 { 2012 compatible = "qcom,msm8998-apcs-hmss-global"; 2013 reg = <0x17911000 0x1000>; 2014 2015 #mbox-cells = <1>; 2016 }; 2017 2018 timer@17920000 { 2019 #address-cells = <1>; 2020 #size-cells = <1>; 2021 ranges; 2022 compatible = "arm,armv7-timer-mem"; 2023 reg = <0x17920000 0x1000>; 2024 2025 frame@17921000 { 2026 frame-number = <0>; 2027 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2029 reg = <0x17921000 0x1000>, 2030 <0x17922000 0x1000>; 2031 }; 2032 2033 frame@17923000 { 2034 frame-number = <1>; 2035 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2036 reg = <0x17923000 0x1000>; 2037 status = "disabled"; 2038 }; 2039 2040 frame@17924000 { 2041 frame-number = <2>; 2042 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2043 reg = <0x17924000 0x1000>; 2044 status = "disabled"; 2045 }; 2046 2047 frame@17925000 { 2048 frame-number = <3>; 2049 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2050 reg = <0x17925000 0x1000>; 2051 status = "disabled"; 2052 }; 2053 2054 frame@17926000 { 2055 frame-number = <4>; 2056 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2057 reg = <0x17926000 0x1000>; 2058 status = "disabled"; 2059 }; 2060 2061 frame@17927000 { 2062 frame-number = <5>; 2063 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2064 reg = <0x17927000 0x1000>; 2065 status = "disabled"; 2066 }; 2067 2068 frame@17928000 { 2069 frame-number = <6>; 2070 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2071 reg = <0x17928000 0x1000>; 2072 status = "disabled"; 2073 }; 2074 }; 2075 2076 intc: interrupt-controller@17a00000 { 2077 compatible = "arm,gic-v3"; 2078 reg = <0x17a00000 0x10000>, /* GICD */ 2079 <0x17b00000 0x100000>; /* GICR * 8 */ 2080 #interrupt-cells = <3>; 2081 #address-cells = <1>; 2082 #size-cells = <1>; 2083 ranges; 2084 interrupt-controller; 2085 #redistributor-regions = <1>; 2086 redistributor-stride = <0x0 0x20000>; 2087 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2088 }; 2089 2090 wifi: wifi@18800000 { 2091 compatible = "qcom,wcn3990-wifi"; 2092 status = "disabled"; 2093 reg = <0x18800000 0x800000>; 2094 reg-names = "membase"; 2095 memory-region = <&wlan_msa_mem>; 2096 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2097 clock-names = "cxo_ref_clk_pin"; 2098 interrupts = 2099 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2111 iommus = <&anoc2_smmu 0x1900>, 2112 <&anoc2_smmu 0x1901>; 2113 qcom,snoc-host-cap-8bit-quirk; 2114 }; 2115 }; 2116}; 2117 2118#include "msm8998-pins.dtsi" 2119