1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 scm_conf: scm-conf@100000 { 22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 23 reg = <0x00 0x00100000 0x00 0x1c000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0x00 0x00 0x00100000 0x1c000>; 27 28 serdes_ln_ctrl: mux-controller@4080 { 29 compatible = "mmio-mux"; 30 #mux-control-cells = <1>; 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 33 }; 34 35 usb_serdes_mux: mux-controller@4000 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 39 }; 40 }; 41 42 gic500: interrupt-controller@1800000 { 43 compatible = "arm,gic-v3"; 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 #interrupt-cells = <3>; 48 interrupt-controller; 49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 50 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 51 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 52 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 53 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 54 55 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 56 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 57 58 gic_its: msi-controller@1820000 { 59 compatible = "arm,gic-v3-its"; 60 reg = <0x00 0x01820000 0x00 0x10000>; 61 socionext,synquacer-pre-its = <0x1000000 0x400000>; 62 msi-controller; 63 #msi-cells = <1>; 64 }; 65 }; 66 67 main_gpio_intr: interrupt-controller0 { 68 compatible = "ti,sci-intr"; 69 ti,intr-trigger-type = <1>; 70 interrupt-controller; 71 interrupt-parent = <&gic500>; 72 #interrupt-cells = <1>; 73 ti,sci = <&dmsc>; 74 ti,sci-dev-id = <131>; 75 ti,interrupt-ranges = <8 392 56>; 76 }; 77 78 main_navss: bus@30000000 { 79 compatible = "simple-mfd"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 83 ti,sci-dev-id = <199>; 84 dma-coherent; 85 dma-ranges; 86 87 main_navss_intr: interrupt-controller1 { 88 compatible = "ti,sci-intr"; 89 ti,intr-trigger-type = <4>; 90 interrupt-controller; 91 interrupt-parent = <&gic500>; 92 #interrupt-cells = <1>; 93 ti,sci = <&dmsc>; 94 ti,sci-dev-id = <213>; 95 ti,interrupt-ranges = <0 64 64>, 96 <64 448 64>, 97 <128 672 64>; 98 }; 99 100 main_udmass_inta: msi-controller@33d00000 { 101 compatible = "ti,sci-inta"; 102 reg = <0x00 0x33d00000 0x00 0x100000>; 103 interrupt-controller; 104 #interrupt-cells = <0>; 105 interrupt-parent = <&main_navss_intr>; 106 msi-controller; 107 ti,sci = <&dmsc>; 108 ti,sci-dev-id = <209>; 109 ti,interrupt-ranges = <0 0 256>; 110 }; 111 112 secure_proxy_main: mailbox@32c00000 { 113 compatible = "ti,am654-secure-proxy"; 114 #mbox-cells = <1>; 115 reg-names = "target_data", "rt", "scfg"; 116 reg = <0x00 0x32c00000 0x00 0x100000>, 117 <0x00 0x32400000 0x00 0x100000>, 118 <0x00 0x32800000 0x00 0x100000>; 119 interrupt-names = "rx_011"; 120 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 121 }; 122 123 main_ringacc: ringacc@3c000000 { 124 compatible = "ti,am654-navss-ringacc"; 125 reg = <0x00 0x3c000000 0x00 0x400000>, 126 <0x00 0x38000000 0x00 0x400000>, 127 <0x00 0x31120000 0x00 0x100>, 128 <0x00 0x33000000 0x00 0x40000>; 129 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 130 ti,num-rings = <1024>; 131 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 132 ti,sci = <&dmsc>; 133 ti,sci-dev-id = <211>; 134 msi-parent = <&main_udmass_inta>; 135 }; 136 137 main_udmap: dma-controller@31150000 { 138 compatible = "ti,j721e-navss-main-udmap"; 139 reg = <0x00 0x31150000 0x00 0x100>, 140 <0x00 0x34000000 0x00 0x100000>, 141 <0x00 0x35000000 0x00 0x100000>; 142 reg-names = "gcfg", "rchanrt", "tchanrt"; 143 msi-parent = <&main_udmass_inta>; 144 #dma-cells = <1>; 145 146 ti,sci = <&dmsc>; 147 ti,sci-dev-id = <212>; 148 ti,ringacc = <&main_ringacc>; 149 150 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 151 <0x0f>, /* TX_HCHAN */ 152 <0x10>; /* TX_UHCHAN */ 153 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 154 <0x0b>, /* RX_HCHAN */ 155 <0x0c>; /* RX_UHCHAN */ 156 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 157 }; 158 159 cpts@310d0000 { 160 compatible = "ti,j721e-cpts"; 161 reg = <0x00 0x310d0000 0x00 0x400>; 162 reg-names = "cpts"; 163 clocks = <&k3_clks 201 1>; 164 clock-names = "cpts"; 165 interrupts-extended = <&main_navss_intr 391>; 166 interrupt-names = "cpts"; 167 ti,cpts-periodic-outputs = <6>; 168 ti,cpts-ext-ts-inputs = <8>; 169 }; 170 }; 171 172 main_pmx0: pinctrl@11c000 { 173 compatible = "pinctrl-single"; 174 /* Proxy 0 addressing */ 175 reg = <0x00 0x11c000 0x00 0x2b4>; 176 #pinctrl-cells = <1>; 177 pinctrl-single,register-width = <32>; 178 pinctrl-single,function-mask = <0xffffffff>; 179 }; 180 181 main_uart0: serial@2800000 { 182 compatible = "ti,j721e-uart", "ti,am654-uart"; 183 reg = <0x00 0x02800000 0x00 0x100>; 184 reg-shift = <2>; 185 reg-io-width = <4>; 186 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 187 clock-frequency = <48000000>; 188 current-speed = <115200>; 189 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 190 clocks = <&k3_clks 146 2>; 191 clock-names = "fclk"; 192 }; 193 194 main_uart1: serial@2810000 { 195 compatible = "ti,j721e-uart", "ti,am654-uart"; 196 reg = <0x00 0x02810000 0x00 0x100>; 197 reg-shift = <2>; 198 reg-io-width = <4>; 199 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 200 clock-frequency = <48000000>; 201 current-speed = <115200>; 202 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 203 clocks = <&k3_clks 278 2>; 204 clock-names = "fclk"; 205 }; 206 207 main_uart2: serial@2820000 { 208 compatible = "ti,j721e-uart", "ti,am654-uart"; 209 reg = <0x00 0x02820000 0x00 0x100>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 213 clock-frequency = <48000000>; 214 current-speed = <115200>; 215 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 216 clocks = <&k3_clks 279 2>; 217 clock-names = "fclk"; 218 }; 219 220 main_uart3: serial@2830000 { 221 compatible = "ti,j721e-uart", "ti,am654-uart"; 222 reg = <0x00 0x02830000 0x00 0x100>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 226 clock-frequency = <48000000>; 227 current-speed = <115200>; 228 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 229 clocks = <&k3_clks 280 2>; 230 clock-names = "fclk"; 231 }; 232 233 main_uart4: serial@2840000 { 234 compatible = "ti,j721e-uart", "ti,am654-uart"; 235 reg = <0x00 0x02840000 0x00 0x100>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 239 clock-frequency = <48000000>; 240 current-speed = <115200>; 241 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 242 clocks = <&k3_clks 281 2>; 243 clock-names = "fclk"; 244 }; 245 246 main_uart5: serial@2850000 { 247 compatible = "ti,j721e-uart", "ti,am654-uart"; 248 reg = <0x00 0x02850000 0x00 0x100>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 252 clock-frequency = <48000000>; 253 current-speed = <115200>; 254 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 255 clocks = <&k3_clks 282 2>; 256 clock-names = "fclk"; 257 }; 258 259 main_uart6: serial@2860000 { 260 compatible = "ti,j721e-uart", "ti,am654-uart"; 261 reg = <0x00 0x02860000 0x00 0x100>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 265 clock-frequency = <48000000>; 266 current-speed = <115200>; 267 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 268 clocks = <&k3_clks 283 2>; 269 clock-names = "fclk"; 270 }; 271 272 main_uart7: serial@2870000 { 273 compatible = "ti,j721e-uart", "ti,am654-uart"; 274 reg = <0x00 0x02870000 0x00 0x100>; 275 reg-shift = <2>; 276 reg-io-width = <4>; 277 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 278 clock-frequency = <48000000>; 279 current-speed = <115200>; 280 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 281 clocks = <&k3_clks 284 2>; 282 clock-names = "fclk"; 283 }; 284 285 main_uart8: serial@2880000 { 286 compatible = "ti,j721e-uart", "ti,am654-uart"; 287 reg = <0x00 0x02880000 0x00 0x100>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 291 clock-frequency = <48000000>; 292 current-speed = <115200>; 293 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 294 clocks = <&k3_clks 285 2>; 295 clock-names = "fclk"; 296 }; 297 298 main_uart9: serial@2890000 { 299 compatible = "ti,j721e-uart", "ti,am654-uart"; 300 reg = <0x00 0x02890000 0x00 0x100>; 301 reg-shift = <2>; 302 reg-io-width = <4>; 303 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 304 clock-frequency = <48000000>; 305 current-speed = <115200>; 306 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 307 clocks = <&k3_clks 286 2>; 308 clock-names = "fclk"; 309 }; 310 311 main_i2c0: i2c@2000000 { 312 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 313 reg = <0x00 0x2000000 0x00 0x100>; 314 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 clock-names = "fck"; 318 clocks = <&k3_clks 187 1>; 319 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 320 }; 321 322 main_i2c1: i2c@2010000 { 323 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 324 reg = <0x00 0x2010000 0x00 0x100>; 325 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clock-names = "fck"; 329 clocks = <&k3_clks 188 1>; 330 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 331 }; 332 333 main_i2c2: i2c@2020000 { 334 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 335 reg = <0x00 0x2020000 0x00 0x100>; 336 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clock-names = "fck"; 340 clocks = <&k3_clks 189 1>; 341 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 342 }; 343 344 main_i2c3: i2c@2030000 { 345 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 346 reg = <0x00 0x2030000 0x00 0x100>; 347 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clock-names = "fck"; 351 clocks = <&k3_clks 190 1>; 352 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 353 }; 354 355 main_i2c4: i2c@2040000 { 356 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 357 reg = <0x00 0x2040000 0x00 0x100>; 358 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clock-names = "fck"; 362 clocks = <&k3_clks 191 1>; 363 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 364 }; 365 366 main_i2c5: i2c@2050000 { 367 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 368 reg = <0x00 0x2050000 0x00 0x100>; 369 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 clock-names = "fck"; 373 clocks = <&k3_clks 192 1>; 374 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 375 }; 376 377 main_i2c6: i2c@2060000 { 378 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 379 reg = <0x00 0x2060000 0x00 0x100>; 380 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clock-names = "fck"; 384 clocks = <&k3_clks 193 1>; 385 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 386 }; 387 388 main_sdhci0: mmc@4f80000 { 389 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 390 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 391 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 392 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 393 clock-names = "clk_xin", "clk_ahb"; 394 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 395 ti,otap-del-sel-legacy = <0x0>; 396 ti,otap-del-sel-mmc-hs = <0x0>; 397 ti,otap-del-sel-ddr52 = <0x6>; 398 ti,otap-del-sel-hs200 = <0x8>; 399 ti,otap-del-sel-hs400 = <0x0>; 400 ti,strobe-sel = <0x77>; 401 ti,trm-icp = <0x8>; 402 bus-width = <8>; 403 mmc-ddr-1_8v; 404 dma-coherent; 405 }; 406 407 main_sdhci1: mmc@4fb0000 { 408 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 409 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 410 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 411 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 412 clock-names = "clk_xin", "clk_ahb"; 413 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 414 ti,otap-del-sel-legacy = <0x0>; 415 ti,otap-del-sel-sd-hs = <0x0>; 416 ti,otap-del-sel-sdr12 = <0xf>; 417 ti,otap-del-sel-sdr25 = <0xf>; 418 ti,otap-del-sel-sdr50 = <0xc>; 419 ti,otap-del-sel-sdr104 = <0x5>; 420 ti,otap-del-sel-ddr50 = <0xc>; 421 no-1-8-v; 422 dma-coherent; 423 }; 424 425 usbss0: cdns-usb@4104000 { 426 compatible = "ti,j721e-usb"; 427 reg = <0x00 0x4104000 0x00 0x100>; 428 dma-coherent; 429 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 430 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 431 clock-names = "ref", "lpm"; 432 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 433 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 438 usb0: usb@6000000 { 439 compatible = "cdns,usb3"; 440 reg = <0x00 0x6000000 0x00 0x10000>, 441 <0x00 0x6010000 0x00 0x10000>, 442 <0x00 0x6020000 0x00 0x10000>; 443 reg-names = "otg", "xhci", "dev"; 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 445 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 446 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 447 interrupt-names = "host", 448 "peripheral", 449 "otg"; 450 maximum-speed = "super-speed"; 451 dr_mode = "otg"; 452 cdns,phyrst-a-enable; 453 }; 454 }; 455}; 456