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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2016,2017 IBM Corporation.
4  */
5 
6 #define pr_fmt(fmt) "xive: " fmt
7 
8 #include <linux/types.h>
9 #include <linux/irq.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/of.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/mm.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
20 
21 #include <asm/machdep.h>
22 #include <asm/prom.h>
23 #include <asm/io.h>
24 #include <asm/smp.h>
25 #include <asm/irq.h>
26 #include <asm/errno.h>
27 #include <asm/xive.h>
28 #include <asm/xive-regs.h>
29 #include <asm/hvcall.h>
30 #include <asm/svm.h>
31 #include <asm/ultravisor.h>
32 
33 #include "xive-internal.h"
34 
35 static u32 xive_queue_shift;
36 
37 struct xive_irq_bitmap {
38 	unsigned long		*bitmap;
39 	unsigned int		base;
40 	unsigned int		count;
41 	spinlock_t		lock;
42 	struct list_head	list;
43 };
44 
45 static LIST_HEAD(xive_irq_bitmaps);
46 
xive_irq_bitmap_add(int base,int count)47 static int xive_irq_bitmap_add(int base, int count)
48 {
49 	struct xive_irq_bitmap *xibm;
50 
51 	xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
52 	if (!xibm)
53 		return -ENOMEM;
54 
55 	spin_lock_init(&xibm->lock);
56 	xibm->base = base;
57 	xibm->count = count;
58 	xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
59 	if (!xibm->bitmap) {
60 		kfree(xibm);
61 		return -ENOMEM;
62 	}
63 	list_add(&xibm->list, &xive_irq_bitmaps);
64 
65 	pr_info("Using IRQ range [%x-%x]", xibm->base,
66 		xibm->base + xibm->count - 1);
67 	return 0;
68 }
69 
__xive_irq_bitmap_alloc(struct xive_irq_bitmap * xibm)70 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
71 {
72 	int irq;
73 
74 	irq = find_first_zero_bit(xibm->bitmap, xibm->count);
75 	if (irq != xibm->count) {
76 		set_bit(irq, xibm->bitmap);
77 		irq += xibm->base;
78 	} else {
79 		irq = -ENOMEM;
80 	}
81 
82 	return irq;
83 }
84 
xive_irq_bitmap_alloc(void)85 static int xive_irq_bitmap_alloc(void)
86 {
87 	struct xive_irq_bitmap *xibm;
88 	unsigned long flags;
89 	int irq = -ENOENT;
90 
91 	list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
92 		spin_lock_irqsave(&xibm->lock, flags);
93 		irq = __xive_irq_bitmap_alloc(xibm);
94 		spin_unlock_irqrestore(&xibm->lock, flags);
95 		if (irq >= 0)
96 			break;
97 	}
98 	return irq;
99 }
100 
xive_irq_bitmap_free(int irq)101 static void xive_irq_bitmap_free(int irq)
102 {
103 	unsigned long flags;
104 	struct xive_irq_bitmap *xibm;
105 
106 	list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
107 		if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
108 			spin_lock_irqsave(&xibm->lock, flags);
109 			clear_bit(irq - xibm->base, xibm->bitmap);
110 			spin_unlock_irqrestore(&xibm->lock, flags);
111 			break;
112 		}
113 	}
114 }
115 
116 
117 /* Based on the similar routines in RTAS */
plpar_busy_delay_time(long rc)118 static unsigned int plpar_busy_delay_time(long rc)
119 {
120 	unsigned int ms = 0;
121 
122 	if (H_IS_LONG_BUSY(rc)) {
123 		ms = get_longbusy_msecs(rc);
124 	} else if (rc == H_BUSY) {
125 		ms = 10; /* seems appropriate for XIVE hcalls */
126 	}
127 
128 	return ms;
129 }
130 
plpar_busy_delay(int rc)131 static unsigned int plpar_busy_delay(int rc)
132 {
133 	unsigned int ms;
134 
135 	ms = plpar_busy_delay_time(rc);
136 	if (ms)
137 		mdelay(ms);
138 
139 	return ms;
140 }
141 
142 /*
143  * Note: this call has a partition wide scope and can take a while to
144  * complete. If it returns H_LONG_BUSY_* it should be retried
145  * periodically.
146  */
plpar_int_reset(unsigned long flags)147 static long plpar_int_reset(unsigned long flags)
148 {
149 	long rc;
150 
151 	do {
152 		rc = plpar_hcall_norets(H_INT_RESET, flags);
153 	} while (plpar_busy_delay(rc));
154 
155 	if (rc)
156 		pr_err("H_INT_RESET failed %ld\n", rc);
157 
158 	return rc;
159 }
160 
plpar_int_get_source_info(unsigned long flags,unsigned long lisn,unsigned long * src_flags,unsigned long * eoi_page,unsigned long * trig_page,unsigned long * esb_shift)161 static long plpar_int_get_source_info(unsigned long flags,
162 				      unsigned long lisn,
163 				      unsigned long *src_flags,
164 				      unsigned long *eoi_page,
165 				      unsigned long *trig_page,
166 				      unsigned long *esb_shift)
167 {
168 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
169 	long rc;
170 
171 	do {
172 		rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
173 	} while (plpar_busy_delay(rc));
174 
175 	if (rc) {
176 		pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
177 		return rc;
178 	}
179 
180 	*src_flags = retbuf[0];
181 	*eoi_page  = retbuf[1];
182 	*trig_page = retbuf[2];
183 	*esb_shift = retbuf[3];
184 
185 	pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
186 		retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
187 
188 	return 0;
189 }
190 
191 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
192 #define XIVE_SRC_MASK     (1ull << (63 - 63)) /* unused */
193 
plpar_int_set_source_config(unsigned long flags,unsigned long lisn,unsigned long target,unsigned long prio,unsigned long sw_irq)194 static long plpar_int_set_source_config(unsigned long flags,
195 					unsigned long lisn,
196 					unsigned long target,
197 					unsigned long prio,
198 					unsigned long sw_irq)
199 {
200 	long rc;
201 
202 
203 	pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
204 		flags, lisn, target, prio, sw_irq);
205 
206 
207 	do {
208 		rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
209 					target, prio, sw_irq);
210 	} while (plpar_busy_delay(rc));
211 
212 	if (rc) {
213 		pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
214 		       lisn, target, prio, rc);
215 		return rc;
216 	}
217 
218 	return 0;
219 }
220 
plpar_int_get_source_config(unsigned long flags,unsigned long lisn,unsigned long * target,unsigned long * prio,unsigned long * sw_irq)221 static long plpar_int_get_source_config(unsigned long flags,
222 					unsigned long lisn,
223 					unsigned long *target,
224 					unsigned long *prio,
225 					unsigned long *sw_irq)
226 {
227 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
228 	long rc;
229 
230 	pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
231 
232 	do {
233 		rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
234 				 target, prio, sw_irq);
235 	} while (plpar_busy_delay(rc));
236 
237 	if (rc) {
238 		pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
239 		       lisn, rc);
240 		return rc;
241 	}
242 
243 	*target = retbuf[0];
244 	*prio   = retbuf[1];
245 	*sw_irq = retbuf[2];
246 
247 	pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
248 		retbuf[0], retbuf[1], retbuf[2]);
249 
250 	return 0;
251 }
252 
plpar_int_get_queue_info(unsigned long flags,unsigned long target,unsigned long priority,unsigned long * esn_page,unsigned long * esn_size)253 static long plpar_int_get_queue_info(unsigned long flags,
254 				     unsigned long target,
255 				     unsigned long priority,
256 				     unsigned long *esn_page,
257 				     unsigned long *esn_size)
258 {
259 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
260 	long rc;
261 
262 	do {
263 		rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
264 				 priority);
265 	} while (plpar_busy_delay(rc));
266 
267 	if (rc) {
268 		pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
269 		       target, priority, rc);
270 		return rc;
271 	}
272 
273 	*esn_page = retbuf[0];
274 	*esn_size = retbuf[1];
275 
276 	pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
277 		retbuf[0], retbuf[1]);
278 
279 	return 0;
280 }
281 
282 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
283 
plpar_int_set_queue_config(unsigned long flags,unsigned long target,unsigned long priority,unsigned long qpage,unsigned long qsize)284 static long plpar_int_set_queue_config(unsigned long flags,
285 				       unsigned long target,
286 				       unsigned long priority,
287 				       unsigned long qpage,
288 				       unsigned long qsize)
289 {
290 	long rc;
291 
292 	pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
293 		flags,  target, priority, qpage, qsize);
294 
295 	do {
296 		rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
297 					priority, qpage, qsize);
298 	} while (plpar_busy_delay(rc));
299 
300 	if (rc) {
301 		pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
302 		       target, priority, qpage, rc);
303 		return  rc;
304 	}
305 
306 	return 0;
307 }
308 
plpar_int_sync(unsigned long flags,unsigned long lisn)309 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
310 {
311 	long rc;
312 
313 	do {
314 		rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
315 	} while (plpar_busy_delay(rc));
316 
317 	if (rc) {
318 		pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
319 		return  rc;
320 	}
321 
322 	return 0;
323 }
324 
325 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
326 
plpar_int_esb(unsigned long flags,unsigned long lisn,unsigned long offset,unsigned long in_data,unsigned long * out_data)327 static long plpar_int_esb(unsigned long flags,
328 			  unsigned long lisn,
329 			  unsigned long offset,
330 			  unsigned long in_data,
331 			  unsigned long *out_data)
332 {
333 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
334 	long rc;
335 
336 	pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
337 		flags,  lisn, offset, in_data);
338 
339 	do {
340 		rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
341 				 in_data);
342 	} while (plpar_busy_delay(rc));
343 
344 	if (rc) {
345 		pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
346 		       lisn, offset, rc);
347 		return  rc;
348 	}
349 
350 	*out_data = retbuf[0];
351 
352 	return 0;
353 }
354 
xive_spapr_esb_rw(u32 lisn,u32 offset,u64 data,bool write)355 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
356 {
357 	unsigned long read_data;
358 	long rc;
359 
360 	rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
361 			   lisn, offset, data, &read_data);
362 	if (rc)
363 		return -1;
364 
365 	return write ? 0 : read_data;
366 }
367 
368 #define XIVE_SRC_H_INT_ESB     (1ull << (63 - 60))
369 #define XIVE_SRC_LSI           (1ull << (63 - 61))
370 #define XIVE_SRC_TRIGGER       (1ull << (63 - 62))
371 #define XIVE_SRC_STORE_EOI     (1ull << (63 - 63))
372 
xive_spapr_populate_irq_data(u32 hw_irq,struct xive_irq_data * data)373 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
374 {
375 	long rc;
376 	unsigned long flags;
377 	unsigned long eoi_page;
378 	unsigned long trig_page;
379 	unsigned long esb_shift;
380 
381 	memset(data, 0, sizeof(*data));
382 
383 	rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
384 				       &esb_shift);
385 	if (rc)
386 		return  -EINVAL;
387 
388 	if (flags & XIVE_SRC_H_INT_ESB)
389 		data->flags  |= XIVE_IRQ_FLAG_H_INT_ESB;
390 	if (flags & XIVE_SRC_STORE_EOI)
391 		data->flags  |= XIVE_IRQ_FLAG_STORE_EOI;
392 	if (flags & XIVE_SRC_LSI)
393 		data->flags  |= XIVE_IRQ_FLAG_LSI;
394 	data->eoi_page  = eoi_page;
395 	data->esb_shift = esb_shift;
396 	data->trig_page = trig_page;
397 
398 	data->hw_irq = hw_irq;
399 
400 	/*
401 	 * No chip-id for the sPAPR backend. This has an impact how we
402 	 * pick a target. See xive_pick_irq_target().
403 	 */
404 	data->src_chip = XIVE_INVALID_CHIP_ID;
405 
406 	/*
407 	 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
408 	 * be used for interrupt management. Skip the remapping of the
409 	 * ESB pages which are not available.
410 	 */
411 	if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
412 		return 0;
413 
414 	data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
415 	if (!data->eoi_mmio) {
416 		pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
417 		return -ENOMEM;
418 	}
419 
420 	/* Full function page supports trigger */
421 	if (flags & XIVE_SRC_TRIGGER) {
422 		data->trig_mmio = data->eoi_mmio;
423 		return 0;
424 	}
425 
426 	data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
427 	if (!data->trig_mmio) {
428 		iounmap(data->eoi_mmio);
429 		pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
430 		return -ENOMEM;
431 	}
432 	return 0;
433 }
434 
xive_spapr_configure_irq(u32 hw_irq,u32 target,u8 prio,u32 sw_irq)435 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
436 {
437 	long rc;
438 
439 	rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
440 					 prio, sw_irq);
441 
442 	return rc == 0 ? 0 : -ENXIO;
443 }
444 
xive_spapr_get_irq_config(u32 hw_irq,u32 * target,u8 * prio,u32 * sw_irq)445 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
446 				     u32 *sw_irq)
447 {
448 	long rc;
449 	unsigned long h_target;
450 	unsigned long h_prio;
451 	unsigned long h_sw_irq;
452 
453 	rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
454 					 &h_sw_irq);
455 
456 	*target = h_target;
457 	*prio = h_prio;
458 	*sw_irq = h_sw_irq;
459 
460 	return rc == 0 ? 0 : -ENXIO;
461 }
462 
463 /* This can be called multiple time to change a queue configuration */
xive_spapr_configure_queue(u32 target,struct xive_q * q,u8 prio,__be32 * qpage,u32 order)464 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
465 				   __be32 *qpage, u32 order)
466 {
467 	s64 rc = 0;
468 	unsigned long esn_page;
469 	unsigned long esn_size;
470 	u64 flags, qpage_phys;
471 
472 	/* If there's an actual queue page, clean it */
473 	if (order) {
474 		if (WARN_ON(!qpage))
475 			return -EINVAL;
476 		qpage_phys = __pa(qpage);
477 	} else {
478 		qpage_phys = 0;
479 	}
480 
481 	/* Initialize the rest of the fields */
482 	q->msk = order ? ((1u << (order - 2)) - 1) : 0;
483 	q->idx = 0;
484 	q->toggle = 0;
485 
486 	rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
487 	if (rc) {
488 		pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
489 		       target, prio);
490 		rc = -EIO;
491 		goto fail;
492 	}
493 
494 	/* TODO: add support for the notification page */
495 	q->eoi_phys = esn_page;
496 
497 	/* Default is to always notify */
498 	flags = XIVE_EQ_ALWAYS_NOTIFY;
499 
500 	/* Configure and enable the queue in HW */
501 	rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
502 	if (rc) {
503 		pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
504 		       target, prio);
505 		rc = -EIO;
506 	} else {
507 		q->qpage = qpage;
508 		if (is_secure_guest())
509 			uv_share_page(PHYS_PFN(qpage_phys),
510 					1 << xive_alloc_order(order));
511 	}
512 fail:
513 	return rc;
514 }
515 
xive_spapr_setup_queue(unsigned int cpu,struct xive_cpu * xc,u8 prio)516 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
517 				  u8 prio)
518 {
519 	struct xive_q *q = &xc->queue[prio];
520 	__be32 *qpage;
521 
522 	qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
523 	if (IS_ERR(qpage))
524 		return PTR_ERR(qpage);
525 
526 	return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
527 					  q, prio, qpage, xive_queue_shift);
528 }
529 
xive_spapr_cleanup_queue(unsigned int cpu,struct xive_cpu * xc,u8 prio)530 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
531 				  u8 prio)
532 {
533 	struct xive_q *q = &xc->queue[prio];
534 	unsigned int alloc_order;
535 	long rc;
536 	int hw_cpu = get_hard_smp_processor_id(cpu);
537 
538 	rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
539 	if (rc)
540 		pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
541 		       hw_cpu, prio);
542 
543 	alloc_order = xive_alloc_order(xive_queue_shift);
544 	if (is_secure_guest())
545 		uv_unshare_page(PHYS_PFN(__pa(q->qpage)), 1 << alloc_order);
546 	free_pages((unsigned long)q->qpage, alloc_order);
547 	q->qpage = NULL;
548 }
549 
xive_spapr_match(struct device_node * node)550 static bool xive_spapr_match(struct device_node *node)
551 {
552 	/* Ignore cascaded controllers for the moment */
553 	return 1;
554 }
555 
556 #ifdef CONFIG_SMP
xive_spapr_get_ipi(unsigned int cpu,struct xive_cpu * xc)557 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
558 {
559 	int irq = xive_irq_bitmap_alloc();
560 
561 	if (irq < 0) {
562 		pr_err("Failed to allocate IPI on CPU %d\n", cpu);
563 		return -ENXIO;
564 	}
565 
566 	xc->hw_ipi = irq;
567 	return 0;
568 }
569 
xive_spapr_put_ipi(unsigned int cpu,struct xive_cpu * xc)570 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
571 {
572 	if (xc->hw_ipi == XIVE_BAD_IRQ)
573 		return;
574 
575 	xive_irq_bitmap_free(xc->hw_ipi);
576 	xc->hw_ipi = XIVE_BAD_IRQ;
577 }
578 #endif /* CONFIG_SMP */
579 
xive_spapr_shutdown(void)580 static void xive_spapr_shutdown(void)
581 {
582 	plpar_int_reset(0);
583 }
584 
585 /*
586  * Perform an "ack" cycle on the current thread. Grab the pending
587  * active priorities and update the CPPR to the most favored one.
588  */
xive_spapr_update_pending(struct xive_cpu * xc)589 static void xive_spapr_update_pending(struct xive_cpu *xc)
590 {
591 	u8 nsr, cppr;
592 	u16 ack;
593 
594 	/*
595 	 * Perform the "Acknowledge O/S to Register" cycle.
596 	 *
597 	 * Let's speedup the access to the TIMA using the raw I/O
598 	 * accessor as we don't need the synchronisation routine of
599 	 * the higher level ones
600 	 */
601 	ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
602 
603 	/* Synchronize subsequent queue accesses */
604 	mb();
605 
606 	/*
607 	 * Grab the CPPR and the "NSR" field which indicates the source
608 	 * of the interrupt (if any)
609 	 */
610 	cppr = ack & 0xff;
611 	nsr = ack >> 8;
612 
613 	if (nsr & TM_QW1_NSR_EO) {
614 		if (cppr == 0xff)
615 			return;
616 		/* Mark the priority pending */
617 		xc->pending_prio |= 1 << cppr;
618 
619 		/*
620 		 * A new interrupt should never have a CPPR less favored
621 		 * than our current one.
622 		 */
623 		if (cppr >= xc->cppr)
624 			pr_err("CPU %d odd ack CPPR, got %d at %d\n",
625 			       smp_processor_id(), cppr, xc->cppr);
626 
627 		/* Update our idea of what the CPPR is */
628 		xc->cppr = cppr;
629 	}
630 }
631 
xive_spapr_eoi(u32 hw_irq)632 static void xive_spapr_eoi(u32 hw_irq)
633 {
634 	/* Not used */;
635 }
636 
xive_spapr_setup_cpu(unsigned int cpu,struct xive_cpu * xc)637 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
638 {
639 	/* Only some debug on the TIMA settings */
640 	pr_debug("(HW value: %08x %08x %08x)\n",
641 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
642 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
643 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
644 }
645 
xive_spapr_teardown_cpu(unsigned int cpu,struct xive_cpu * xc)646 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
647 {
648 	/* Nothing to do */;
649 }
650 
xive_spapr_sync_source(u32 hw_irq)651 static void xive_spapr_sync_source(u32 hw_irq)
652 {
653 	/* Specs are unclear on what this is doing */
654 	plpar_int_sync(0, hw_irq);
655 }
656 
xive_spapr_debug_show(struct seq_file * m,void * private)657 static int xive_spapr_debug_show(struct seq_file *m, void *private)
658 {
659 	struct xive_irq_bitmap *xibm;
660 	char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
661 
662 	if (!buf)
663 		return -ENOMEM;
664 
665 	list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
666 		memset(buf, 0, PAGE_SIZE);
667 		bitmap_print_to_pagebuf(true, buf, xibm->bitmap, xibm->count);
668 		seq_printf(m, "bitmap #%d: %s", xibm->count, buf);
669 	}
670 	kfree(buf);
671 
672 	return 0;
673 }
674 
675 static const struct xive_ops xive_spapr_ops = {
676 	.populate_irq_data	= xive_spapr_populate_irq_data,
677 	.configure_irq		= xive_spapr_configure_irq,
678 	.get_irq_config		= xive_spapr_get_irq_config,
679 	.setup_queue		= xive_spapr_setup_queue,
680 	.cleanup_queue		= xive_spapr_cleanup_queue,
681 	.match			= xive_spapr_match,
682 	.shutdown		= xive_spapr_shutdown,
683 	.update_pending		= xive_spapr_update_pending,
684 	.eoi			= xive_spapr_eoi,
685 	.setup_cpu		= xive_spapr_setup_cpu,
686 	.teardown_cpu		= xive_spapr_teardown_cpu,
687 	.sync_source		= xive_spapr_sync_source,
688 	.esb_rw			= xive_spapr_esb_rw,
689 #ifdef CONFIG_SMP
690 	.get_ipi		= xive_spapr_get_ipi,
691 	.put_ipi		= xive_spapr_put_ipi,
692 	.debug_show		= xive_spapr_debug_show,
693 #endif /* CONFIG_SMP */
694 	.name			= "spapr",
695 };
696 
697 /*
698  * get max priority from "/ibm,plat-res-int-priorities"
699  */
xive_get_max_prio(u8 * max_prio)700 static bool xive_get_max_prio(u8 *max_prio)
701 {
702 	struct device_node *rootdn;
703 	const __be32 *reg;
704 	u32 len;
705 	int prio, found;
706 
707 	rootdn = of_find_node_by_path("/");
708 	if (!rootdn) {
709 		pr_err("not root node found !\n");
710 		return false;
711 	}
712 
713 	reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
714 	of_node_put(rootdn);
715 	if (!reg) {
716 		pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
717 		return false;
718 	}
719 
720 	if (len % (2 * sizeof(u32)) != 0) {
721 		pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
722 		return false;
723 	}
724 
725 	/* HW supports priorities in the range [0-7] and 0xFF is a
726 	 * wildcard priority used to mask. We scan the ranges reserved
727 	 * by the hypervisor to find the lowest priority we can use.
728 	 */
729 	found = 0xFF;
730 	for (prio = 0; prio < 8; prio++) {
731 		int reserved = 0;
732 		int i;
733 
734 		for (i = 0; i < len / (2 * sizeof(u32)); i++) {
735 			int base  = be32_to_cpu(reg[2 * i]);
736 			int range = be32_to_cpu(reg[2 * i + 1]);
737 
738 			if (prio >= base && prio < base + range)
739 				reserved++;
740 		}
741 
742 		if (!reserved)
743 			found = prio;
744 	}
745 
746 	if (found == 0xFF) {
747 		pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
748 		return false;
749 	}
750 
751 	*max_prio = found;
752 	return true;
753 }
754 
get_vec5_feature(unsigned int index)755 static const u8 *get_vec5_feature(unsigned int index)
756 {
757 	unsigned long root, chosen;
758 	int size;
759 	const u8 *vec5;
760 
761 	root = of_get_flat_dt_root();
762 	chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
763 	if (chosen == -FDT_ERR_NOTFOUND)
764 		return NULL;
765 
766 	vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
767 	if (!vec5)
768 		return NULL;
769 
770 	if (size <= index)
771 		return NULL;
772 
773 	return vec5 + index;
774 }
775 
xive_spapr_disabled(void)776 static bool __init xive_spapr_disabled(void)
777 {
778 	const u8 *vec5_xive;
779 
780 	vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
781 	if (vec5_xive) {
782 		u8 val;
783 
784 		val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
785 		switch (val) {
786 		case OV5_FEAT(OV5_XIVE_EITHER):
787 		case OV5_FEAT(OV5_XIVE_LEGACY):
788 			break;
789 		case OV5_FEAT(OV5_XIVE_EXPLOIT):
790 			/* Hypervisor only supports XIVE */
791 			if (xive_cmdline_disabled)
792 				pr_warn("WARNING: Ignoring cmdline option xive=off\n");
793 			return false;
794 		default:
795 			pr_warn("%s: Unknown xive support option: 0x%x\n",
796 				__func__, val);
797 			break;
798 		}
799 	}
800 
801 	return xive_cmdline_disabled;
802 }
803 
xive_spapr_init(void)804 bool __init xive_spapr_init(void)
805 {
806 	struct device_node *np;
807 	struct resource r;
808 	void __iomem *tima;
809 	struct property *prop;
810 	u8 max_prio;
811 	u32 val;
812 	u32 len;
813 	const __be32 *reg;
814 	int i;
815 
816 	if (xive_spapr_disabled())
817 		return false;
818 
819 	pr_devel("%s()\n", __func__);
820 	np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
821 	if (!np) {
822 		pr_devel("not found !\n");
823 		return false;
824 	}
825 	pr_devel("Found %s\n", np->full_name);
826 
827 	/* Resource 1 is the OS ring TIMA */
828 	if (of_address_to_resource(np, 1, &r)) {
829 		pr_err("Failed to get thread mgmnt area resource\n");
830 		return false;
831 	}
832 	tima = ioremap(r.start, resource_size(&r));
833 	if (!tima) {
834 		pr_err("Failed to map thread mgmnt area\n");
835 		return false;
836 	}
837 
838 	if (!xive_get_max_prio(&max_prio))
839 		return false;
840 
841 	/* Feed the IRQ number allocator with the ranges given in the DT */
842 	reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
843 	if (!reg) {
844 		pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
845 		return false;
846 	}
847 
848 	if (len % (2 * sizeof(u32)) != 0) {
849 		pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
850 		return false;
851 	}
852 
853 	for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
854 		xive_irq_bitmap_add(be32_to_cpu(reg[0]),
855 				    be32_to_cpu(reg[1]));
856 
857 	/* Iterate the EQ sizes and pick one */
858 	of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
859 		xive_queue_shift = val;
860 		if (val == PAGE_SHIFT)
861 			break;
862 	}
863 
864 	/* Initialize XIVE core with our backend */
865 	if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
866 		return false;
867 
868 	pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
869 	return true;
870 }
871 
872 machine_arch_initcall(pseries, xive_core_debug_init);
873