1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef ADF_DH895x_HW_DATA_H_ 4 #define ADF_DH895x_HW_DATA_H_ 5 6 /* PCIe configuration space */ 7 #define ADF_DH895XCC_SRAM_BAR 0 8 #define ADF_DH895XCC_PMISC_BAR 1 9 #define ADF_DH895XCC_ETR_BAR 2 10 #define ADF_DH895XCC_RX_RINGS_OFFSET 8 11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF 12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000 13 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20 14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0 15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1 16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2 17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3 18 #define ADF_DH895XCC_MAX_ACCELERATORS 6 19 #define ADF_DH895XCC_MAX_ACCELENGINES 12 20 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13 21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F 22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF 23 #define ADF_DH895XCC_ETR_MAX_BANKS 32 24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 25 #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 26 #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF 27 #define ADF_DH895XCC_SMIA1_MASK 0x1 28 /* Error detection and correction */ 29 #define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 30 #define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 31 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28) 32 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 33 #define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18) 34 #define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10) 35 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3) 36 37 #define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04)) 38 #define ADF_DH895XCC_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i) * 0x04)) 39 /* FW names */ 40 #define ADF_DH895XCC_FW "qat_895xcc.bin" 41 #define ADF_DH895XCC_MMP "qat_895xcc_mmp.bin" 42 43 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 44 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 45 #endif 46