1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_gfx.h"
32 #include "soc15.h"
33 #include "soc15d.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_pm.h"
36
37 #include "gc/gc_9_0_offset.h"
38 #include "gc/gc_9_0_sh_mask.h"
39
40 #include "vega10_enum.h"
41 #include "hdp/hdp_4_0_offset.h"
42
43 #include "soc15_common.h"
44 #include "clearstate_gfx9.h"
45 #include "v9_structs.h"
46
47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
48
49 #include "amdgpu_ras.h"
50
51 #include "gfx_v9_4.h"
52 #include "gfx_v9_0.h"
53
54 #include "asic_reg/pwr/pwr_10_0_offset.h"
55 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
56
57 #define GFX9_NUM_GFX_RINGS 1
58 #define GFX9_MEC_HPD_SIZE 4096
59 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
60 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
61
62 #define mmGCEA_PROBE_MAP 0x070c
63 #define mmGCEA_PROBE_MAP_BASE_IDX 0
64
65 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
66 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
67 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
68 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
69 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
70 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
71
72 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
73 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
74 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
75 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
76 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
77 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
78
79 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
80 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
81 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
82 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
83 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
84 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
85
86 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
87 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
88 MODULE_FIRMWARE("amdgpu/raven_me.bin");
89 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
90 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
91 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
92
93 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
94 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
95 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
96 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
97 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
98 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
99 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
100
101 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
102 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
103 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
104 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
105 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
106 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
107 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
108
109 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
110 MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
111 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
112
113 MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
114 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
115 MODULE_FIRMWARE("amdgpu/renoir_me.bin");
116 MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
117 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
118 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
119
120 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
121 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
122 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
123 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
124 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
125 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
126
127 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03
128 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
129 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04
130 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0
131 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09
132 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0
133 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a
134 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0
135 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b
136 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0
137 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c
138 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0
139
140 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025
141 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1
142 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026
143 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1
144
145 enum ta_ras_gfx_subblock {
146 /*CPC*/
147 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
148 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
149 TA_RAS_BLOCK__GFX_CPC_UCODE,
150 TA_RAS_BLOCK__GFX_DC_STATE_ME1,
151 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
152 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
153 TA_RAS_BLOCK__GFX_DC_STATE_ME2,
154 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
155 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
156 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
157 /* CPF*/
158 TA_RAS_BLOCK__GFX_CPF_INDEX_START,
159 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
160 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
161 TA_RAS_BLOCK__GFX_CPF_TAG,
162 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
163 /* CPG*/
164 TA_RAS_BLOCK__GFX_CPG_INDEX_START,
165 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
166 TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
167 TA_RAS_BLOCK__GFX_CPG_TAG,
168 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
169 /* GDS*/
170 TA_RAS_BLOCK__GFX_GDS_INDEX_START,
171 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
172 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
173 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
174 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
175 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
176 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
177 /* SPI*/
178 TA_RAS_BLOCK__GFX_SPI_SR_MEM,
179 /* SQ*/
180 TA_RAS_BLOCK__GFX_SQ_INDEX_START,
181 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
182 TA_RAS_BLOCK__GFX_SQ_LDS_D,
183 TA_RAS_BLOCK__GFX_SQ_LDS_I,
184 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
185 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
186 /* SQC (3 ranges)*/
187 TA_RAS_BLOCK__GFX_SQC_INDEX_START,
188 /* SQC range 0*/
189 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
190 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
191 TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
192 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
193 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
194 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
195 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
196 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
197 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
198 TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
199 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
200 /* SQC range 1*/
201 TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
202 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
203 TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
204 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
205 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
206 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
207 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
208 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
209 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
210 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
211 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
212 TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
214 /* SQC range 2*/
215 TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
216 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
217 TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
218 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
219 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
220 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
221 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
222 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
223 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
224 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
225 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
226 TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
227 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
228 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
229 /* TA*/
230 TA_RAS_BLOCK__GFX_TA_INDEX_START,
231 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
232 TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
233 TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
234 TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
235 TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
236 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
237 /* TCA*/
238 TA_RAS_BLOCK__GFX_TCA_INDEX_START,
239 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
240 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
241 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
242 /* TCC (5 sub-ranges)*/
243 TA_RAS_BLOCK__GFX_TCC_INDEX_START,
244 /* TCC range 0*/
245 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
246 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
247 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
248 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
249 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
250 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
251 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
252 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
253 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
254 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
255 /* TCC range 1*/
256 TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
257 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
258 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
259 TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
260 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
261 /* TCC range 2*/
262 TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
263 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
264 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
265 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
266 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
267 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
268 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
269 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
270 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
271 TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
272 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
273 /* TCC range 3*/
274 TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
275 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
276 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
277 TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
278 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
279 /* TCC range 4*/
280 TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
281 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
282 TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
283 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
284 TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
285 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
286 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
287 /* TCI*/
288 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
289 /* TCP*/
290 TA_RAS_BLOCK__GFX_TCP_INDEX_START,
291 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
292 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
293 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
294 TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
295 TA_RAS_BLOCK__GFX_TCP_DB_RAM,
296 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
297 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
298 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
299 /* TD*/
300 TA_RAS_BLOCK__GFX_TD_INDEX_START,
301 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
302 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
303 TA_RAS_BLOCK__GFX_TD_CS_FIFO,
304 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
305 /* EA (3 sub-ranges)*/
306 TA_RAS_BLOCK__GFX_EA_INDEX_START,
307 /* EA range 0*/
308 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
309 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
310 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
311 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
312 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
313 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
314 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
315 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
316 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
317 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
318 /* EA range 1*/
319 TA_RAS_BLOCK__GFX_EA_INDEX1_START,
320 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
321 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
322 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
323 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
324 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
325 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
326 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
327 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
328 /* EA range 2*/
329 TA_RAS_BLOCK__GFX_EA_INDEX2_START,
330 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
331 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
332 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
333 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
334 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
335 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
336 /* UTC VM L2 bank*/
337 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
338 /* UTC VM walker*/
339 TA_RAS_BLOCK__UTC_VML2_WALKER,
340 /* UTC ATC L2 2MB cache*/
341 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
342 /* UTC ATC L2 4KB cache*/
343 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
344 TA_RAS_BLOCK__GFX_MAX
345 };
346
347 struct ras_gfx_subblock {
348 unsigned char *name;
349 int ta_subblock;
350 int hw_supported_error_type;
351 int sw_supported_error_type;
352 };
353
354 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \
355 [AMDGPU_RAS_BLOCK__##subblock] = { \
356 #subblock, \
357 TA_RAS_BLOCK__##subblock, \
358 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \
359 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \
360 }
361
362 static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
363 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
364 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
365 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
366 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
367 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
368 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
369 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
370 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
371 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
372 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
373 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
374 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
375 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
376 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
377 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
378 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
379 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
380 0),
381 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
382 0),
383 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
384 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
385 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
386 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
387 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
388 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
390 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
391 0, 0),
392 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
393 0),
394 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
395 0, 0),
396 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
397 0),
398 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
399 0, 0),
400 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
401 0),
402 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
403 1),
404 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
405 0, 0, 0),
406 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
407 0),
408 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
409 0),
410 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
411 0),
412 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
413 0),
414 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
415 0),
416 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
417 0, 0),
418 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
419 0),
420 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
421 0),
422 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
423 0, 0, 0),
424 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
425 0),
426 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
427 0),
428 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
429 0),
430 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
431 0),
432 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
433 0),
434 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
435 0, 0),
436 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
437 0),
438 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
439 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
440 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
441 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
442 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
443 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
444 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
446 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
447 1),
448 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
449 1),
450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
451 1),
452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
453 0),
454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
455 0),
456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
464 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
466 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
468 0),
469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
470 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
471 0),
472 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
473 0, 0),
474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
475 0),
476 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
477 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
478 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
479 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
480 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
481 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
482 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
483 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
484 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
485 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
486 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
499 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
500 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
501 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
502 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
503 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
506 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
507 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
508 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
509 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
510 };
511
512 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
513 {
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
534 };
535
536 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
537 {
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
556 };
557
558 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
559 {
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
571 };
572
573 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
574 {
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
599 };
600
601 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
602 {
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
610 };
611
612 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
613 {
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
633 };
634
635 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
636 {
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
649 };
650
651 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
652 {
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
656 };
657
658 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
659 {
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
676 };
677
678 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
679 {
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
693 };
694
695 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
696 {
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
708 };
709
710 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
711 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
712 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
713 };
714
715 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
716 {
717 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
718 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
719 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
720 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
721 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
722 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
723 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
724 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
725 };
726
727 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
728 {
729 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
730 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
731 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
732 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
733 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
734 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
735 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
736 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
737 };
738
gfx_v9_0_rlcg_wreg(struct amdgpu_device * adev,u32 offset,u32 v)739 static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
740 {
741 static void *scratch_reg0;
742 static void *scratch_reg1;
743 static void *scratch_reg2;
744 static void *scratch_reg3;
745 static void *spare_int;
746 static uint32_t grbm_cntl;
747 static uint32_t grbm_idx;
748
749 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
750 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
751 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
752 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
753 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
754
755 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
756 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
757
758 if (amdgpu_sriov_runtime(adev)) {
759 pr_err("shouldn't call rlcg write register during runtime\n");
760 return;
761 }
762
763 if (offset == grbm_cntl || offset == grbm_idx) {
764 if (offset == grbm_cntl)
765 writel(v, scratch_reg2);
766 else if (offset == grbm_idx)
767 writel(v, scratch_reg3);
768
769 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
770 } else {
771 uint32_t i = 0;
772 uint32_t retries = 50000;
773
774 writel(v, scratch_reg0);
775 writel(offset | 0x80000000, scratch_reg1);
776 writel(1, spare_int);
777 for (i = 0; i < retries; i++) {
778 u32 tmp;
779
780 tmp = readl(scratch_reg1);
781 if (!(tmp & 0x80000000))
782 break;
783
784 udelay(10);
785 }
786 if (i >= retries)
787 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
788 }
789
790 }
791
792 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
793 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
794 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
795 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
796
797 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
798 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
799 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
800 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
801 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
802 struct amdgpu_cu_info *cu_info);
803 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
804 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
805 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
806 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
807 void *ras_error_status);
808 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
809 void *inject_if);
810 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
811
gfx_v9_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)812 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
813 uint64_t queue_mask)
814 {
815 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
816 amdgpu_ring_write(kiq_ring,
817 PACKET3_SET_RESOURCES_VMID_MASK(0) |
818 /* vmid_mask:0* queue_type:0 (KIQ) */
819 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
820 amdgpu_ring_write(kiq_ring,
821 lower_32_bits(queue_mask)); /* queue mask lo */
822 amdgpu_ring_write(kiq_ring,
823 upper_32_bits(queue_mask)); /* queue mask hi */
824 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
825 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
826 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
827 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
828 }
829
gfx_v9_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)830 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
831 struct amdgpu_ring *ring)
832 {
833 struct amdgpu_device *adev = kiq_ring->adev;
834 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
835 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
836 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
837
838 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
839 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
840 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
841 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
842 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
843 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
844 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
845 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
846 /*queue_type: normal compute queue */
847 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
848 /* alloc format: all_on_one_pipe */
849 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
850 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
851 /* num_queues: must be 1 */
852 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
853 amdgpu_ring_write(kiq_ring,
854 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
855 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
856 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
857 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
858 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
859 }
860
gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)861 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
862 struct amdgpu_ring *ring,
863 enum amdgpu_unmap_queues_action action,
864 u64 gpu_addr, u64 seq)
865 {
866 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
867
868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
869 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
870 PACKET3_UNMAP_QUEUES_ACTION(action) |
871 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
872 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
873 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
874 amdgpu_ring_write(kiq_ring,
875 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
876
877 if (action == PREEMPT_QUEUES_NO_UNMAP) {
878 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
879 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
880 amdgpu_ring_write(kiq_ring, seq);
881 } else {
882 amdgpu_ring_write(kiq_ring, 0);
883 amdgpu_ring_write(kiq_ring, 0);
884 amdgpu_ring_write(kiq_ring, 0);
885 }
886 }
887
gfx_v9_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)888 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
889 struct amdgpu_ring *ring,
890 u64 addr,
891 u64 seq)
892 {
893 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
894
895 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
896 amdgpu_ring_write(kiq_ring,
897 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
898 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
899 PACKET3_QUERY_STATUS_COMMAND(2));
900 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
901 amdgpu_ring_write(kiq_ring,
902 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
903 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
904 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
905 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
906 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
907 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
908 }
909
gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)910 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
911 uint16_t pasid, uint32_t flush_type,
912 bool all_hub)
913 {
914 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
915 amdgpu_ring_write(kiq_ring,
916 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
917 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
918 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
919 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
920 }
921
922 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {
923 .kiq_set_resources = gfx_v9_0_kiq_set_resources,
924 .kiq_map_queues = gfx_v9_0_kiq_map_queues,
925 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,
926 .kiq_query_status = gfx_v9_0_kiq_query_status,
927 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,
928 .set_resources_size = 8,
929 .map_queues_size = 7,
930 .unmap_queues_size = 6,
931 .query_status_size = 7,
932 .invalidate_tlbs_size = 2,
933 };
934
gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)935 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
936 {
937 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs;
938 }
939
gfx_v9_0_init_golden_registers(struct amdgpu_device * adev)940 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
941 {
942 switch (adev->asic_type) {
943 case CHIP_VEGA10:
944 soc15_program_register_sequence(adev,
945 golden_settings_gc_9_0,
946 ARRAY_SIZE(golden_settings_gc_9_0));
947 soc15_program_register_sequence(adev,
948 golden_settings_gc_9_0_vg10,
949 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
950 break;
951 case CHIP_VEGA12:
952 soc15_program_register_sequence(adev,
953 golden_settings_gc_9_2_1,
954 ARRAY_SIZE(golden_settings_gc_9_2_1));
955 soc15_program_register_sequence(adev,
956 golden_settings_gc_9_2_1_vg12,
957 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
958 break;
959 case CHIP_VEGA20:
960 soc15_program_register_sequence(adev,
961 golden_settings_gc_9_0,
962 ARRAY_SIZE(golden_settings_gc_9_0));
963 soc15_program_register_sequence(adev,
964 golden_settings_gc_9_0_vg20,
965 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
966 break;
967 case CHIP_ARCTURUS:
968 soc15_program_register_sequence(adev,
969 golden_settings_gc_9_4_1_arct,
970 ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
971 break;
972 case CHIP_RAVEN:
973 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
974 ARRAY_SIZE(golden_settings_gc_9_1));
975 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
976 soc15_program_register_sequence(adev,
977 golden_settings_gc_9_1_rv2,
978 ARRAY_SIZE(golden_settings_gc_9_1_rv2));
979 else
980 soc15_program_register_sequence(adev,
981 golden_settings_gc_9_1_rv1,
982 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
983 break;
984 case CHIP_RENOIR:
985 soc15_program_register_sequence(adev,
986 golden_settings_gc_9_1_rn,
987 ARRAY_SIZE(golden_settings_gc_9_1_rn));
988 return; /* for renoir, don't need common goldensetting */
989 default:
990 break;
991 }
992
993 if (adev->asic_type != CHIP_ARCTURUS)
994 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
995 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
996 }
997
gfx_v9_0_scratch_init(struct amdgpu_device * adev)998 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
999 {
1000 adev->gfx.scratch.num_reg = 8;
1001 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
1002 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1003 }
1004
gfx_v9_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)1005 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
1006 bool wc, uint32_t reg, uint32_t val)
1007 {
1008 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1009 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
1010 WRITE_DATA_DST_SEL(0) |
1011 (wc ? WR_CONFIRM : 0));
1012 amdgpu_ring_write(ring, reg);
1013 amdgpu_ring_write(ring, 0);
1014 amdgpu_ring_write(ring, val);
1015 }
1016
gfx_v9_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)1017 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
1018 int mem_space, int opt, uint32_t addr0,
1019 uint32_t addr1, uint32_t ref, uint32_t mask,
1020 uint32_t inv)
1021 {
1022 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1023 amdgpu_ring_write(ring,
1024 /* memory (1) or register (0) */
1025 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
1026 WAIT_REG_MEM_OPERATION(opt) | /* wait */
1027 WAIT_REG_MEM_FUNCTION(3) | /* equal */
1028 WAIT_REG_MEM_ENGINE(eng_sel)));
1029
1030 if (mem_space)
1031 BUG_ON(addr0 & 0x3); /* Dword align */
1032 amdgpu_ring_write(ring, addr0);
1033 amdgpu_ring_write(ring, addr1);
1034 amdgpu_ring_write(ring, ref);
1035 amdgpu_ring_write(ring, mask);
1036 amdgpu_ring_write(ring, inv); /* poll interval */
1037 }
1038
gfx_v9_0_ring_test_ring(struct amdgpu_ring * ring)1039 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
1040 {
1041 struct amdgpu_device *adev = ring->adev;
1042 uint32_t scratch;
1043 uint32_t tmp = 0;
1044 unsigned i;
1045 int r;
1046
1047 r = amdgpu_gfx_scratch_get(adev, &scratch);
1048 if (r)
1049 return r;
1050
1051 WREG32(scratch, 0xCAFEDEAD);
1052 r = amdgpu_ring_alloc(ring, 3);
1053 if (r)
1054 goto error_free_scratch;
1055
1056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1057 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1058 amdgpu_ring_write(ring, 0xDEADBEEF);
1059 amdgpu_ring_commit(ring);
1060
1061 for (i = 0; i < adev->usec_timeout; i++) {
1062 tmp = RREG32(scratch);
1063 if (tmp == 0xDEADBEEF)
1064 break;
1065 udelay(1);
1066 }
1067
1068 if (i >= adev->usec_timeout)
1069 r = -ETIMEDOUT;
1070
1071 error_free_scratch:
1072 amdgpu_gfx_scratch_free(adev, scratch);
1073 return r;
1074 }
1075
gfx_v9_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)1076 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1077 {
1078 struct amdgpu_device *adev = ring->adev;
1079 struct amdgpu_ib ib;
1080 struct dma_fence *f = NULL;
1081
1082 unsigned index;
1083 uint64_t gpu_addr;
1084 uint32_t tmp;
1085 long r;
1086
1087 r = amdgpu_device_wb_get(adev, &index);
1088 if (r)
1089 return r;
1090
1091 gpu_addr = adev->wb.gpu_addr + (index * 4);
1092 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
1093 memset(&ib, 0, sizeof(ib));
1094 r = amdgpu_ib_get(adev, NULL, 16,
1095 AMDGPU_IB_POOL_DIRECT, &ib);
1096 if (r)
1097 goto err1;
1098
1099 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
1100 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1101 ib.ptr[2] = lower_32_bits(gpu_addr);
1102 ib.ptr[3] = upper_32_bits(gpu_addr);
1103 ib.ptr[4] = 0xDEADBEEF;
1104 ib.length_dw = 5;
1105
1106 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1107 if (r)
1108 goto err2;
1109
1110 r = dma_fence_wait_timeout(f, false, timeout);
1111 if (r == 0) {
1112 r = -ETIMEDOUT;
1113 goto err2;
1114 } else if (r < 0) {
1115 goto err2;
1116 }
1117
1118 tmp = adev->wb.wb[index];
1119 if (tmp == 0xDEADBEEF)
1120 r = 0;
1121 else
1122 r = -EINVAL;
1123
1124 err2:
1125 amdgpu_ib_free(adev, &ib, NULL);
1126 dma_fence_put(f);
1127 err1:
1128 amdgpu_device_wb_free(adev, index);
1129 return r;
1130 }
1131
1132
gfx_v9_0_free_microcode(struct amdgpu_device * adev)1133 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
1134 {
1135 release_firmware(adev->gfx.pfp_fw);
1136 adev->gfx.pfp_fw = NULL;
1137 release_firmware(adev->gfx.me_fw);
1138 adev->gfx.me_fw = NULL;
1139 release_firmware(adev->gfx.ce_fw);
1140 adev->gfx.ce_fw = NULL;
1141 release_firmware(adev->gfx.rlc_fw);
1142 adev->gfx.rlc_fw = NULL;
1143 release_firmware(adev->gfx.mec_fw);
1144 adev->gfx.mec_fw = NULL;
1145 release_firmware(adev->gfx.mec2_fw);
1146 adev->gfx.mec2_fw = NULL;
1147
1148 kfree(adev->gfx.rlc.register_list_format);
1149 }
1150
gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device * adev)1151 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
1152 {
1153 const struct rlc_firmware_header_v2_1 *rlc_hdr;
1154
1155 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1156 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
1157 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
1158 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
1159 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
1160 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
1161 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
1162 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
1163 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
1164 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
1165 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
1166 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
1167 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
1168 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
1169 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
1170 }
1171
gfx_v9_0_check_fw_write_wait(struct amdgpu_device * adev)1172 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
1173 {
1174 adev->gfx.me_fw_write_wait = false;
1175 adev->gfx.mec_fw_write_wait = false;
1176
1177 if ((adev->asic_type != CHIP_ARCTURUS) &&
1178 ((adev->gfx.mec_fw_version < 0x000001a5) ||
1179 (adev->gfx.mec_feature_version < 46) ||
1180 (adev->gfx.pfp_fw_version < 0x000000b7) ||
1181 (adev->gfx.pfp_feature_version < 46)))
1182 DRM_WARN_ONCE("CP firmware version too old, please update!");
1183
1184 switch (adev->asic_type) {
1185 case CHIP_VEGA10:
1186 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1187 (adev->gfx.me_feature_version >= 42) &&
1188 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1189 (adev->gfx.pfp_feature_version >= 42))
1190 adev->gfx.me_fw_write_wait = true;
1191
1192 if ((adev->gfx.mec_fw_version >= 0x00000193) &&
1193 (adev->gfx.mec_feature_version >= 42))
1194 adev->gfx.mec_fw_write_wait = true;
1195 break;
1196 case CHIP_VEGA12:
1197 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1198 (adev->gfx.me_feature_version >= 44) &&
1199 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1200 (adev->gfx.pfp_feature_version >= 44))
1201 adev->gfx.me_fw_write_wait = true;
1202
1203 if ((adev->gfx.mec_fw_version >= 0x00000196) &&
1204 (adev->gfx.mec_feature_version >= 44))
1205 adev->gfx.mec_fw_write_wait = true;
1206 break;
1207 case CHIP_VEGA20:
1208 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1209 (adev->gfx.me_feature_version >= 44) &&
1210 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1211 (adev->gfx.pfp_feature_version >= 44))
1212 adev->gfx.me_fw_write_wait = true;
1213
1214 if ((adev->gfx.mec_fw_version >= 0x00000197) &&
1215 (adev->gfx.mec_feature_version >= 44))
1216 adev->gfx.mec_fw_write_wait = true;
1217 break;
1218 case CHIP_RAVEN:
1219 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1220 (adev->gfx.me_feature_version >= 42) &&
1221 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1222 (adev->gfx.pfp_feature_version >= 42))
1223 adev->gfx.me_fw_write_wait = true;
1224
1225 if ((adev->gfx.mec_fw_version >= 0x00000192) &&
1226 (adev->gfx.mec_feature_version >= 42))
1227 adev->gfx.mec_fw_write_wait = true;
1228 break;
1229 default:
1230 adev->gfx.me_fw_write_wait = true;
1231 adev->gfx.mec_fw_write_wait = true;
1232 break;
1233 }
1234 }
1235
1236 struct amdgpu_gfxoff_quirk {
1237 u16 chip_vendor;
1238 u16 chip_device;
1239 u16 subsys_vendor;
1240 u16 subsys_device;
1241 u8 revision;
1242 };
1243
1244 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
1245 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */
1246 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1247 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
1248 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
1249 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
1250 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
1251 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */
1252 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },
1253 { 0, 0, 0, 0, 0 },
1254 };
1255
gfx_v9_0_should_disable_gfxoff(struct pci_dev * pdev)1256 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
1257 {
1258 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list;
1259
1260 while (p && p->chip_device != 0) {
1261 if (pdev->vendor == p->chip_vendor &&
1262 pdev->device == p->chip_device &&
1263 pdev->subsystem_vendor == p->subsys_vendor &&
1264 pdev->subsystem_device == p->subsys_device &&
1265 pdev->revision == p->revision) {
1266 return true;
1267 }
1268 ++p;
1269 }
1270 return false;
1271 }
1272
is_raven_kicker(struct amdgpu_device * adev)1273 static bool is_raven_kicker(struct amdgpu_device *adev)
1274 {
1275 if (adev->pm.fw_version >= 0x41e2b)
1276 return true;
1277 else
1278 return false;
1279 }
1280
check_if_enlarge_doorbell_range(struct amdgpu_device * adev)1281 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
1282 {
1283 if ((adev->asic_type == CHIP_RENOIR) &&
1284 (adev->gfx.me_fw_version >= 0x000000a5) &&
1285 (adev->gfx.me_feature_version >= 52))
1286 return true;
1287 else
1288 return false;
1289 }
1290
gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device * adev)1291 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
1292 {
1293 if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
1294 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1295
1296 switch (adev->asic_type) {
1297 case CHIP_VEGA10:
1298 case CHIP_VEGA12:
1299 case CHIP_VEGA20:
1300 break;
1301 case CHIP_RAVEN:
1302 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1303 (adev->apu_flags & AMD_APU_IS_PICASSO)) &&
1304 ((!is_raven_kicker(adev) &&
1305 adev->gfx.rlc_fw_version < 531) ||
1306 (adev->gfx.rlc_feature_version < 1) ||
1307 !adev->gfx.rlc.is_rlc_v2_1))
1308 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1309
1310 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1311 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1312 AMD_PG_SUPPORT_CP |
1313 AMD_PG_SUPPORT_RLC_SMU_HS;
1314 break;
1315 case CHIP_RENOIR:
1316 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1317 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1318 AMD_PG_SUPPORT_CP |
1319 AMD_PG_SUPPORT_RLC_SMU_HS;
1320 break;
1321 default:
1322 break;
1323 }
1324 }
1325
gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device * adev,const char * chip_name)1326 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
1327 const char *chip_name)
1328 {
1329 char fw_name[30];
1330 int err;
1331 struct amdgpu_firmware_info *info = NULL;
1332 const struct common_firmware_header *header = NULL;
1333 const struct gfx_firmware_header_v1_0 *cp_hdr;
1334
1335 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1336 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1337 if (err)
1338 goto out;
1339 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1340 if (err)
1341 goto out;
1342 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1343 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1344 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1345
1346 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1347 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1348 if (err)
1349 goto out;
1350 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1351 if (err)
1352 goto out;
1353 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1354 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1355 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1356
1357 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1358 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1359 if (err)
1360 goto out;
1361 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1362 if (err)
1363 goto out;
1364 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1365 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1366 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1367
1368 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1369 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1370 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1371 info->fw = adev->gfx.pfp_fw;
1372 header = (const struct common_firmware_header *)info->fw->data;
1373 adev->firmware.fw_size +=
1374 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1375
1376 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1377 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1378 info->fw = adev->gfx.me_fw;
1379 header = (const struct common_firmware_header *)info->fw->data;
1380 adev->firmware.fw_size +=
1381 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1382
1383 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1384 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1385 info->fw = adev->gfx.ce_fw;
1386 header = (const struct common_firmware_header *)info->fw->data;
1387 adev->firmware.fw_size +=
1388 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1389 }
1390
1391 out:
1392 if (err) {
1393 dev_err(adev->dev,
1394 "gfx9: Failed to load firmware \"%s\"\n",
1395 fw_name);
1396 release_firmware(adev->gfx.pfp_fw);
1397 adev->gfx.pfp_fw = NULL;
1398 release_firmware(adev->gfx.me_fw);
1399 adev->gfx.me_fw = NULL;
1400 release_firmware(adev->gfx.ce_fw);
1401 adev->gfx.ce_fw = NULL;
1402 }
1403 return err;
1404 }
1405
gfx_v9_0_init_rlc_microcode(struct amdgpu_device * adev,const char * chip_name)1406 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
1407 const char *chip_name)
1408 {
1409 char fw_name[30];
1410 int err;
1411 struct amdgpu_firmware_info *info = NULL;
1412 const struct common_firmware_header *header = NULL;
1413 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1414 unsigned int *tmp = NULL;
1415 unsigned int i = 0;
1416 uint16_t version_major;
1417 uint16_t version_minor;
1418 uint32_t smu_version;
1419
1420 /*
1421 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
1422 * instead of picasso_rlc.bin.
1423 * Judgment method:
1424 * PCO AM4: revision >= 0xC8 && revision <= 0xCF
1425 * or revision >= 0xD8 && revision <= 0xDF
1426 * otherwise is PCO FP5
1427 */
1428 if (!strcmp(chip_name, "picasso") &&
1429 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
1430 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
1431 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
1432 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
1433 (smu_version >= 0x41e2b))
1434 /**
1435 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
1436 */
1437 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
1438 else
1439 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1440 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1441 if (err)
1442 goto out;
1443 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1444 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1445
1446 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1447 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1448 if (version_major == 2 && version_minor == 1)
1449 adev->gfx.rlc.is_rlc_v2_1 = true;
1450
1451 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1452 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1453 adev->gfx.rlc.save_and_restore_offset =
1454 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1455 adev->gfx.rlc.clear_state_descriptor_offset =
1456 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1457 adev->gfx.rlc.avail_scratch_ram_locations =
1458 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1459 adev->gfx.rlc.reg_restore_list_size =
1460 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1461 adev->gfx.rlc.reg_list_format_start =
1462 le32_to_cpu(rlc_hdr->reg_list_format_start);
1463 adev->gfx.rlc.reg_list_format_separate_start =
1464 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1465 adev->gfx.rlc.starting_offsets_start =
1466 le32_to_cpu(rlc_hdr->starting_offsets_start);
1467 adev->gfx.rlc.reg_list_format_size_bytes =
1468 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1469 adev->gfx.rlc.reg_list_size_bytes =
1470 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1471 adev->gfx.rlc.register_list_format =
1472 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1473 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1474 if (!adev->gfx.rlc.register_list_format) {
1475 err = -ENOMEM;
1476 goto out;
1477 }
1478
1479 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1480 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1481 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1482 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1483
1484 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1485
1486 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1487 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1488 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1489 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1490
1491 if (adev->gfx.rlc.is_rlc_v2_1)
1492 gfx_v9_0_init_rlc_ext_microcode(adev);
1493
1494 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1495 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1496 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1497 info->fw = adev->gfx.rlc_fw;
1498 header = (const struct common_firmware_header *)info->fw->data;
1499 adev->firmware.fw_size +=
1500 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1501
1502 if (adev->gfx.rlc.is_rlc_v2_1 &&
1503 adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
1504 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
1505 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
1506 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
1507 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
1508 info->fw = adev->gfx.rlc_fw;
1509 adev->firmware.fw_size +=
1510 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
1511
1512 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
1513 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
1514 info->fw = adev->gfx.rlc_fw;
1515 adev->firmware.fw_size +=
1516 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
1517
1518 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
1519 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
1520 info->fw = adev->gfx.rlc_fw;
1521 adev->firmware.fw_size +=
1522 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
1523 }
1524 }
1525
1526 out:
1527 if (err) {
1528 dev_err(adev->dev,
1529 "gfx9: Failed to load firmware \"%s\"\n",
1530 fw_name);
1531 release_firmware(adev->gfx.rlc_fw);
1532 adev->gfx.rlc_fw = NULL;
1533 }
1534 return err;
1535 }
1536
gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device * adev,const char * chip_name)1537 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
1538 const char *chip_name)
1539 {
1540 char fw_name[30];
1541 int err;
1542 struct amdgpu_firmware_info *info = NULL;
1543 const struct common_firmware_header *header = NULL;
1544 const struct gfx_firmware_header_v1_0 *cp_hdr;
1545
1546 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1547 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1548 if (err)
1549 goto out;
1550 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1551 if (err)
1552 goto out;
1553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1554 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1555 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1556
1557
1558 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1559 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1560 if (!err) {
1561 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1562 if (err)
1563 goto out;
1564 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1565 adev->gfx.mec2_fw->data;
1566 adev->gfx.mec2_fw_version =
1567 le32_to_cpu(cp_hdr->header.ucode_version);
1568 adev->gfx.mec2_feature_version =
1569 le32_to_cpu(cp_hdr->ucode_feature_version);
1570 } else {
1571 err = 0;
1572 adev->gfx.mec2_fw = NULL;
1573 }
1574
1575 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1576 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1577 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1578 info->fw = adev->gfx.mec_fw;
1579 header = (const struct common_firmware_header *)info->fw->data;
1580 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1581 adev->firmware.fw_size +=
1582 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1583
1584 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
1585 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
1586 info->fw = adev->gfx.mec_fw;
1587 adev->firmware.fw_size +=
1588 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1589
1590 if (adev->gfx.mec2_fw) {
1591 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1592 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1593 info->fw = adev->gfx.mec2_fw;
1594 header = (const struct common_firmware_header *)info->fw->data;
1595 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
1596 adev->firmware.fw_size +=
1597 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
1598
1599 /* TODO: Determine if MEC2 JT FW loading can be removed
1600 for all GFX V9 asic and above */
1601 if (adev->asic_type != CHIP_ARCTURUS &&
1602 adev->asic_type != CHIP_RENOIR) {
1603 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
1604 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
1605 info->fw = adev->gfx.mec2_fw;
1606 adev->firmware.fw_size +=
1607 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
1608 PAGE_SIZE);
1609 }
1610 }
1611 }
1612
1613 out:
1614 gfx_v9_0_check_if_need_gfxoff(adev);
1615 gfx_v9_0_check_fw_write_wait(adev);
1616 if (err) {
1617 dev_err(adev->dev,
1618 "gfx9: Failed to load firmware \"%s\"\n",
1619 fw_name);
1620 release_firmware(adev->gfx.mec_fw);
1621 adev->gfx.mec_fw = NULL;
1622 release_firmware(adev->gfx.mec2_fw);
1623 adev->gfx.mec2_fw = NULL;
1624 }
1625 return err;
1626 }
1627
gfx_v9_0_init_microcode(struct amdgpu_device * adev)1628 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
1629 {
1630 const char *chip_name;
1631 int r;
1632
1633 DRM_DEBUG("\n");
1634
1635 switch (adev->asic_type) {
1636 case CHIP_VEGA10:
1637 chip_name = "vega10";
1638 break;
1639 case CHIP_VEGA12:
1640 chip_name = "vega12";
1641 break;
1642 case CHIP_VEGA20:
1643 chip_name = "vega20";
1644 break;
1645 case CHIP_RAVEN:
1646 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1647 chip_name = "raven2";
1648 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1649 chip_name = "picasso";
1650 else
1651 chip_name = "raven";
1652 break;
1653 case CHIP_ARCTURUS:
1654 chip_name = "arcturus";
1655 break;
1656 case CHIP_RENOIR:
1657 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1658 chip_name = "renoir";
1659 else
1660 chip_name = "green_sardine";
1661 break;
1662 default:
1663 BUG();
1664 }
1665
1666 /* No CPG in Arcturus */
1667 if (adev->asic_type != CHIP_ARCTURUS) {
1668 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
1669 if (r)
1670 return r;
1671 }
1672
1673 r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
1674 if (r)
1675 return r;
1676
1677 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
1678 if (r)
1679 return r;
1680
1681 return r;
1682 }
1683
gfx_v9_0_get_csb_size(struct amdgpu_device * adev)1684 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1685 {
1686 u32 count = 0;
1687 const struct cs_section_def *sect = NULL;
1688 const struct cs_extent_def *ext = NULL;
1689
1690 /* begin clear state */
1691 count += 2;
1692 /* context control state */
1693 count += 3;
1694
1695 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1696 for (ext = sect->section; ext->extent != NULL; ++ext) {
1697 if (sect->id == SECT_CONTEXT)
1698 count += 2 + ext->reg_count;
1699 else
1700 return 0;
1701 }
1702 }
1703
1704 /* end clear state */
1705 count += 2;
1706 /* clear state */
1707 count += 2;
1708
1709 return count;
1710 }
1711
gfx_v9_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)1712 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
1713 volatile u32 *buffer)
1714 {
1715 u32 count = 0, i;
1716 const struct cs_section_def *sect = NULL;
1717 const struct cs_extent_def *ext = NULL;
1718
1719 if (adev->gfx.rlc.cs_data == NULL)
1720 return;
1721 if (buffer == NULL)
1722 return;
1723
1724 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1725 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1726
1727 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1728 buffer[count++] = cpu_to_le32(0x80000000);
1729 buffer[count++] = cpu_to_le32(0x80000000);
1730
1731 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1732 for (ext = sect->section; ext->extent != NULL; ++ext) {
1733 if (sect->id == SECT_CONTEXT) {
1734 buffer[count++] =
1735 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1736 buffer[count++] = cpu_to_le32(ext->reg_index -
1737 PACKET3_SET_CONTEXT_REG_START);
1738 for (i = 0; i < ext->reg_count; i++)
1739 buffer[count++] = cpu_to_le32(ext->extent[i]);
1740 } else {
1741 return;
1742 }
1743 }
1744 }
1745
1746 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1747 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1748
1749 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1750 buffer[count++] = cpu_to_le32(0);
1751 }
1752
gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device * adev)1753 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
1754 {
1755 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1756 uint32_t pg_always_on_cu_num = 2;
1757 uint32_t always_on_cu_num;
1758 uint32_t i, j, k;
1759 uint32_t mask, cu_bitmap, counter;
1760
1761 if (adev->flags & AMD_IS_APU)
1762 always_on_cu_num = 4;
1763 else if (adev->asic_type == CHIP_VEGA12)
1764 always_on_cu_num = 8;
1765 else
1766 always_on_cu_num = 12;
1767
1768 mutex_lock(&adev->grbm_idx_mutex);
1769 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1770 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1771 mask = 1;
1772 cu_bitmap = 0;
1773 counter = 0;
1774 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1775
1776 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1777 if (cu_info->bitmap[i][j] & mask) {
1778 if (counter == pg_always_on_cu_num)
1779 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
1780 if (counter < always_on_cu_num)
1781 cu_bitmap |= mask;
1782 else
1783 break;
1784 counter++;
1785 }
1786 mask <<= 1;
1787 }
1788
1789 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
1790 cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
1791 }
1792 }
1793 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1794 mutex_unlock(&adev->grbm_idx_mutex);
1795 }
1796
gfx_v9_0_init_lbpw(struct amdgpu_device * adev)1797 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
1798 {
1799 uint32_t data;
1800
1801 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1802 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1803 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
1804 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1805 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
1806
1807 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1808 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1809
1810 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1811 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
1812
1813 mutex_lock(&adev->grbm_idx_mutex);
1814 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1815 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1816 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1817
1818 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1819 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1820 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1821 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1822 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1823
1824 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1825 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1826 data &= 0x0000FFFF;
1827 data |= 0x00C00000;
1828 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1829
1830 /*
1831 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1832 * programmed in gfx_v9_0_init_always_on_cu_mask()
1833 */
1834
1835 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1836 * but used for RLC_LB_CNTL configuration */
1837 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1838 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1839 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1840 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1841 mutex_unlock(&adev->grbm_idx_mutex);
1842
1843 gfx_v9_0_init_always_on_cu_mask(adev);
1844 }
1845
gfx_v9_4_init_lbpw(struct amdgpu_device * adev)1846 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1847 {
1848 uint32_t data;
1849
1850 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1851 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1852 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1853 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1854 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1855
1856 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1857 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1858
1859 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1860 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1861
1862 mutex_lock(&adev->grbm_idx_mutex);
1863 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1864 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1865 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1866
1867 /* set mmRLC_LB_PARAMS = 0x003F_1006 */
1868 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1869 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1870 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1871 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1872
1873 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1874 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1875 data &= 0x0000FFFF;
1876 data |= 0x00C00000;
1877 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1878
1879 /*
1880 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1881 * programmed in gfx_v9_0_init_always_on_cu_mask()
1882 */
1883
1884 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1885 * but used for RLC_LB_CNTL configuration */
1886 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1887 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1888 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1889 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1890 mutex_unlock(&adev->grbm_idx_mutex);
1891
1892 gfx_v9_0_init_always_on_cu_mask(adev);
1893 }
1894
gfx_v9_0_enable_lbpw(struct amdgpu_device * adev,bool enable)1895 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1896 {
1897 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1898 }
1899
gfx_v9_0_cp_jump_table_num(struct amdgpu_device * adev)1900 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1901 {
1902 return 5;
1903 }
1904
gfx_v9_0_rlc_init(struct amdgpu_device * adev)1905 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1906 {
1907 const struct cs_section_def *cs_data;
1908 int r;
1909
1910 adev->gfx.rlc.cs_data = gfx9_cs_data;
1911
1912 cs_data = adev->gfx.rlc.cs_data;
1913
1914 if (cs_data) {
1915 /* init clear state block */
1916 r = amdgpu_gfx_rlc_init_csb(adev);
1917 if (r)
1918 return r;
1919 }
1920
1921 if (adev->flags & AMD_IS_APU) {
1922 /* TODO: double check the cp_table_size for RV */
1923 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1924 r = amdgpu_gfx_rlc_init_cpt(adev);
1925 if (r)
1926 return r;
1927 }
1928
1929 switch (adev->asic_type) {
1930 case CHIP_RAVEN:
1931 gfx_v9_0_init_lbpw(adev);
1932 break;
1933 case CHIP_VEGA20:
1934 gfx_v9_4_init_lbpw(adev);
1935 break;
1936 default:
1937 break;
1938 }
1939
1940 /* init spm vmid with 0xf */
1941 if (adev->gfx.rlc.funcs->update_spm_vmid)
1942 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1943
1944 return 0;
1945 }
1946
gfx_v9_0_mec_fini(struct amdgpu_device * adev)1947 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1948 {
1949 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1950 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1951 }
1952
gfx_v9_0_mec_init(struct amdgpu_device * adev)1953 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1954 {
1955 int r;
1956 u32 *hpd;
1957 const __le32 *fw_data;
1958 unsigned fw_size;
1959 u32 *fw;
1960 size_t mec_hpd_size;
1961
1962 const struct gfx_firmware_header_v1_0 *mec_hdr;
1963
1964 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1965
1966 /* take ownership of the relevant compute queues */
1967 amdgpu_gfx_compute_queue_acquire(adev);
1968 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1969 if (mec_hpd_size) {
1970 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1971 AMDGPU_GEM_DOMAIN_VRAM,
1972 &adev->gfx.mec.hpd_eop_obj,
1973 &adev->gfx.mec.hpd_eop_gpu_addr,
1974 (void **)&hpd);
1975 if (r) {
1976 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1977 gfx_v9_0_mec_fini(adev);
1978 return r;
1979 }
1980
1981 memset(hpd, 0, mec_hpd_size);
1982
1983 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1984 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1985 }
1986
1987 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1988
1989 fw_data = (const __le32 *)
1990 (adev->gfx.mec_fw->data +
1991 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1992 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1993
1994 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1995 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1996 &adev->gfx.mec.mec_fw_obj,
1997 &adev->gfx.mec.mec_fw_gpu_addr,
1998 (void **)&fw);
1999 if (r) {
2000 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
2001 gfx_v9_0_mec_fini(adev);
2002 return r;
2003 }
2004
2005 memcpy(fw, fw_data, fw_size);
2006
2007 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2008 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2009
2010 return 0;
2011 }
2012
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)2013 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2014 {
2015 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
2016 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2017 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2018 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2019 (SQ_IND_INDEX__FORCE_READ_MASK));
2020 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
2021 }
2022
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)2023 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2024 uint32_t wave, uint32_t thread,
2025 uint32_t regno, uint32_t num, uint32_t *out)
2026 {
2027 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
2028 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2029 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2030 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2031 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2032 (SQ_IND_INDEX__FORCE_READ_MASK) |
2033 (SQ_IND_INDEX__AUTO_INCR_MASK));
2034 while (num--)
2035 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
2036 }
2037
gfx_v9_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)2038 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2039 {
2040 /* type 1 wave data */
2041 dst[(*no_fields)++] = 1;
2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2053 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2054 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2055 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2056 }
2057
gfx_v9_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)2058 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
2059 uint32_t wave, uint32_t start,
2060 uint32_t size, uint32_t *dst)
2061 {
2062 wave_read_regs(
2063 adev, simd, wave, 0,
2064 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
2065 }
2066
gfx_v9_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)2067 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
2068 uint32_t wave, uint32_t thread,
2069 uint32_t start, uint32_t size,
2070 uint32_t *dst)
2071 {
2072 wave_read_regs(
2073 adev, simd, wave, thread,
2074 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
2075 }
2076
gfx_v9_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm)2077 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
2078 u32 me, u32 pipe, u32 q, u32 vm)
2079 {
2080 soc15_grbm_select(adev, me, pipe, q, vm);
2081 }
2082
2083 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
2084 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
2085 .select_se_sh = &gfx_v9_0_select_se_sh,
2086 .read_wave_data = &gfx_v9_0_read_wave_data,
2087 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
2088 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
2089 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
2090 .ras_error_inject = &gfx_v9_0_ras_error_inject,
2091 .query_ras_error_count = &gfx_v9_0_query_ras_error_count,
2092 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,
2093 };
2094
2095 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = {
2096 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
2097 .select_se_sh = &gfx_v9_0_select_se_sh,
2098 .read_wave_data = &gfx_v9_0_read_wave_data,
2099 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
2100 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
2101 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
2102 .ras_error_inject = &gfx_v9_4_ras_error_inject,
2103 .query_ras_error_count = &gfx_v9_4_query_ras_error_count,
2104 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
2105 .query_ras_error_status = &gfx_v9_4_query_ras_error_status,
2106 };
2107
gfx_v9_0_gpu_early_init(struct amdgpu_device * adev)2108 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
2109 {
2110 u32 gb_addr_config;
2111 int err;
2112
2113 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
2114
2115 switch (adev->asic_type) {
2116 case CHIP_VEGA10:
2117 adev->gfx.config.max_hw_contexts = 8;
2118 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2119 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2120 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2121 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2122 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
2123 break;
2124 case CHIP_VEGA12:
2125 adev->gfx.config.max_hw_contexts = 8;
2126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2128 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2130 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
2131 DRM_INFO("fix gfx.config for vega12\n");
2132 break;
2133 case CHIP_VEGA20:
2134 adev->gfx.config.max_hw_contexts = 8;
2135 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2136 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2137 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2138 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2139 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2140 gb_addr_config &= ~0xf3e777ff;
2141 gb_addr_config |= 0x22014042;
2142 /* check vbios table if gpu info is not available */
2143 err = amdgpu_atomfirmware_get_gfx_info(adev);
2144 if (err)
2145 return err;
2146 break;
2147 case CHIP_RAVEN:
2148 adev->gfx.config.max_hw_contexts = 8;
2149 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2150 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2151 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2152 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2153 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2154 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
2155 else
2156 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
2157 break;
2158 case CHIP_ARCTURUS:
2159 adev->gfx.funcs = &gfx_v9_4_gfx_funcs;
2160 adev->gfx.config.max_hw_contexts = 8;
2161 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2162 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2163 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2164 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2165 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2166 gb_addr_config &= ~0xf3e777ff;
2167 gb_addr_config |= 0x22014042;
2168 break;
2169 case CHIP_RENOIR:
2170 adev->gfx.config.max_hw_contexts = 8;
2171 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2172 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2173 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
2174 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
2175 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
2176 gb_addr_config &= ~0xf3e777ff;
2177 gb_addr_config |= 0x22010042;
2178 break;
2179 default:
2180 BUG();
2181 break;
2182 }
2183
2184 adev->gfx.config.gb_addr_config = gb_addr_config;
2185
2186 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
2187 REG_GET_FIELD(
2188 adev->gfx.config.gb_addr_config,
2189 GB_ADDR_CONFIG,
2190 NUM_PIPES);
2191
2192 adev->gfx.config.max_tile_pipes =
2193 adev->gfx.config.gb_addr_config_fields.num_pipes;
2194
2195 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
2196 REG_GET_FIELD(
2197 adev->gfx.config.gb_addr_config,
2198 GB_ADDR_CONFIG,
2199 NUM_BANKS);
2200 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
2201 REG_GET_FIELD(
2202 adev->gfx.config.gb_addr_config,
2203 GB_ADDR_CONFIG,
2204 MAX_COMPRESSED_FRAGS);
2205 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
2206 REG_GET_FIELD(
2207 adev->gfx.config.gb_addr_config,
2208 GB_ADDR_CONFIG,
2209 NUM_RB_PER_SE);
2210 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
2211 REG_GET_FIELD(
2212 adev->gfx.config.gb_addr_config,
2213 GB_ADDR_CONFIG,
2214 NUM_SHADER_ENGINES);
2215 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
2216 REG_GET_FIELD(
2217 adev->gfx.config.gb_addr_config,
2218 GB_ADDR_CONFIG,
2219 PIPE_INTERLEAVE_SIZE));
2220
2221 return 0;
2222 }
2223
gfx_v9_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)2224 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
2225 int mec, int pipe, int queue)
2226 {
2227 unsigned irq_type;
2228 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
2229 unsigned int hw_prio;
2230
2231 ring = &adev->gfx.compute_ring[ring_id];
2232
2233 /* mec0 is me1 */
2234 ring->me = mec + 1;
2235 ring->pipe = pipe;
2236 ring->queue = queue;
2237
2238 ring->ring_obj = NULL;
2239 ring->use_doorbell = true;
2240 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
2241 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
2242 + (ring_id * GFX9_MEC_HPD_SIZE);
2243 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
2244
2245 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
2246 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
2247 + ring->pipe;
2248 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
2249 ring->queue) ?
2250 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
2251 /* type-2 packets are deprecated on MEC, use type-3 instead */
2252 return amdgpu_ring_init(adev, ring, 1024,
2253 &adev->gfx.eop_irq, irq_type, hw_prio);
2254 }
2255
gfx_v9_0_sw_init(void * handle)2256 static int gfx_v9_0_sw_init(void *handle)
2257 {
2258 int i, j, k, r, ring_id;
2259 struct amdgpu_ring *ring;
2260 struct amdgpu_kiq *kiq;
2261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2262
2263 switch (adev->asic_type) {
2264 case CHIP_VEGA10:
2265 case CHIP_VEGA12:
2266 case CHIP_VEGA20:
2267 case CHIP_RAVEN:
2268 case CHIP_ARCTURUS:
2269 case CHIP_RENOIR:
2270 adev->gfx.mec.num_mec = 2;
2271 break;
2272 default:
2273 adev->gfx.mec.num_mec = 1;
2274 break;
2275 }
2276
2277 adev->gfx.mec.num_pipe_per_mec = 4;
2278 adev->gfx.mec.num_queue_per_pipe = 8;
2279
2280 /* EOP Event */
2281 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
2282 if (r)
2283 return r;
2284
2285 /* Privileged reg */
2286 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
2287 &adev->gfx.priv_reg_irq);
2288 if (r)
2289 return r;
2290
2291 /* Privileged inst */
2292 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
2293 &adev->gfx.priv_inst_irq);
2294 if (r)
2295 return r;
2296
2297 /* ECC error */
2298 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR,
2299 &adev->gfx.cp_ecc_error_irq);
2300 if (r)
2301 return r;
2302
2303 /* FUE error */
2304 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR,
2305 &adev->gfx.cp_ecc_error_irq);
2306 if (r)
2307 return r;
2308
2309 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2310
2311 gfx_v9_0_scratch_init(adev);
2312
2313 r = gfx_v9_0_init_microcode(adev);
2314 if (r) {
2315 DRM_ERROR("Failed to load gfx firmware!\n");
2316 return r;
2317 }
2318
2319 r = adev->gfx.rlc.funcs->init(adev);
2320 if (r) {
2321 DRM_ERROR("Failed to init rlc BOs!\n");
2322 return r;
2323 }
2324
2325 r = gfx_v9_0_mec_init(adev);
2326 if (r) {
2327 DRM_ERROR("Failed to init MEC BOs!\n");
2328 return r;
2329 }
2330
2331 /* set up the gfx ring */
2332 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2333 ring = &adev->gfx.gfx_ring[i];
2334 ring->ring_obj = NULL;
2335 if (!i)
2336 sprintf(ring->name, "gfx");
2337 else
2338 sprintf(ring->name, "gfx_%d", i);
2339 ring->use_doorbell = true;
2340 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
2341 r = amdgpu_ring_init(adev, ring, 1024,
2342 &adev->gfx.eop_irq,
2343 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2344 AMDGPU_RING_PRIO_DEFAULT);
2345 if (r)
2346 return r;
2347 }
2348
2349 /* set up the compute queues - allocate horizontally across pipes */
2350 ring_id = 0;
2351 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2352 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2353 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2354 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2355 continue;
2356
2357 r = gfx_v9_0_compute_ring_init(adev,
2358 ring_id,
2359 i, k, j);
2360 if (r)
2361 return r;
2362
2363 ring_id++;
2364 }
2365 }
2366 }
2367
2368 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
2369 if (r) {
2370 DRM_ERROR("Failed to init KIQ BOs!\n");
2371 return r;
2372 }
2373
2374 kiq = &adev->gfx.kiq;
2375 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2376 if (r)
2377 return r;
2378
2379 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
2380 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
2381 if (r)
2382 return r;
2383
2384 adev->gfx.ce_ram_size = 0x8000;
2385
2386 r = gfx_v9_0_gpu_early_init(adev);
2387 if (r)
2388 return r;
2389
2390 return 0;
2391 }
2392
2393
gfx_v9_0_sw_fini(void * handle)2394 static int gfx_v9_0_sw_fini(void *handle)
2395 {
2396 int i;
2397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2398
2399 amdgpu_gfx_ras_fini(adev);
2400
2401 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2402 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2403 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2404 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2405
2406 amdgpu_gfx_mqd_sw_fini(adev);
2407 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2408 amdgpu_gfx_kiq_fini(adev);
2409
2410 gfx_v9_0_mec_fini(adev);
2411 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
2412 if (adev->flags & AMD_IS_APU) {
2413 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2414 &adev->gfx.rlc.cp_table_gpu_addr,
2415 (void **)&adev->gfx.rlc.cp_table_ptr);
2416 }
2417 gfx_v9_0_free_microcode(adev);
2418
2419 return 0;
2420 }
2421
2422
gfx_v9_0_tiling_mode_table_init(struct amdgpu_device * adev)2423 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
2424 {
2425 /* TODO */
2426 }
2427
gfx_v9_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)2428 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
2429 u32 instance)
2430 {
2431 u32 data;
2432
2433 if (instance == 0xffffffff)
2434 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2435 else
2436 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2437
2438 if (se_num == 0xffffffff)
2439 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2440 else
2441 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2442
2443 if (sh_num == 0xffffffff)
2444 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2445 else
2446 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2447
2448 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
2449 }
2450
gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device * adev)2451 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2452 {
2453 u32 data, mask;
2454
2455 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
2456 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
2457
2458 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2459 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2460
2461 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2462 adev->gfx.config.max_sh_per_se);
2463
2464 return (~data) & mask;
2465 }
2466
gfx_v9_0_setup_rb(struct amdgpu_device * adev)2467 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
2468 {
2469 int i, j;
2470 u32 data;
2471 u32 active_rbs = 0;
2472 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2473 adev->gfx.config.max_sh_per_se;
2474
2475 mutex_lock(&adev->grbm_idx_mutex);
2476 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2477 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2478 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2479 data = gfx_v9_0_get_rb_active_bitmap(adev);
2480 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2481 rb_bitmap_width_per_sh);
2482 }
2483 }
2484 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2485 mutex_unlock(&adev->grbm_idx_mutex);
2486
2487 adev->gfx.config.backend_enable_mask = active_rbs;
2488 adev->gfx.config.num_rbs = hweight32(active_rbs);
2489 }
2490
2491 #define DEFAULT_SH_MEM_BASES (0x6000)
gfx_v9_0_init_compute_vmid(struct amdgpu_device * adev)2492 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
2493 {
2494 int i;
2495 uint32_t sh_mem_config;
2496 uint32_t sh_mem_bases;
2497
2498 /*
2499 * Configure apertures:
2500 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2501 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2502 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2503 */
2504 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2505
2506 sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
2507 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2508 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
2509
2510 mutex_lock(&adev->srbm_mutex);
2511 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
2512 soc15_grbm_select(adev, 0, 0, 0, i);
2513 /* CP and shaders */
2514 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
2515 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2516 }
2517 soc15_grbm_select(adev, 0, 0, 0, 0);
2518 mutex_unlock(&adev->srbm_mutex);
2519
2520 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
2521 acccess. These should be enabled by FW for target VMIDs. */
2522 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
2523 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
2524 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
2525 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
2526 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
2527 }
2528 }
2529
gfx_v9_0_init_gds_vmid(struct amdgpu_device * adev)2530 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
2531 {
2532 int vmid;
2533
2534 /*
2535 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2536 * access. Compute VMIDs should be enabled by FW for target VMIDs,
2537 * the driver can enable them for graphics. VMID0 should maintain
2538 * access so that HWS firmware can save/restore entries.
2539 */
2540 for (vmid = 1; vmid < 16; vmid++) {
2541 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
2542 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
2543 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
2544 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
2545 }
2546 }
2547
gfx_v9_0_init_sq_config(struct amdgpu_device * adev)2548 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
2549 {
2550 uint32_t tmp;
2551
2552 switch (adev->asic_type) {
2553 case CHIP_ARCTURUS:
2554 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
2555 tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
2556 DISABLE_BARRIER_WAITCNT, 1);
2557 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
2558 break;
2559 default:
2560 break;
2561 }
2562 }
2563
gfx_v9_0_constants_init(struct amdgpu_device * adev)2564 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
2565 {
2566 u32 tmp;
2567 int i;
2568
2569 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
2570
2571 gfx_v9_0_tiling_mode_table_init(adev);
2572
2573 if (adev->gfx.num_gfx_rings)
2574 gfx_v9_0_setup_rb(adev);
2575 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
2576 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
2577
2578 /* XXX SH_MEM regs */
2579 /* where to put LDS, scratch, GPUVM in FSA64 space */
2580 mutex_lock(&adev->srbm_mutex);
2581 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
2582 soc15_grbm_select(adev, 0, 0, 0, i);
2583 /* CP and shaders */
2584 if (i == 0) {
2585 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2586 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2587 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2588 !!adev->gmc.noretry);
2589 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2590 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
2591 } else {
2592 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2593 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2594 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2595 !!adev->gmc.noretry);
2596 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2597 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2598 (adev->gmc.private_aperture_start >> 48));
2599 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
2600 (adev->gmc.shared_aperture_start >> 48));
2601 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
2602 }
2603 }
2604 soc15_grbm_select(adev, 0, 0, 0, 0);
2605
2606 mutex_unlock(&adev->srbm_mutex);
2607
2608 gfx_v9_0_init_compute_vmid(adev);
2609 gfx_v9_0_init_gds_vmid(adev);
2610 gfx_v9_0_init_sq_config(adev);
2611 }
2612
gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device * adev)2613 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2614 {
2615 u32 i, j, k;
2616 u32 mask;
2617
2618 mutex_lock(&adev->grbm_idx_mutex);
2619 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2620 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2621 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
2622 for (k = 0; k < adev->usec_timeout; k++) {
2623 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2624 break;
2625 udelay(1);
2626 }
2627 if (k == adev->usec_timeout) {
2628 gfx_v9_0_select_se_sh(adev, 0xffffffff,
2629 0xffffffff, 0xffffffff);
2630 mutex_unlock(&adev->grbm_idx_mutex);
2631 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2632 i, j);
2633 return;
2634 }
2635 }
2636 }
2637 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2638 mutex_unlock(&adev->grbm_idx_mutex);
2639
2640 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2641 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2642 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2643 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2644 for (k = 0; k < adev->usec_timeout; k++) {
2645 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2646 break;
2647 udelay(1);
2648 }
2649 }
2650
gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)2651 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2652 bool enable)
2653 {
2654 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
2655
2656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2657 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2658 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2659 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2660
2661 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
2662 }
2663
gfx_v9_0_init_csb(struct amdgpu_device * adev)2664 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2665 {
2666 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2667 /* csib */
2668 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2669 adev->gfx.rlc.clear_state_gpu_addr >> 32);
2670 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
2671 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2672 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
2673 adev->gfx.rlc.clear_state_size);
2674 }
2675
gfx_v9_1_parse_ind_reg_list(int * register_list_format,int indirect_offset,int list_size,int * unique_indirect_regs,int unique_indirect_reg_count,int * indirect_start_offsets,int * indirect_start_offsets_count,int max_start_offsets_count)2676 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2677 int indirect_offset,
2678 int list_size,
2679 int *unique_indirect_regs,
2680 int unique_indirect_reg_count,
2681 int *indirect_start_offsets,
2682 int *indirect_start_offsets_count,
2683 int max_start_offsets_count)
2684 {
2685 int idx;
2686
2687 for (; indirect_offset < list_size; indirect_offset++) {
2688 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
2689 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2690 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2691
2692 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2693 indirect_offset += 2;
2694
2695 /* look for the matching indice */
2696 for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2697 if (unique_indirect_regs[idx] ==
2698 register_list_format[indirect_offset] ||
2699 !unique_indirect_regs[idx])
2700 break;
2701 }
2702
2703 BUG_ON(idx >= unique_indirect_reg_count);
2704
2705 if (!unique_indirect_regs[idx])
2706 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2707
2708 indirect_offset++;
2709 }
2710 }
2711 }
2712
gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device * adev)2713 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2714 {
2715 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2716 int unique_indirect_reg_count = 0;
2717
2718 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2719 int indirect_start_offsets_count = 0;
2720
2721 int list_size = 0;
2722 int i = 0, j = 0;
2723 u32 tmp = 0;
2724
2725 u32 *register_list_format =
2726 kmemdup(adev->gfx.rlc.register_list_format,
2727 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2728 if (!register_list_format)
2729 return -ENOMEM;
2730
2731 /* setup unique_indirect_regs array and indirect_start_offsets array */
2732 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2733 gfx_v9_1_parse_ind_reg_list(register_list_format,
2734 adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2735 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2736 unique_indirect_regs,
2737 unique_indirect_reg_count,
2738 indirect_start_offsets,
2739 &indirect_start_offsets_count,
2740 ARRAY_SIZE(indirect_start_offsets));
2741
2742 /* enable auto inc in case it is disabled */
2743 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2744 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2745 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2746
2747 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2748 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2749 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2750 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2751 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2752 adev->gfx.rlc.register_restore[i]);
2753
2754 /* load indirect register */
2755 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2756 adev->gfx.rlc.reg_list_format_start);
2757
2758 /* direct register portion */
2759 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2761 register_list_format[i]);
2762
2763 /* indirect register portion */
2764 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2765 if (register_list_format[i] == 0xFFFFFFFF) {
2766 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2767 continue;
2768 }
2769
2770 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2771 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2772
2773 for (j = 0; j < unique_indirect_reg_count; j++) {
2774 if (register_list_format[i] == unique_indirect_regs[j]) {
2775 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2776 break;
2777 }
2778 }
2779
2780 BUG_ON(j >= unique_indirect_reg_count);
2781
2782 i++;
2783 }
2784
2785 /* set save/restore list size */
2786 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2787 list_size = list_size >> 1;
2788 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2789 adev->gfx.rlc.reg_restore_list_size);
2790 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2791
2792 /* write the starting offsets to RLC scratch ram */
2793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2794 adev->gfx.rlc.starting_offsets_start);
2795 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2796 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2797 indirect_start_offsets[i]);
2798
2799 /* load unique indirect regs*/
2800 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2801 if (unique_indirect_regs[i] != 0) {
2802 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2803 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2804 unique_indirect_regs[i] & 0x3FFFF);
2805
2806 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2807 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2808 unique_indirect_regs[i] >> 20);
2809 }
2810 }
2811
2812 kfree(register_list_format);
2813 return 0;
2814 }
2815
gfx_v9_0_enable_save_restore_machine(struct amdgpu_device * adev)2816 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2817 {
2818 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2819 }
2820
pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device * adev,bool enable)2821 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2822 bool enable)
2823 {
2824 uint32_t data = 0;
2825 uint32_t default_data = 0;
2826
2827 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2828 if (enable) {
2829 /* enable GFXIP control over CGPG */
2830 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2831 if(default_data != data)
2832 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2833
2834 /* update status */
2835 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2836 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2837 if(default_data != data)
2838 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2839 } else {
2840 /* restore GFXIP control over GCPG */
2841 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2842 if(default_data != data)
2843 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2844 }
2845 }
2846
gfx_v9_0_init_gfx_power_gating(struct amdgpu_device * adev)2847 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2848 {
2849 uint32_t data = 0;
2850
2851 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2852 AMD_PG_SUPPORT_GFX_SMG |
2853 AMD_PG_SUPPORT_GFX_DMG)) {
2854 /* init IDLE_POLL_COUNT = 60 */
2855 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2856 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2857 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2858 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2859
2860 /* init RLC PG Delay */
2861 data = 0;
2862 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2863 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2864 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2865 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2866 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2867
2868 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2869 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2870 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2871 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2872
2873 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2874 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2875 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2876 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2877
2878 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2879 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2880
2881 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2882 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2883 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2884 if (adev->asic_type != CHIP_RENOIR)
2885 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2886 }
2887 }
2888
gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device * adev,bool enable)2889 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2890 bool enable)
2891 {
2892 uint32_t data = 0;
2893 uint32_t default_data = 0;
2894
2895 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2896 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2897 SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2898 enable ? 1 : 0);
2899 if (default_data != data)
2900 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2901 }
2902
gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device * adev,bool enable)2903 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2904 bool enable)
2905 {
2906 uint32_t data = 0;
2907 uint32_t default_data = 0;
2908
2909 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2910 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2911 SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2912 enable ? 1 : 0);
2913 if(default_data != data)
2914 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2915 }
2916
gfx_v9_0_enable_cp_power_gating(struct amdgpu_device * adev,bool enable)2917 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2918 bool enable)
2919 {
2920 uint32_t data = 0;
2921 uint32_t default_data = 0;
2922
2923 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2924 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2925 CP_PG_DISABLE,
2926 enable ? 0 : 1);
2927 if(default_data != data)
2928 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2929 }
2930
gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)2931 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2932 bool enable)
2933 {
2934 uint32_t data, default_data;
2935
2936 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2937 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2938 GFX_POWER_GATING_ENABLE,
2939 enable ? 1 : 0);
2940 if(default_data != data)
2941 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2942 }
2943
gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device * adev,bool enable)2944 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2945 bool enable)
2946 {
2947 uint32_t data, default_data;
2948
2949 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2950 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2951 GFX_PIPELINE_PG_ENABLE,
2952 enable ? 1 : 0);
2953 if(default_data != data)
2954 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2955
2956 if (!enable)
2957 /* read any GFX register to wake up GFX */
2958 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2959 }
2960
gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device * adev,bool enable)2961 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2962 bool enable)
2963 {
2964 uint32_t data, default_data;
2965
2966 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2967 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2968 STATIC_PER_CU_PG_ENABLE,
2969 enable ? 1 : 0);
2970 if(default_data != data)
2971 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2972 }
2973
gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device * adev,bool enable)2974 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2975 bool enable)
2976 {
2977 uint32_t data, default_data;
2978
2979 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2980 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2981 DYN_PER_CU_PG_ENABLE,
2982 enable ? 1 : 0);
2983 if(default_data != data)
2984 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2985 }
2986
gfx_v9_0_init_pg(struct amdgpu_device * adev)2987 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2988 {
2989 gfx_v9_0_init_csb(adev);
2990
2991 /*
2992 * Rlc save restore list is workable since v2_1.
2993 * And it's needed by gfxoff feature.
2994 */
2995 if (adev->gfx.rlc.is_rlc_v2_1) {
2996 if (adev->asic_type == CHIP_VEGA12 ||
2997 (adev->apu_flags & AMD_APU_IS_RAVEN2))
2998 gfx_v9_1_init_rlc_save_restore_list(adev);
2999 gfx_v9_0_enable_save_restore_machine(adev);
3000 }
3001
3002 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3003 AMD_PG_SUPPORT_GFX_SMG |
3004 AMD_PG_SUPPORT_GFX_DMG |
3005 AMD_PG_SUPPORT_CP |
3006 AMD_PG_SUPPORT_GDS |
3007 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3008 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,
3009 adev->gfx.rlc.cp_table_gpu_addr >> 8);
3010 gfx_v9_0_init_gfx_power_gating(adev);
3011 }
3012 }
3013
gfx_v9_0_rlc_stop(struct amdgpu_device * adev)3014 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
3015 {
3016 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
3017 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3018 gfx_v9_0_wait_for_rlc_serdes(adev);
3019 }
3020
gfx_v9_0_rlc_reset(struct amdgpu_device * adev)3021 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
3022 {
3023 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3024 udelay(50);
3025 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
3026 udelay(50);
3027 }
3028
gfx_v9_0_rlc_start(struct amdgpu_device * adev)3029 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
3030 {
3031 #ifdef AMDGPU_RLC_DEBUG_RETRY
3032 u32 rlc_ucode_ver;
3033 #endif
3034
3035 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
3036 udelay(50);
3037
3038 /* carrizo do enable cp interrupt after cp inited */
3039 if (!(adev->flags & AMD_IS_APU)) {
3040 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3041 udelay(50);
3042 }
3043
3044 #ifdef AMDGPU_RLC_DEBUG_RETRY
3045 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
3046 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
3047 if(rlc_ucode_ver == 0x108) {
3048 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
3049 rlc_ucode_ver, adev->gfx.rlc_fw_version);
3050 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
3051 * default is 0x9C4 to create a 100us interval */
3052 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
3053 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
3054 * to disable the page fault retry interrupts, default is
3055 * 0x100 (256) */
3056 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
3057 }
3058 #endif
3059 }
3060
gfx_v9_0_rlc_load_microcode(struct amdgpu_device * adev)3061 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
3062 {
3063 const struct rlc_firmware_header_v2_0 *hdr;
3064 const __le32 *fw_data;
3065 unsigned i, fw_size;
3066
3067 if (!adev->gfx.rlc_fw)
3068 return -EINVAL;
3069
3070 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3071 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3072
3073 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
3074 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3075 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3076
3077 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
3078 RLCG_UCODE_LOADING_START_ADDRESS);
3079 for (i = 0; i < fw_size; i++)
3080 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3081 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3082
3083 return 0;
3084 }
3085
gfx_v9_0_rlc_resume(struct amdgpu_device * adev)3086 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
3087 {
3088 int r;
3089
3090 if (amdgpu_sriov_vf(adev)) {
3091 gfx_v9_0_init_csb(adev);
3092 return 0;
3093 }
3094
3095 adev->gfx.rlc.funcs->stop(adev);
3096
3097 /* disable CG */
3098 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
3099
3100 gfx_v9_0_init_pg(adev);
3101
3102 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3103 /* legacy rlc firmware loading */
3104 r = gfx_v9_0_rlc_load_microcode(adev);
3105 if (r)
3106 return r;
3107 }
3108
3109 switch (adev->asic_type) {
3110 case CHIP_RAVEN:
3111 if (amdgpu_lbpw == 0)
3112 gfx_v9_0_enable_lbpw(adev, false);
3113 else
3114 gfx_v9_0_enable_lbpw(adev, true);
3115 break;
3116 case CHIP_VEGA20:
3117 if (amdgpu_lbpw > 0)
3118 gfx_v9_0_enable_lbpw(adev, true);
3119 else
3120 gfx_v9_0_enable_lbpw(adev, false);
3121 break;
3122 default:
3123 break;
3124 }
3125
3126 adev->gfx.rlc.funcs->start(adev);
3127
3128 return 0;
3129 }
3130
gfx_v9_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)3131 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
3132 {
3133 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
3134
3135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
3136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
3137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
3138 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
3139 udelay(50);
3140 }
3141
gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device * adev)3142 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3143 {
3144 const struct gfx_firmware_header_v1_0 *pfp_hdr;
3145 const struct gfx_firmware_header_v1_0 *ce_hdr;
3146 const struct gfx_firmware_header_v1_0 *me_hdr;
3147 const __le32 *fw_data;
3148 unsigned i, fw_size;
3149
3150 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
3151 return -EINVAL;
3152
3153 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
3154 adev->gfx.pfp_fw->data;
3155 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
3156 adev->gfx.ce_fw->data;
3157 me_hdr = (const struct gfx_firmware_header_v1_0 *)
3158 adev->gfx.me_fw->data;
3159
3160 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
3161 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
3162 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
3163
3164 gfx_v9_0_cp_gfx_enable(adev, false);
3165
3166 /* PFP */
3167 fw_data = (const __le32 *)
3168 (adev->gfx.pfp_fw->data +
3169 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3170 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3171 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
3172 for (i = 0; i < fw_size; i++)
3173 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3174 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3175
3176 /* CE */
3177 fw_data = (const __le32 *)
3178 (adev->gfx.ce_fw->data +
3179 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3180 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3181 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
3182 for (i = 0; i < fw_size; i++)
3183 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3184 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3185
3186 /* ME */
3187 fw_data = (const __le32 *)
3188 (adev->gfx.me_fw->data +
3189 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3190 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3191 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
3192 for (i = 0; i < fw_size; i++)
3193 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3194 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3195
3196 return 0;
3197 }
3198
gfx_v9_0_cp_gfx_start(struct amdgpu_device * adev)3199 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
3200 {
3201 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3202 const struct cs_section_def *sect = NULL;
3203 const struct cs_extent_def *ext = NULL;
3204 int r, i, tmp;
3205
3206 /* init the CP */
3207 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3208 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
3209
3210 gfx_v9_0_cp_gfx_enable(adev, true);
3211
3212 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
3213 if (r) {
3214 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3215 return r;
3216 }
3217
3218 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3219 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3220
3221 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3222 amdgpu_ring_write(ring, 0x80000000);
3223 amdgpu_ring_write(ring, 0x80000000);
3224
3225 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
3226 for (ext = sect->section; ext->extent != NULL; ++ext) {
3227 if (sect->id == SECT_CONTEXT) {
3228 amdgpu_ring_write(ring,
3229 PACKET3(PACKET3_SET_CONTEXT_REG,
3230 ext->reg_count));
3231 amdgpu_ring_write(ring,
3232 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3233 for (i = 0; i < ext->reg_count; i++)
3234 amdgpu_ring_write(ring, ext->extent[i]);
3235 }
3236 }
3237 }
3238
3239 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3240 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3241
3242 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3243 amdgpu_ring_write(ring, 0);
3244
3245 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3246 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3247 amdgpu_ring_write(ring, 0x8000);
3248 amdgpu_ring_write(ring, 0x8000);
3249
3250 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
3251 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
3252 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
3253 amdgpu_ring_write(ring, tmp);
3254 amdgpu_ring_write(ring, 0);
3255
3256 amdgpu_ring_commit(ring);
3257
3258 return 0;
3259 }
3260
gfx_v9_0_cp_gfx_resume(struct amdgpu_device * adev)3261 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
3262 {
3263 struct amdgpu_ring *ring;
3264 u32 tmp;
3265 u32 rb_bufsz;
3266 u64 rb_addr, rptr_addr, wptr_gpu_addr;
3267
3268 /* Set the write pointer delay */
3269 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
3270
3271 /* set the RB to use vmid 0 */
3272 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
3273
3274 /* Set ring buffer size */
3275 ring = &adev->gfx.gfx_ring[0];
3276 rb_bufsz = order_base_2(ring->ring_size / 8);
3277 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3278 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3279 #ifdef __BIG_ENDIAN
3280 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3281 #endif
3282 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3283
3284 /* Initialize the ring buffer's write pointers */
3285 ring->wptr = 0;
3286 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3287 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3288
3289 /* set the wb address wether it's enabled or not */
3290 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3291 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3292 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3293
3294 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3295 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
3296 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3297
3298 mdelay(1);
3299 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3300
3301 rb_addr = ring->gpu_addr >> 8;
3302 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
3303 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3304
3305 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3306 if (ring->use_doorbell) {
3307 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3308 DOORBELL_OFFSET, ring->doorbell_index);
3309 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3310 DOORBELL_EN, 1);
3311 } else {
3312 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
3313 }
3314 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
3315
3316 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3317 DOORBELL_RANGE_LOWER, ring->doorbell_index);
3318 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3319
3320 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
3321 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3322
3323
3324 /* start the ring */
3325 gfx_v9_0_cp_gfx_start(adev);
3326 ring->sched.ready = true;
3327
3328 return 0;
3329 }
3330
gfx_v9_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)3331 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3332 {
3333 if (enable) {
3334 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
3335 } else {
3336 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
3337 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3338 adev->gfx.kiq.ring.sched.ready = false;
3339 }
3340 udelay(50);
3341 }
3342
gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device * adev)3343 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3344 {
3345 const struct gfx_firmware_header_v1_0 *mec_hdr;
3346 const __le32 *fw_data;
3347 unsigned i;
3348 u32 tmp;
3349
3350 if (!adev->gfx.mec_fw)
3351 return -EINVAL;
3352
3353 gfx_v9_0_cp_compute_enable(adev, false);
3354
3355 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3356 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3357
3358 fw_data = (const __le32 *)
3359 (adev->gfx.mec_fw->data +
3360 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3361 tmp = 0;
3362 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3363 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3364 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
3365
3366 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
3367 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
3368 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
3369 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3370
3371 /* MEC1 */
3372 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3373 mec_hdr->jt_offset);
3374 for (i = 0; i < mec_hdr->jt_size; i++)
3375 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
3376 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3377
3378 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3379 adev->gfx.mec_fw_version);
3380 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3381
3382 return 0;
3383 }
3384
3385 /* KIQ functions */
gfx_v9_0_kiq_setting(struct amdgpu_ring * ring)3386 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
3387 {
3388 uint32_t tmp;
3389 struct amdgpu_device *adev = ring->adev;
3390
3391 /* tell RLC which is KIQ queue */
3392 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
3393 tmp &= 0xffffff00;
3394 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3395 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3396 tmp |= 0x80;
3397 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3398 }
3399
gfx_v9_0_mqd_set_priority(struct amdgpu_ring * ring,struct v9_mqd * mqd)3400 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
3401 {
3402 struct amdgpu_device *adev = ring->adev;
3403
3404 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3405 if (amdgpu_gfx_is_high_priority_compute_queue(adev,
3406 ring->pipe,
3407 ring->queue)) {
3408 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
3409 mqd->cp_hqd_queue_priority =
3410 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
3411 }
3412 }
3413 }
3414
gfx_v9_0_mqd_init(struct amdgpu_ring * ring)3415 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
3416 {
3417 struct amdgpu_device *adev = ring->adev;
3418 struct v9_mqd *mqd = ring->mqd_ptr;
3419 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3420 uint32_t tmp;
3421
3422 mqd->header = 0xC0310800;
3423 mqd->compute_pipelinestat_enable = 0x00000001;
3424 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3425 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3426 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3427 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3428 mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
3429 mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
3430 mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
3431 mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
3432 mqd->compute_misc_reserved = 0x00000003;
3433
3434 mqd->dynamic_cu_mask_addr_lo =
3435 lower_32_bits(ring->mqd_gpu_addr
3436 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3437 mqd->dynamic_cu_mask_addr_hi =
3438 upper_32_bits(ring->mqd_gpu_addr
3439 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3440
3441 eop_base_addr = ring->eop_gpu_addr >> 8;
3442 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3443 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3444
3445 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3446 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3447 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3448 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
3449
3450 mqd->cp_hqd_eop_control = tmp;
3451
3452 /* enable doorbell? */
3453 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3454
3455 if (ring->use_doorbell) {
3456 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3457 DOORBELL_OFFSET, ring->doorbell_index);
3458 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3459 DOORBELL_EN, 1);
3460 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3461 DOORBELL_SOURCE, 0);
3462 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3463 DOORBELL_HIT, 0);
3464 } else {
3465 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3466 DOORBELL_EN, 0);
3467 }
3468
3469 mqd->cp_hqd_pq_doorbell_control = tmp;
3470
3471 /* disable the queue if it's active */
3472 ring->wptr = 0;
3473 mqd->cp_hqd_dequeue_request = 0;
3474 mqd->cp_hqd_pq_rptr = 0;
3475 mqd->cp_hqd_pq_wptr_lo = 0;
3476 mqd->cp_hqd_pq_wptr_hi = 0;
3477
3478 /* set the pointer to the MQD */
3479 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3480 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3481
3482 /* set MQD vmid to 0 */
3483 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3484 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3485 mqd->cp_mqd_control = tmp;
3486
3487 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3488 hqd_gpu_addr = ring->gpu_addr >> 8;
3489 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3490 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3491
3492 /* set up the HQD, this is similar to CP_RB0_CNTL */
3493 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3495 (order_base_2(ring->ring_size / 4) - 1));
3496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3497 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3498 #ifdef __BIG_ENDIAN
3499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3500 #endif
3501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3502 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3504 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3505 mqd->cp_hqd_pq_control = tmp;
3506
3507 /* set the wb address whether it's enabled or not */
3508 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3509 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3510 mqd->cp_hqd_pq_rptr_report_addr_hi =
3511 upper_32_bits(wb_gpu_addr) & 0xffff;
3512
3513 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3514 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3515 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3516 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3517
3518 tmp = 0;
3519 /* enable the doorbell if requested */
3520 if (ring->use_doorbell) {
3521 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3523 DOORBELL_OFFSET, ring->doorbell_index);
3524
3525 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3526 DOORBELL_EN, 1);
3527 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3528 DOORBELL_SOURCE, 0);
3529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3530 DOORBELL_HIT, 0);
3531 }
3532
3533 mqd->cp_hqd_pq_doorbell_control = tmp;
3534
3535 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3536 ring->wptr = 0;
3537 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3538
3539 /* set the vmid for the queue */
3540 mqd->cp_hqd_vmid = 0;
3541
3542 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3543 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3544 mqd->cp_hqd_persistent_state = tmp;
3545
3546 /* set MIN_IB_AVAIL_SIZE */
3547 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3548 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3549 mqd->cp_hqd_ib_control = tmp;
3550
3551 /* set static priority for a queue/ring */
3552 gfx_v9_0_mqd_set_priority(ring, mqd);
3553 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);
3554
3555 /* map_queues packet doesn't need activate the queue,
3556 * so only kiq need set this field.
3557 */
3558 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3559 mqd->cp_hqd_active = 1;
3560
3561 return 0;
3562 }
3563
gfx_v9_0_kiq_init_register(struct amdgpu_ring * ring)3564 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3565 {
3566 struct amdgpu_device *adev = ring->adev;
3567 struct v9_mqd *mqd = ring->mqd_ptr;
3568 int j;
3569
3570 /* disable wptr polling */
3571 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3572
3573 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3574 mqd->cp_hqd_eop_base_addr_lo);
3575 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3576 mqd->cp_hqd_eop_base_addr_hi);
3577
3578 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3579 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
3580 mqd->cp_hqd_eop_control);
3581
3582 /* enable doorbell? */
3583 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3584 mqd->cp_hqd_pq_doorbell_control);
3585
3586 /* disable the queue if it's active */
3587 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3588 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3589 for (j = 0; j < adev->usec_timeout; j++) {
3590 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3591 break;
3592 udelay(1);
3593 }
3594 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3595 mqd->cp_hqd_dequeue_request);
3596 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,
3597 mqd->cp_hqd_pq_rptr);
3598 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3599 mqd->cp_hqd_pq_wptr_lo);
3600 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3601 mqd->cp_hqd_pq_wptr_hi);
3602 }
3603
3604 /* set the pointer to the MQD */
3605 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
3606 mqd->cp_mqd_base_addr_lo);
3607 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3608 mqd->cp_mqd_base_addr_hi);
3609
3610 /* set MQD vmid to 0 */
3611 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,
3612 mqd->cp_mqd_control);
3613
3614 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3615 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
3616 mqd->cp_hqd_pq_base_lo);
3617 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
3618 mqd->cp_hqd_pq_base_hi);
3619
3620 /* set up the HQD, this is similar to CP_RB0_CNTL */
3621 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
3622 mqd->cp_hqd_pq_control);
3623
3624 /* set the wb address whether it's enabled or not */
3625 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3626 mqd->cp_hqd_pq_rptr_report_addr_lo);
3627 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3628 mqd->cp_hqd_pq_rptr_report_addr_hi);
3629
3630 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3631 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3632 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3633 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3634 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3635
3636 /* enable the doorbell if requested */
3637 if (ring->use_doorbell) {
3638 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3639 (adev->doorbell_index.kiq * 2) << 2);
3640 /* If GC has entered CGPG, ringing doorbell > first page
3641 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
3642 * workaround this issue. And this change has to align with firmware
3643 * update.
3644 */
3645 if (check_if_enlarge_doorbell_range(adev))
3646 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3647 (adev->doorbell.size - 4));
3648 else
3649 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3650 (adev->doorbell_index.userqueue_end * 2) << 2);
3651 }
3652
3653 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3654 mqd->cp_hqd_pq_doorbell_control);
3655
3656 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3657 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3658 mqd->cp_hqd_pq_wptr_lo);
3659 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3660 mqd->cp_hqd_pq_wptr_hi);
3661
3662 /* set the vmid for the queue */
3663 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3664
3665 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3666 mqd->cp_hqd_persistent_state);
3667
3668 /* activate the queue */
3669 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
3670 mqd->cp_hqd_active);
3671
3672 if (ring->use_doorbell)
3673 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3674
3675 return 0;
3676 }
3677
gfx_v9_0_kiq_fini_register(struct amdgpu_ring * ring)3678 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3679 {
3680 struct amdgpu_device *adev = ring->adev;
3681 int j;
3682
3683 /* disable the queue if it's active */
3684 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3685
3686 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3687
3688 for (j = 0; j < adev->usec_timeout; j++) {
3689 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3690 break;
3691 udelay(1);
3692 }
3693
3694 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3695 DRM_DEBUG("KIQ dequeue request failed.\n");
3696
3697 /* Manual disable if dequeue request times out */
3698 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
3699 }
3700
3701 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3702 0);
3703 }
3704
3705 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3706 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3707 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3708 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3709 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3710 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3711 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3712 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3713
3714 return 0;
3715 }
3716
gfx_v9_0_kiq_init_queue(struct amdgpu_ring * ring)3717 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3718 {
3719 struct amdgpu_device *adev = ring->adev;
3720 struct v9_mqd *mqd = ring->mqd_ptr;
3721 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3722
3723 gfx_v9_0_kiq_setting(ring);
3724
3725 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3726 /* reset MQD to a clean status */
3727 if (adev->gfx.mec.mqd_backup[mqd_idx])
3728 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3729
3730 /* reset ring buffer */
3731 ring->wptr = 0;
3732 amdgpu_ring_clear_ring(ring);
3733
3734 mutex_lock(&adev->srbm_mutex);
3735 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3736 gfx_v9_0_kiq_init_register(ring);
3737 soc15_grbm_select(adev, 0, 0, 0, 0);
3738 mutex_unlock(&adev->srbm_mutex);
3739 } else {
3740 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3741 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3742 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3743 mutex_lock(&adev->srbm_mutex);
3744 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3745 gfx_v9_0_mqd_init(ring);
3746 gfx_v9_0_kiq_init_register(ring);
3747 soc15_grbm_select(adev, 0, 0, 0, 0);
3748 mutex_unlock(&adev->srbm_mutex);
3749
3750 if (adev->gfx.mec.mqd_backup[mqd_idx])
3751 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3752 }
3753
3754 return 0;
3755 }
3756
gfx_v9_0_kcq_init_queue(struct amdgpu_ring * ring)3757 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3758 {
3759 struct amdgpu_device *adev = ring->adev;
3760 struct v9_mqd *mqd = ring->mqd_ptr;
3761 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3762
3763 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3764 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3765 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3766 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3767 mutex_lock(&adev->srbm_mutex);
3768 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3769 gfx_v9_0_mqd_init(ring);
3770 soc15_grbm_select(adev, 0, 0, 0, 0);
3771 mutex_unlock(&adev->srbm_mutex);
3772
3773 if (adev->gfx.mec.mqd_backup[mqd_idx])
3774 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3775 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3776 /* reset MQD to a clean status */
3777 if (adev->gfx.mec.mqd_backup[mqd_idx])
3778 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3779
3780 /* reset ring buffer */
3781 ring->wptr = 0;
3782 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3783 amdgpu_ring_clear_ring(ring);
3784 } else {
3785 amdgpu_ring_clear_ring(ring);
3786 }
3787
3788 return 0;
3789 }
3790
gfx_v9_0_kiq_resume(struct amdgpu_device * adev)3791 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3792 {
3793 struct amdgpu_ring *ring;
3794 int r;
3795
3796 ring = &adev->gfx.kiq.ring;
3797
3798 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3799 if (unlikely(r != 0))
3800 return r;
3801
3802 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3803 if (unlikely(r != 0))
3804 return r;
3805
3806 gfx_v9_0_kiq_init_queue(ring);
3807 amdgpu_bo_kunmap(ring->mqd_obj);
3808 ring->mqd_ptr = NULL;
3809 amdgpu_bo_unreserve(ring->mqd_obj);
3810 ring->sched.ready = true;
3811 return 0;
3812 }
3813
gfx_v9_0_kcq_resume(struct amdgpu_device * adev)3814 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3815 {
3816 struct amdgpu_ring *ring = NULL;
3817 int r = 0, i;
3818
3819 gfx_v9_0_cp_compute_enable(adev, true);
3820
3821 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3822 ring = &adev->gfx.compute_ring[i];
3823
3824 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3825 if (unlikely(r != 0))
3826 goto done;
3827 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3828 if (!r) {
3829 r = gfx_v9_0_kcq_init_queue(ring);
3830 amdgpu_bo_kunmap(ring->mqd_obj);
3831 ring->mqd_ptr = NULL;
3832 }
3833 amdgpu_bo_unreserve(ring->mqd_obj);
3834 if (r)
3835 goto done;
3836 }
3837
3838 r = amdgpu_gfx_enable_kcq(adev);
3839 done:
3840 return r;
3841 }
3842
gfx_v9_0_cp_resume(struct amdgpu_device * adev)3843 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3844 {
3845 int r, i;
3846 struct amdgpu_ring *ring;
3847
3848 if (!(adev->flags & AMD_IS_APU))
3849 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3850
3851 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3852 if (adev->asic_type != CHIP_ARCTURUS) {
3853 /* legacy firmware loading */
3854 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3855 if (r)
3856 return r;
3857 }
3858
3859 r = gfx_v9_0_cp_compute_load_microcode(adev);
3860 if (r)
3861 return r;
3862 }
3863
3864 r = gfx_v9_0_kiq_resume(adev);
3865 if (r)
3866 return r;
3867
3868 if (adev->asic_type != CHIP_ARCTURUS) {
3869 r = gfx_v9_0_cp_gfx_resume(adev);
3870 if (r)
3871 return r;
3872 }
3873
3874 r = gfx_v9_0_kcq_resume(adev);
3875 if (r)
3876 return r;
3877
3878 if (adev->asic_type != CHIP_ARCTURUS) {
3879 ring = &adev->gfx.gfx_ring[0];
3880 r = amdgpu_ring_test_helper(ring);
3881 if (r)
3882 return r;
3883 }
3884
3885 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3886 ring = &adev->gfx.compute_ring[i];
3887 amdgpu_ring_test_helper(ring);
3888 }
3889
3890 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3891
3892 return 0;
3893 }
3894
gfx_v9_0_init_tcp_config(struct amdgpu_device * adev)3895 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
3896 {
3897 u32 tmp;
3898
3899 if (adev->asic_type != CHIP_ARCTURUS)
3900 return;
3901
3902 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
3903 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
3904 adev->df.hash_status.hash_64k);
3905 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
3906 adev->df.hash_status.hash_2m);
3907 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
3908 adev->df.hash_status.hash_1g);
3909 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
3910 }
3911
gfx_v9_0_cp_enable(struct amdgpu_device * adev,bool enable)3912 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3913 {
3914 if (adev->asic_type != CHIP_ARCTURUS)
3915 gfx_v9_0_cp_gfx_enable(adev, enable);
3916 gfx_v9_0_cp_compute_enable(adev, enable);
3917 }
3918
gfx_v9_0_hw_init(void * handle)3919 static int gfx_v9_0_hw_init(void *handle)
3920 {
3921 int r;
3922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3923
3924 if (!amdgpu_sriov_vf(adev))
3925 gfx_v9_0_init_golden_registers(adev);
3926
3927 gfx_v9_0_constants_init(adev);
3928
3929 gfx_v9_0_init_tcp_config(adev);
3930
3931 r = adev->gfx.rlc.funcs->resume(adev);
3932 if (r)
3933 return r;
3934
3935 r = gfx_v9_0_cp_resume(adev);
3936 if (r)
3937 return r;
3938
3939 return r;
3940 }
3941
gfx_v9_0_hw_fini(void * handle)3942 static int gfx_v9_0_hw_fini(void *handle)
3943 {
3944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3945
3946 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3947 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3948 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3949
3950 /* DF freeze and kcq disable will fail */
3951 if (!amdgpu_ras_intr_triggered())
3952 /* disable KCQ to avoid CPC touch memory not valid anymore */
3953 amdgpu_gfx_disable_kcq(adev);
3954
3955 if (amdgpu_sriov_vf(adev)) {
3956 gfx_v9_0_cp_gfx_enable(adev, false);
3957 /* must disable polling for SRIOV when hw finished, otherwise
3958 * CPC engine may still keep fetching WB address which is already
3959 * invalid after sw finished and trigger DMAR reading error in
3960 * hypervisor side.
3961 */
3962 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3963 return 0;
3964 }
3965
3966 /* Use deinitialize sequence from CAIL when unbinding device from driver,
3967 * otherwise KIQ is hanging when binding back
3968 */
3969 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3970 mutex_lock(&adev->srbm_mutex);
3971 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3972 adev->gfx.kiq.ring.pipe,
3973 adev->gfx.kiq.ring.queue, 0);
3974 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3975 soc15_grbm_select(adev, 0, 0, 0, 0);
3976 mutex_unlock(&adev->srbm_mutex);
3977 }
3978
3979 gfx_v9_0_cp_enable(adev, false);
3980 adev->gfx.rlc.funcs->stop(adev);
3981
3982 return 0;
3983 }
3984
gfx_v9_0_suspend(void * handle)3985 static int gfx_v9_0_suspend(void *handle)
3986 {
3987 return gfx_v9_0_hw_fini(handle);
3988 }
3989
gfx_v9_0_resume(void * handle)3990 static int gfx_v9_0_resume(void *handle)
3991 {
3992 return gfx_v9_0_hw_init(handle);
3993 }
3994
gfx_v9_0_is_idle(void * handle)3995 static bool gfx_v9_0_is_idle(void *handle)
3996 {
3997 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3998
3999 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
4000 GRBM_STATUS, GUI_ACTIVE))
4001 return false;
4002 else
4003 return true;
4004 }
4005
gfx_v9_0_wait_for_idle(void * handle)4006 static int gfx_v9_0_wait_for_idle(void *handle)
4007 {
4008 unsigned i;
4009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4010
4011 for (i = 0; i < adev->usec_timeout; i++) {
4012 if (gfx_v9_0_is_idle(handle))
4013 return 0;
4014 udelay(1);
4015 }
4016 return -ETIMEDOUT;
4017 }
4018
gfx_v9_0_soft_reset(void * handle)4019 static int gfx_v9_0_soft_reset(void *handle)
4020 {
4021 u32 grbm_soft_reset = 0;
4022 u32 tmp;
4023 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4024
4025 /* GRBM_STATUS */
4026 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
4027 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4028 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4029 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4030 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4031 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4032 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4033 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4034 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4035 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4036 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4037 }
4038
4039 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4040 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4041 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4042 }
4043
4044 /* GRBM_STATUS2 */
4045 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
4046 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4047 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4048 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4049
4050
4051 if (grbm_soft_reset) {
4052 /* stop the rlc */
4053 adev->gfx.rlc.funcs->stop(adev);
4054
4055 if (adev->asic_type != CHIP_ARCTURUS)
4056 /* Disable GFX parsing/prefetching */
4057 gfx_v9_0_cp_gfx_enable(adev, false);
4058
4059 /* Disable MEC parsing/prefetching */
4060 gfx_v9_0_cp_compute_enable(adev, false);
4061
4062 if (grbm_soft_reset) {
4063 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
4064 tmp |= grbm_soft_reset;
4065 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4066 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
4067 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
4068
4069 udelay(50);
4070
4071 tmp &= ~grbm_soft_reset;
4072 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
4073 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
4074 }
4075
4076 /* Wait a little for things to settle down */
4077 udelay(50);
4078 }
4079 return 0;
4080 }
4081
gfx_v9_0_kiq_read_clock(struct amdgpu_device * adev)4082 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev)
4083 {
4084 signed long r, cnt = 0;
4085 unsigned long flags;
4086 uint32_t seq, reg_val_offs = 0;
4087 uint64_t value = 0;
4088 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4089 struct amdgpu_ring *ring = &kiq->ring;
4090
4091 BUG_ON(!ring->funcs->emit_rreg);
4092
4093 spin_lock_irqsave(&kiq->ring_lock, flags);
4094 if (amdgpu_device_wb_get(adev, ®_val_offs)) {
4095 pr_err("critical bug! too many kiq readers\n");
4096 goto failed_unlock;
4097 }
4098 amdgpu_ring_alloc(ring, 32);
4099 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4100 amdgpu_ring_write(ring, 9 | /* src: register*/
4101 (5 << 8) | /* dst: memory */
4102 (1 << 16) | /* count sel */
4103 (1 << 20)); /* write confirm */
4104 amdgpu_ring_write(ring, 0);
4105 amdgpu_ring_write(ring, 0);
4106 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4107 reg_val_offs * 4));
4108 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4109 reg_val_offs * 4));
4110 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
4111 if (r)
4112 goto failed_undo;
4113
4114 amdgpu_ring_commit(ring);
4115 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4116
4117 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
4118
4119 /* don't wait anymore for gpu reset case because this way may
4120 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
4121 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
4122 * never return if we keep waiting in virt_kiq_rreg, which cause
4123 * gpu_recover() hang there.
4124 *
4125 * also don't wait anymore for IRQ context
4126 * */
4127 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
4128 goto failed_kiq_read;
4129
4130 might_sleep();
4131 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
4132 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
4133 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
4134 }
4135
4136 if (cnt > MAX_KIQ_REG_TRY)
4137 goto failed_kiq_read;
4138
4139 mb();
4140 value = (uint64_t)adev->wb.wb[reg_val_offs] |
4141 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL;
4142 amdgpu_device_wb_free(adev, reg_val_offs);
4143 return value;
4144
4145 failed_undo:
4146 amdgpu_ring_undo(ring);
4147 failed_unlock:
4148 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4149 failed_kiq_read:
4150 if (reg_val_offs)
4151 amdgpu_device_wb_free(adev, reg_val_offs);
4152 pr_err("failed to read gpu clock\n");
4153 return ~0;
4154 }
4155
gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device * adev)4156 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4157 {
4158 uint64_t clock, clock_lo, clock_hi, hi_check;
4159
4160 switch (adev->asic_type) {
4161 case CHIP_RENOIR:
4162 preempt_disable();
4163 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
4164 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
4165 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
4166 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
4167 * roughly every 42 seconds.
4168 */
4169 if (hi_check != clock_hi) {
4170 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
4171 clock_hi = hi_check;
4172 }
4173 preempt_enable();
4174 clock = clock_lo | (clock_hi << 32ULL);
4175 break;
4176 default:
4177 amdgpu_gfx_off_ctrl(adev, false);
4178 mutex_lock(&adev->gfx.gpu_clock_mutex);
4179 if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
4180 clock = gfx_v9_0_kiq_read_clock(adev);
4181 } else {
4182 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4183 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
4184 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4185 }
4186 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4187 amdgpu_gfx_off_ctrl(adev, true);
4188 break;
4189 }
4190 return clock;
4191 }
4192
gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)4193 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4194 uint32_t vmid,
4195 uint32_t gds_base, uint32_t gds_size,
4196 uint32_t gws_base, uint32_t gws_size,
4197 uint32_t oa_base, uint32_t oa_size)
4198 {
4199 struct amdgpu_device *adev = ring->adev;
4200
4201 /* GDS Base */
4202 gfx_v9_0_write_data_to_reg(ring, 0, false,
4203 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
4204 gds_base);
4205
4206 /* GDS Size */
4207 gfx_v9_0_write_data_to_reg(ring, 0, false,
4208 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
4209 gds_size);
4210
4211 /* GWS */
4212 gfx_v9_0_write_data_to_reg(ring, 0, false,
4213 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
4214 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4215
4216 /* OA */
4217 gfx_v9_0_write_data_to_reg(ring, 0, false,
4218 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
4219 (1 << (oa_size + oa_base)) - (1 << oa_base));
4220 }
4221
4222 static const u32 vgpr_init_compute_shader[] =
4223 {
4224 0xb07c0000, 0xbe8000ff,
4225 0x000000f8, 0xbf110800,
4226 0x7e000280, 0x7e020280,
4227 0x7e040280, 0x7e060280,
4228 0x7e080280, 0x7e0a0280,
4229 0x7e0c0280, 0x7e0e0280,
4230 0x80808800, 0xbe803200,
4231 0xbf84fff5, 0xbf9c0000,
4232 0xd28c0001, 0x0001007f,
4233 0xd28d0001, 0x0002027e,
4234 0x10020288, 0xb8810904,
4235 0xb7814000, 0xd1196a01,
4236 0x00000301, 0xbe800087,
4237 0xbefc00c1, 0xd89c4000,
4238 0x00020201, 0xd89cc080,
4239 0x00040401, 0x320202ff,
4240 0x00000800, 0x80808100,
4241 0xbf84fff8, 0x7e020280,
4242 0xbf810000, 0x00000000,
4243 };
4244
4245 static const u32 sgpr_init_compute_shader[] =
4246 {
4247 0xb07c0000, 0xbe8000ff,
4248 0x0000005f, 0xbee50080,
4249 0xbe812c65, 0xbe822c65,
4250 0xbe832c65, 0xbe842c65,
4251 0xbe852c65, 0xb77c0005,
4252 0x80808500, 0xbf84fff8,
4253 0xbe800080, 0xbf810000,
4254 };
4255
4256 static const u32 vgpr_init_compute_shader_arcturus[] = {
4257 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080,
4258 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080,
4259 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080,
4260 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080,
4261 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080,
4262 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080,
4263 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080,
4264 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080,
4265 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080,
4266 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080,
4267 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080,
4268 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080,
4269 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080,
4270 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080,
4271 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080,
4272 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080,
4273 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080,
4274 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080,
4275 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080,
4276 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080,
4277 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080,
4278 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080,
4279 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080,
4280 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080,
4281 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080,
4282 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080,
4283 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080,
4284 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080,
4285 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080,
4286 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080,
4287 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080,
4288 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080,
4289 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080,
4290 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080,
4291 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080,
4292 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080,
4293 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080,
4294 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080,
4295 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080,
4296 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080,
4297 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080,
4298 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080,
4299 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080,
4300 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080,
4301 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080,
4302 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080,
4303 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080,
4304 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080,
4305 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080,
4306 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080,
4307 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080,
4308 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080,
4309 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080,
4310 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080,
4311 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080,
4312 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080,
4313 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080,
4314 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080,
4315 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080,
4316 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080,
4317 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080,
4318 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080,
4319 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080,
4320 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080,
4321 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080,
4322 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080,
4323 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080,
4324 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080,
4325 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080,
4326 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080,
4327 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080,
4328 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080,
4329 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080,
4330 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080,
4331 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080,
4332 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080,
4333 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080,
4334 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080,
4335 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080,
4336 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080,
4337 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080,
4338 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080,
4339 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080,
4340 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080,
4341 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080,
4342 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a,
4343 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280,
4344 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000,
4345 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904,
4346 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000,
4347 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a,
4348 0xbf84fff8, 0xbf810000,
4349 };
4350
4351 /* When below register arrays changed, please update gpr_reg_size,
4352 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
4353 to cover all gfx9 ASICs */
4354 static const struct soc15_reg_entry vgpr_init_regs[] = {
4355 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4356 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4357 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4358 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4359 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
4360 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
4361 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4362 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4366 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4367 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4368 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4369 };
4370
4371 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = {
4372 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4373 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4374 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4375 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4376 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf },
4377 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */
4378 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4379 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4380 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4381 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4382 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4383 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4384 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4385 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4386 };
4387
4388 static const struct soc15_reg_entry sgpr1_init_regs[] = {
4389 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4390 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4391 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4392 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4393 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4394 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4395 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
4396 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
4397 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
4398 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
4399 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff },
4400 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff },
4401 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff },
4402 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff },
4403 };
4404
4405 static const struct soc15_reg_entry sgpr2_init_regs[] = {
4406 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4407 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4408 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4409 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4410 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4411 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4412 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
4413 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
4414 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
4415 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
4416 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 },
4417 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 },
4418 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 },
4419 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 },
4420 };
4421
4422 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = {
4423 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1},
4424 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1},
4425 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
4426 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1},
4427 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1},
4428 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1},
4429 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1},
4430 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1},
4431 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
4432 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1},
4433 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1},
4434 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1},
4435 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1},
4436 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6},
4437 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16},
4438 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
4439 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
4440 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
4441 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
4442 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
4443 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
4444 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
4445 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
4446 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
4447 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16},
4448 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1},
4449 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1},
4450 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32},
4451 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32},
4452 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72},
4453 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
4454 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
4455 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
4456 };
4457
gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device * adev)4458 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
4459 {
4460 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4461 int i, r;
4462
4463 /* only support when RAS is enabled */
4464 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4465 return 0;
4466
4467 r = amdgpu_ring_alloc(ring, 7);
4468 if (r) {
4469 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
4470 ring->name, r);
4471 return r;
4472 }
4473
4474 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000);
4475 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size);
4476
4477 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
4478 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
4479 PACKET3_DMA_DATA_DST_SEL(1) |
4480 PACKET3_DMA_DATA_SRC_SEL(2) |
4481 PACKET3_DMA_DATA_ENGINE(0)));
4482 amdgpu_ring_write(ring, 0);
4483 amdgpu_ring_write(ring, 0);
4484 amdgpu_ring_write(ring, 0);
4485 amdgpu_ring_write(ring, 0);
4486 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
4487 adev->gds.gds_size);
4488
4489 amdgpu_ring_commit(ring);
4490
4491 for (i = 0; i < adev->usec_timeout; i++) {
4492 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring))
4493 break;
4494 udelay(1);
4495 }
4496
4497 if (i >= adev->usec_timeout)
4498 r = -ETIMEDOUT;
4499
4500 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000);
4501
4502 return r;
4503 }
4504
gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device * adev)4505 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
4506 {
4507 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4508 struct amdgpu_ib ib;
4509 struct dma_fence *f = NULL;
4510 int r, i;
4511 unsigned total_size, vgpr_offset, sgpr_offset;
4512 u64 gpu_addr;
4513
4514 int compute_dim_x = adev->gfx.config.max_shader_engines *
4515 adev->gfx.config.max_cu_per_sh *
4516 adev->gfx.config.max_sh_per_se;
4517 int sgpr_work_group_size = 5;
4518 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6;
4519 int vgpr_init_shader_size;
4520 const u32 *vgpr_init_shader_ptr;
4521 const struct soc15_reg_entry *vgpr_init_regs_ptr;
4522
4523 /* only support when RAS is enabled */
4524 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4525 return 0;
4526
4527 /* bail if the compute ring is not ready */
4528 if (!ring->sched.ready)
4529 return 0;
4530
4531 if (adev->asic_type == CHIP_ARCTURUS) {
4532 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
4533 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
4534 vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
4535 } else {
4536 vgpr_init_shader_ptr = vgpr_init_compute_shader;
4537 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader);
4538 vgpr_init_regs_ptr = vgpr_init_regs;
4539 }
4540
4541 total_size =
4542 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */
4543 total_size +=
4544 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */
4545 total_size +=
4546 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */
4547 total_size = ALIGN(total_size, 256);
4548 vgpr_offset = total_size;
4549 total_size += ALIGN(vgpr_init_shader_size, 256);
4550 sgpr_offset = total_size;
4551 total_size += sizeof(sgpr_init_compute_shader);
4552
4553 /* allocate an indirect buffer to put the commands in */
4554 memset(&ib, 0, sizeof(ib));
4555 r = amdgpu_ib_get(adev, NULL, total_size,
4556 AMDGPU_IB_POOL_DIRECT, &ib);
4557 if (r) {
4558 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
4559 return r;
4560 }
4561
4562 /* load the compute shaders */
4563 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)
4564 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i];
4565
4566 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
4567 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
4568
4569 /* init the ib length to 0 */
4570 ib.length_dw = 0;
4571
4572 /* VGPR */
4573 /* write the register state for the compute dispatch */
4574 for (i = 0; i < gpr_reg_size; i++) {
4575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4576 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])
4577 - PACKET3_SET_SH_REG_START;
4578 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;
4579 }
4580 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4581 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
4582 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4583 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4584 - PACKET3_SET_SH_REG_START;
4585 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4586 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4587
4588 /* write dispatch packet */
4589 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4590 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */
4591 ib.ptr[ib.length_dw++] = 1; /* y */
4592 ib.ptr[ib.length_dw++] = 1; /* z */
4593 ib.ptr[ib.length_dw++] =
4594 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4595
4596 /* write CS partial flush packet */
4597 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4598 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4599
4600 /* SGPR1 */
4601 /* write the register state for the compute dispatch */
4602 for (i = 0; i < gpr_reg_size; i++) {
4603 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4604 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
4605 - PACKET3_SET_SH_REG_START;
4606 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4607 }
4608 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4609 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4610 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4611 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4612 - PACKET3_SET_SH_REG_START;
4613 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4614 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4615
4616 /* write dispatch packet */
4617 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4618 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4619 ib.ptr[ib.length_dw++] = 1; /* y */
4620 ib.ptr[ib.length_dw++] = 1; /* z */
4621 ib.ptr[ib.length_dw++] =
4622 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4623
4624 /* write CS partial flush packet */
4625 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4626 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4627
4628 /* SGPR2 */
4629 /* write the register state for the compute dispatch */
4630 for (i = 0; i < gpr_reg_size; i++) {
4631 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4632 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
4633 - PACKET3_SET_SH_REG_START;
4634 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
4635 }
4636 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4637 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4638 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4639 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4640 - PACKET3_SET_SH_REG_START;
4641 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4642 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4643
4644 /* write dispatch packet */
4645 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4646 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4647 ib.ptr[ib.length_dw++] = 1; /* y */
4648 ib.ptr[ib.length_dw++] = 1; /* z */
4649 ib.ptr[ib.length_dw++] =
4650 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4651
4652 /* write CS partial flush packet */
4653 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4654 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4655
4656 /* shedule the ib on the ring */
4657 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4658 if (r) {
4659 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
4660 goto fail;
4661 }
4662
4663 /* wait for the GPU to finish processing the IB */
4664 r = dma_fence_wait(f, false);
4665 if (r) {
4666 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
4667 goto fail;
4668 }
4669
4670 fail:
4671 amdgpu_ib_free(adev, &ib, NULL);
4672 dma_fence_put(f);
4673
4674 return r;
4675 }
4676
gfx_v9_0_early_init(void * handle)4677 static int gfx_v9_0_early_init(void *handle)
4678 {
4679 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4680
4681 if (adev->asic_type == CHIP_ARCTURUS)
4682 adev->gfx.num_gfx_rings = 0;
4683 else
4684 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
4685 adev->gfx.num_compute_rings = amdgpu_num_kcq;
4686 gfx_v9_0_set_kiq_pm4_funcs(adev);
4687 gfx_v9_0_set_ring_funcs(adev);
4688 gfx_v9_0_set_irq_funcs(adev);
4689 gfx_v9_0_set_gds_init(adev);
4690 gfx_v9_0_set_rlc_funcs(adev);
4691
4692 return 0;
4693 }
4694
gfx_v9_0_ecc_late_init(void * handle)4695 static int gfx_v9_0_ecc_late_init(void *handle)
4696 {
4697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4698 int r;
4699
4700 /*
4701 * Temp workaround to fix the issue that CP firmware fails to
4702 * update read pointer when CPDMA is writing clearing operation
4703 * to GDS in suspend/resume sequence on several cards. So just
4704 * limit this operation in cold boot sequence.
4705 */
4706 if (!adev->in_suspend) {
4707 r = gfx_v9_0_do_edc_gds_workarounds(adev);
4708 if (r)
4709 return r;
4710 }
4711
4712 /* requires IBs so do in late init after IB pool is initialized */
4713 r = gfx_v9_0_do_edc_gpr_workarounds(adev);
4714 if (r)
4715 return r;
4716
4717 if (adev->gfx.funcs &&
4718 adev->gfx.funcs->reset_ras_error_count)
4719 adev->gfx.funcs->reset_ras_error_count(adev);
4720
4721 r = amdgpu_gfx_ras_late_init(adev);
4722 if (r)
4723 return r;
4724
4725 return 0;
4726 }
4727
gfx_v9_0_late_init(void * handle)4728 static int gfx_v9_0_late_init(void *handle)
4729 {
4730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4731 int r;
4732
4733 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4734 if (r)
4735 return r;
4736
4737 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4738 if (r)
4739 return r;
4740
4741 r = gfx_v9_0_ecc_late_init(handle);
4742 if (r)
4743 return r;
4744
4745 return 0;
4746 }
4747
gfx_v9_0_is_rlc_enabled(struct amdgpu_device * adev)4748 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
4749 {
4750 uint32_t rlc_setting;
4751
4752 /* if RLC is not enabled, do nothing */
4753 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4754 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
4755 return false;
4756
4757 return true;
4758 }
4759
gfx_v9_0_set_safe_mode(struct amdgpu_device * adev)4760 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev)
4761 {
4762 uint32_t data;
4763 unsigned i;
4764
4765 data = RLC_SAFE_MODE__CMD_MASK;
4766 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4767 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4768
4769 /* wait for RLC_SAFE_MODE */
4770 for (i = 0; i < adev->usec_timeout; i++) {
4771 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4772 break;
4773 udelay(1);
4774 }
4775 }
4776
gfx_v9_0_unset_safe_mode(struct amdgpu_device * adev)4777 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev)
4778 {
4779 uint32_t data;
4780
4781 data = RLC_SAFE_MODE__CMD_MASK;
4782 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4783 }
4784
gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)4785 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
4786 bool enable)
4787 {
4788 amdgpu_gfx_rlc_enter_safe_mode(adev);
4789
4790 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
4791 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
4792 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4793 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
4794 } else {
4795 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
4796 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4797 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
4798 }
4799
4800 amdgpu_gfx_rlc_exit_safe_mode(adev);
4801 }
4802
gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device * adev,bool enable)4803 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
4804 bool enable)
4805 {
4806 /* TODO: double check if we need to perform under safe mode */
4807 /* gfx_v9_0_enter_rlc_safe_mode(adev); */
4808
4809 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
4810 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
4811 else
4812 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
4813
4814 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
4815 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
4816 else
4817 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
4818
4819 /* gfx_v9_0_exit_rlc_safe_mode(adev); */
4820 }
4821
gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)4822 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4823 bool enable)
4824 {
4825 uint32_t data, def;
4826
4827 amdgpu_gfx_rlc_enter_safe_mode(adev);
4828
4829 /* It is disabled by HW by default */
4830 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4831 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4832 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4833
4834 if (adev->asic_type != CHIP_VEGA12)
4835 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4836
4837 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4838 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4839 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4840
4841 /* only for Vega10 & Raven1 */
4842 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4843
4844 if (def != data)
4845 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4846
4847 /* MGLS is a global flag to control all MGLS in GFX */
4848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4849 /* 2 - RLC memory Light sleep */
4850 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4851 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4852 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4853 if (def != data)
4854 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4855 }
4856 /* 3 - CP memory Light sleep */
4857 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4858 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4859 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4860 if (def != data)
4861 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4862 }
4863 }
4864 } else {
4865 /* 1 - MGCG_OVERRIDE */
4866 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4867
4868 if (adev->asic_type != CHIP_VEGA12)
4869 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4870
4871 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4872 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4873 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4874 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4875
4876 if (def != data)
4877 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4878
4879 /* 2 - disable MGLS in RLC */
4880 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4881 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4882 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4883 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4884 }
4885
4886 /* 3 - disable MGLS in CP */
4887 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4888 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4889 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4890 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4891 }
4892 }
4893
4894 amdgpu_gfx_rlc_exit_safe_mode(adev);
4895 }
4896
gfx_v9_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)4897 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
4898 bool enable)
4899 {
4900 uint32_t data, def;
4901
4902 if (adev->asic_type == CHIP_ARCTURUS)
4903 return;
4904
4905 amdgpu_gfx_rlc_enter_safe_mode(adev);
4906
4907 /* Enable 3D CGCG/CGLS */
4908 if (enable) {
4909 /* write cmd to clear cgcg/cgls ov */
4910 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4911 /* unset CGCG override */
4912 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4913 /* update CGCG and CGLS override bits */
4914 if (def != data)
4915 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4916
4917 /* enable 3Dcgcg FSM(0x0000363f) */
4918 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4919
4920 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4921 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4922 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4923 else
4924 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
4925
4926 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4927 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4928 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4929 if (def != data)
4930 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4931
4932 /* set IDLE_POLL_COUNT(0x00900100) */
4933 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4934 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4935 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4936 if (def != data)
4937 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4938 } else {
4939 /* Disable CGCG/CGLS */
4940 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4941 /* disable cgcg, cgls should be disabled */
4942 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4943 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4944 /* disable cgcg and cgls in FSM */
4945 if (def != data)
4946 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4947 }
4948
4949 amdgpu_gfx_rlc_exit_safe_mode(adev);
4950 }
4951
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)4952 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4953 bool enable)
4954 {
4955 uint32_t def, data;
4956
4957 amdgpu_gfx_rlc_enter_safe_mode(adev);
4958
4959 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4960 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4961 /* unset CGCG override */
4962 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4963 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4964 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4965 else
4966 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4967 /* update CGCG and CGLS override bits */
4968 if (def != data)
4969 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4970
4971 /* enable cgcg FSM(0x0000363F) */
4972 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4973
4974 if (adev->asic_type == CHIP_ARCTURUS)
4975 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4976 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4977 else
4978 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4979 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4980 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4981 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4982 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4983 if (def != data)
4984 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4985
4986 /* set IDLE_POLL_COUNT(0x00900100) */
4987 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4988 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4989 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4990 if (def != data)
4991 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4992 } else {
4993 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4994 /* reset CGCG/CGLS bits */
4995 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4996 /* disable cgcg and cgls in FSM */
4997 if (def != data)
4998 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4999 }
5000
5001 amdgpu_gfx_rlc_exit_safe_mode(adev);
5002 }
5003
gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)5004 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5005 bool enable)
5006 {
5007 if (enable) {
5008 /* CGCG/CGLS should be enabled after MGCG/MGLS
5009 * === MGCG + MGLS ===
5010 */
5011 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
5012 /* === CGCG /CGLS for GFX 3D Only === */
5013 gfx_v9_0_update_3d_clock_gating(adev, enable);
5014 /* === CGCG + CGLS === */
5015 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
5016 } else {
5017 /* CGCG/CGLS should be disabled before MGCG/MGLS
5018 * === CGCG + CGLS ===
5019 */
5020 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
5021 /* === CGCG /CGLS for GFX 3D Only === */
5022 gfx_v9_0_update_3d_clock_gating(adev, enable);
5023 /* === MGCG + MGLS === */
5024 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
5025 }
5026 return 0;
5027 }
5028
gfx_v9_0_update_spm_vmid(struct amdgpu_device * adev,unsigned vmid)5029 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5030 {
5031 u32 reg, data;
5032
5033 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
5034 if (amdgpu_sriov_is_pp_one_vf(adev))
5035 data = RREG32_NO_KIQ(reg);
5036 else
5037 data = RREG32(reg);
5038
5039 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
5040 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
5041
5042 if (amdgpu_sriov_is_pp_one_vf(adev))
5043 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
5044 else
5045 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
5046 }
5047
gfx_v9_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)5048 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,
5049 uint32_t offset,
5050 struct soc15_reg_rlcg *entries, int arr_size)
5051 {
5052 int i;
5053 uint32_t reg;
5054
5055 if (!entries)
5056 return false;
5057
5058 for (i = 0; i < arr_size; i++) {
5059 const struct soc15_reg_rlcg *entry;
5060
5061 entry = &entries[i];
5062 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
5063 if (offset == reg)
5064 return true;
5065 }
5066
5067 return false;
5068 }
5069
gfx_v9_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)5070 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
5071 {
5072 return gfx_v9_0_check_rlcg_range(adev, offset,
5073 (void *)rlcg_access_gc_9_0,
5074 ARRAY_SIZE(rlcg_access_gc_9_0));
5075 }
5076
5077 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
5078 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
5079 .set_safe_mode = gfx_v9_0_set_safe_mode,
5080 .unset_safe_mode = gfx_v9_0_unset_safe_mode,
5081 .init = gfx_v9_0_rlc_init,
5082 .get_csb_size = gfx_v9_0_get_csb_size,
5083 .get_csb_buffer = gfx_v9_0_get_csb_buffer,
5084 .get_cp_table_num = gfx_v9_0_cp_jump_table_num,
5085 .resume = gfx_v9_0_rlc_resume,
5086 .stop = gfx_v9_0_rlc_stop,
5087 .reset = gfx_v9_0_rlc_reset,
5088 .start = gfx_v9_0_rlc_start,
5089 .update_spm_vmid = gfx_v9_0_update_spm_vmid,
5090 .rlcg_wreg = gfx_v9_0_rlcg_wreg,
5091 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
5092 };
5093
gfx_v9_0_set_powergating_state(void * handle,enum amd_powergating_state state)5094 static int gfx_v9_0_set_powergating_state(void *handle,
5095 enum amd_powergating_state state)
5096 {
5097 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5098 bool enable = (state == AMD_PG_STATE_GATE);
5099
5100 switch (adev->asic_type) {
5101 case CHIP_RAVEN:
5102 case CHIP_RENOIR:
5103 if (!enable)
5104 amdgpu_gfx_off_ctrl(adev, false);
5105
5106 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5107 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
5108 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
5109 } else {
5110 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
5111 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
5112 }
5113
5114 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5115 gfx_v9_0_enable_cp_power_gating(adev, true);
5116 else
5117 gfx_v9_0_enable_cp_power_gating(adev, false);
5118
5119 /* update gfx cgpg state */
5120 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
5121
5122 /* update mgcg state */
5123 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
5124
5125 if (enable)
5126 amdgpu_gfx_off_ctrl(adev, true);
5127 break;
5128 case CHIP_VEGA12:
5129 amdgpu_gfx_off_ctrl(adev, enable);
5130 break;
5131 default:
5132 break;
5133 }
5134
5135 return 0;
5136 }
5137
gfx_v9_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)5138 static int gfx_v9_0_set_clockgating_state(void *handle,
5139 enum amd_clockgating_state state)
5140 {
5141 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5142
5143 if (amdgpu_sriov_vf(adev))
5144 return 0;
5145
5146 switch (adev->asic_type) {
5147 case CHIP_VEGA10:
5148 case CHIP_VEGA12:
5149 case CHIP_VEGA20:
5150 case CHIP_RAVEN:
5151 case CHIP_ARCTURUS:
5152 case CHIP_RENOIR:
5153 gfx_v9_0_update_gfx_clock_gating(adev,
5154 state == AMD_CG_STATE_GATE);
5155 break;
5156 default:
5157 break;
5158 }
5159 return 0;
5160 }
5161
gfx_v9_0_get_clockgating_state(void * handle,u32 * flags)5162 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
5163 {
5164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5165 int data;
5166
5167 if (amdgpu_sriov_vf(adev))
5168 *flags = 0;
5169
5170 /* AMD_CG_SUPPORT_GFX_MGCG */
5171 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
5172 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5173 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5174
5175 /* AMD_CG_SUPPORT_GFX_CGCG */
5176 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
5177 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5178 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5179
5180 /* AMD_CG_SUPPORT_GFX_CGLS */
5181 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5182 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5183
5184 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5185 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
5186 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5187 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5188
5189 /* AMD_CG_SUPPORT_GFX_CP_LS */
5190 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
5191 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5192 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5193
5194 if (adev->asic_type != CHIP_ARCTURUS) {
5195 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5196 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
5197 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5198 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5199
5200 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5201 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5202 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5203 }
5204 }
5205
gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)5206 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5207 {
5208 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
5209 }
5210
gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)5211 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5212 {
5213 struct amdgpu_device *adev = ring->adev;
5214 u64 wptr;
5215
5216 /* XXX check if swapping is necessary on BE */
5217 if (ring->use_doorbell) {
5218 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
5219 } else {
5220 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
5221 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
5222 }
5223
5224 return wptr;
5225 }
5226
gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)5227 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5228 {
5229 struct amdgpu_device *adev = ring->adev;
5230
5231 if (ring->use_doorbell) {
5232 /* XXX check if swapping is necessary on BE */
5233 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
5234 WDOORBELL64(ring->doorbell_index, ring->wptr);
5235 } else {
5236 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5237 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5238 }
5239 }
5240
gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)5241 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5242 {
5243 struct amdgpu_device *adev = ring->adev;
5244 u32 ref_and_mask, reg_mem_engine;
5245 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5246
5247 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5248 switch (ring->me) {
5249 case 1:
5250 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5251 break;
5252 case 2:
5253 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5254 break;
5255 default:
5256 return;
5257 }
5258 reg_mem_engine = 0;
5259 } else {
5260 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5261 reg_mem_engine = 1; /* pfp */
5262 }
5263
5264 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5265 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5266 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5267 ref_and_mask, ref_and_mask, 0x20);
5268 }
5269
gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)5270 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5271 struct amdgpu_job *job,
5272 struct amdgpu_ib *ib,
5273 uint32_t flags)
5274 {
5275 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5276 u32 header, control = 0;
5277
5278 if (ib->flags & AMDGPU_IB_FLAG_CE)
5279 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5280 else
5281 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5282
5283 control |= ib->length_dw | (vmid << 24);
5284
5285 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5286 control |= INDIRECT_BUFFER_PRE_ENB(1);
5287
5288 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
5289 gfx_v9_0_ring_emit_de_meta(ring);
5290 }
5291
5292 amdgpu_ring_write(ring, header);
5293 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5294 amdgpu_ring_write(ring,
5295 #ifdef __BIG_ENDIAN
5296 (2 << 0) |
5297 #endif
5298 lower_32_bits(ib->gpu_addr));
5299 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5300 amdgpu_ring_write(ring, control);
5301 }
5302
gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)5303 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5304 struct amdgpu_job *job,
5305 struct amdgpu_ib *ib,
5306 uint32_t flags)
5307 {
5308 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5309 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5310
5311 /* Currently, there is a high possibility to get wave ID mismatch
5312 * between ME and GDS, leading to a hw deadlock, because ME generates
5313 * different wave IDs than the GDS expects. This situation happens
5314 * randomly when at least 5 compute pipes use GDS ordered append.
5315 * The wave IDs generated by ME are also wrong after suspend/resume.
5316 * Those are probably bugs somewhere else in the kernel driver.
5317 *
5318 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5319 * GDS to 0 for this ring (me/pipe).
5320 */
5321 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5322 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5323 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
5324 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5325 }
5326
5327 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5328 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5329 amdgpu_ring_write(ring,
5330 #ifdef __BIG_ENDIAN
5331 (2 << 0) |
5332 #endif
5333 lower_32_bits(ib->gpu_addr));
5334 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5335 amdgpu_ring_write(ring, control);
5336 }
5337
gfx_v9_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)5338 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5339 u64 seq, unsigned flags)
5340 {
5341 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5342 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5343 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
5344
5345 /* RELEASE_MEM - flush caches, send int */
5346 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5347 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
5348 EOP_TC_NC_ACTION_EN) :
5349 (EOP_TCL1_ACTION_EN |
5350 EOP_TC_ACTION_EN |
5351 EOP_TC_WB_ACTION_EN |
5352 EOP_TC_MD_ACTION_EN)) |
5353 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5354 EVENT_INDEX(5)));
5355 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
5356
5357 /*
5358 * the address should be Qword aligned if 64bit write, Dword
5359 * aligned if only send 32bit data low (discard data high)
5360 */
5361 if (write64bit)
5362 BUG_ON(addr & 0x7);
5363 else
5364 BUG_ON(addr & 0x3);
5365 amdgpu_ring_write(ring, lower_32_bits(addr));
5366 amdgpu_ring_write(ring, upper_32_bits(addr));
5367 amdgpu_ring_write(ring, lower_32_bits(seq));
5368 amdgpu_ring_write(ring, upper_32_bits(seq));
5369 amdgpu_ring_write(ring, 0);
5370 }
5371
gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)5372 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5373 {
5374 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5375 uint32_t seq = ring->fence_drv.sync_seq;
5376 uint64_t addr = ring->fence_drv.gpu_addr;
5377
5378 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
5379 lower_32_bits(addr), upper_32_bits(addr),
5380 seq, 0xffffffff, 4);
5381 }
5382
gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)5383 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5384 unsigned vmid, uint64_t pd_addr)
5385 {
5386 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5387
5388 /* compute doesn't have PFP */
5389 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5390 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5391 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5392 amdgpu_ring_write(ring, 0x0);
5393 }
5394 }
5395
gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring * ring)5396 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5397 {
5398 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
5399 }
5400
gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring * ring)5401 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5402 {
5403 u64 wptr;
5404
5405 /* XXX check if swapping is necessary on BE */
5406 if (ring->use_doorbell)
5407 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
5408 else
5409 BUG();
5410 return wptr;
5411 }
5412
gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring * ring)5413 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5414 {
5415 struct amdgpu_device *adev = ring->adev;
5416
5417 /* XXX check if swapping is necessary on BE */
5418 if (ring->use_doorbell) {
5419 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
5420 WDOORBELL64(ring->doorbell_index, ring->wptr);
5421 } else{
5422 BUG(); /* only DOORBELL method supported on gfx9 now */
5423 }
5424 }
5425
gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)5426 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5427 u64 seq, unsigned int flags)
5428 {
5429 struct amdgpu_device *adev = ring->adev;
5430
5431 /* we only allocate 32bit for each seq wb address */
5432 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5433
5434 /* write fence seq to the "addr" */
5435 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5436 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5437 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5438 amdgpu_ring_write(ring, lower_32_bits(addr));
5439 amdgpu_ring_write(ring, upper_32_bits(addr));
5440 amdgpu_ring_write(ring, lower_32_bits(seq));
5441
5442 if (flags & AMDGPU_FENCE_FLAG_INT) {
5443 /* set register to trigger INT */
5444 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5445 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5446 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5447 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
5448 amdgpu_ring_write(ring, 0);
5449 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5450 }
5451 }
5452
gfx_v9_ring_emit_sb(struct amdgpu_ring * ring)5453 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
5454 {
5455 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5456 amdgpu_ring_write(ring, 0);
5457 }
5458
gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring * ring)5459 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
5460 {
5461 struct v9_ce_ib_state ce_payload = {0};
5462 uint64_t csa_addr;
5463 int cnt;
5464
5465 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
5466 csa_addr = amdgpu_csa_vaddr(ring->adev);
5467
5468 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5469 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
5470 WRITE_DATA_DST_SEL(8) |
5471 WR_CONFIRM) |
5472 WRITE_DATA_CACHE_POLICY(0));
5473 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
5474 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
5475 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
5476 }
5477
gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring * ring)5478 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
5479 {
5480 struct v9_de_ib_state de_payload = {0};
5481 uint64_t csa_addr, gds_addr;
5482 int cnt;
5483
5484 csa_addr = amdgpu_csa_vaddr(ring->adev);
5485 gds_addr = csa_addr + 4096;
5486 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5487 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5488
5489 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5490 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5491 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5492 WRITE_DATA_DST_SEL(8) |
5493 WR_CONFIRM) |
5494 WRITE_DATA_CACHE_POLICY(0));
5495 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
5496 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
5497 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
5498 }
5499
gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)5500 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5501 bool secure)
5502 {
5503 uint32_t v = secure ? FRAME_TMZ : 0;
5504
5505 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5506 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5507 }
5508
gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)5509 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
5510 {
5511 uint32_t dw2 = 0;
5512
5513 if (amdgpu_sriov_vf(ring->adev))
5514 gfx_v9_0_ring_emit_ce_meta(ring);
5515
5516 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5517 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5518 /* set load_global_config & load_global_uconfig */
5519 dw2 |= 0x8001;
5520 /* set load_cs_sh_regs */
5521 dw2 |= 0x01000000;
5522 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5523 dw2 |= 0x10002;
5524
5525 /* set load_ce_ram if preamble presented */
5526 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
5527 dw2 |= 0x10000000;
5528 } else {
5529 /* still load_ce_ram if this is the first time preamble presented
5530 * although there is no context switch happens.
5531 */
5532 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
5533 dw2 |= 0x10000000;
5534 }
5535
5536 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5537 amdgpu_ring_write(ring, dw2);
5538 amdgpu_ring_write(ring, 0);
5539 }
5540
gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)5541 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5542 {
5543 unsigned ret;
5544 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5545 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5546 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5547 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5548 ret = ring->wptr & ring->buf_mask;
5549 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5550 return ret;
5551 }
5552
gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)5553 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5554 {
5555 unsigned cur;
5556 BUG_ON(offset > ring->buf_mask);
5557 BUG_ON(ring->ring[offset] != 0x55aa55aa);
5558
5559 cur = (ring->wptr & ring->buf_mask) - 1;
5560 if (likely(cur > offset))
5561 ring->ring[offset] = cur - offset;
5562 else
5563 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
5564 }
5565
gfx_v9_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)5566 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5567 uint32_t reg_val_offs)
5568 {
5569 struct amdgpu_device *adev = ring->adev;
5570
5571 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5572 amdgpu_ring_write(ring, 0 | /* src: register*/
5573 (5 << 8) | /* dst: memory */
5574 (1 << 20)); /* write confirm */
5575 amdgpu_ring_write(ring, reg);
5576 amdgpu_ring_write(ring, 0);
5577 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5578 reg_val_offs * 4));
5579 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5580 reg_val_offs * 4));
5581 }
5582
gfx_v9_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)5583 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5584 uint32_t val)
5585 {
5586 uint32_t cmd = 0;
5587
5588 switch (ring->funcs->type) {
5589 case AMDGPU_RING_TYPE_GFX:
5590 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5591 break;
5592 case AMDGPU_RING_TYPE_KIQ:
5593 cmd = (1 << 16); /* no inc addr */
5594 break;
5595 default:
5596 cmd = WR_CONFIRM;
5597 break;
5598 }
5599 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5600 amdgpu_ring_write(ring, cmd);
5601 amdgpu_ring_write(ring, reg);
5602 amdgpu_ring_write(ring, 0);
5603 amdgpu_ring_write(ring, val);
5604 }
5605
gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)5606 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5607 uint32_t val, uint32_t mask)
5608 {
5609 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5610 }
5611
gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)5612 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5613 uint32_t reg0, uint32_t reg1,
5614 uint32_t ref, uint32_t mask)
5615 {
5616 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5617 struct amdgpu_device *adev = ring->adev;
5618 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
5619 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
5620
5621 if (fw_version_ok)
5622 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5623 ref, mask, 0x20);
5624 else
5625 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
5626 ref, mask);
5627 }
5628
gfx_v9_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned vmid)5629 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
5630 {
5631 struct amdgpu_device *adev = ring->adev;
5632 uint32_t value = 0;
5633
5634 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5635 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5636 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5637 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5638 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
5639 }
5640
gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)5641 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5642 enum amdgpu_interrupt_state state)
5643 {
5644 switch (state) {
5645 case AMDGPU_IRQ_STATE_DISABLE:
5646 case AMDGPU_IRQ_STATE_ENABLE:
5647 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5648 TIME_STAMP_INT_ENABLE,
5649 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5650 break;
5651 default:
5652 break;
5653 }
5654 }
5655
gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)5656 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5657 int me, int pipe,
5658 enum amdgpu_interrupt_state state)
5659 {
5660 u32 mec_int_cntl, mec_int_cntl_reg;
5661
5662 /*
5663 * amdgpu controls only the first MEC. That's why this function only
5664 * handles the setting of interrupts for this specific MEC. All other
5665 * pipes' interrupts are set by amdkfd.
5666 */
5667
5668 if (me == 1) {
5669 switch (pipe) {
5670 case 0:
5671 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5672 break;
5673 case 1:
5674 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5675 break;
5676 case 2:
5677 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5678 break;
5679 case 3:
5680 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5681 break;
5682 default:
5683 DRM_DEBUG("invalid pipe %d\n", pipe);
5684 return;
5685 }
5686 } else {
5687 DRM_DEBUG("invalid me %d\n", me);
5688 return;
5689 }
5690
5691 switch (state) {
5692 case AMDGPU_IRQ_STATE_DISABLE:
5693 mec_int_cntl = RREG32(mec_int_cntl_reg);
5694 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5695 TIME_STAMP_INT_ENABLE, 0);
5696 WREG32(mec_int_cntl_reg, mec_int_cntl);
5697 break;
5698 case AMDGPU_IRQ_STATE_ENABLE:
5699 mec_int_cntl = RREG32(mec_int_cntl_reg);
5700 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5701 TIME_STAMP_INT_ENABLE, 1);
5702 WREG32(mec_int_cntl_reg, mec_int_cntl);
5703 break;
5704 default:
5705 break;
5706 }
5707 }
5708
gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)5709 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5710 struct amdgpu_irq_src *source,
5711 unsigned type,
5712 enum amdgpu_interrupt_state state)
5713 {
5714 switch (state) {
5715 case AMDGPU_IRQ_STATE_DISABLE:
5716 case AMDGPU_IRQ_STATE_ENABLE:
5717 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5718 PRIV_REG_INT_ENABLE,
5719 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5720 break;
5721 default:
5722 break;
5723 }
5724
5725 return 0;
5726 }
5727
gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)5728 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5729 struct amdgpu_irq_src *source,
5730 unsigned type,
5731 enum amdgpu_interrupt_state state)
5732 {
5733 switch (state) {
5734 case AMDGPU_IRQ_STATE_DISABLE:
5735 case AMDGPU_IRQ_STATE_ENABLE:
5736 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5737 PRIV_INSTR_INT_ENABLE,
5738 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5739 default:
5740 break;
5741 }
5742
5743 return 0;
5744 }
5745
5746 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \
5747 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5748 CP_ECC_ERROR_INT_ENABLE, 1)
5749
5750 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \
5751 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5752 CP_ECC_ERROR_INT_ENABLE, 0)
5753
gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)5754 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5755 struct amdgpu_irq_src *source,
5756 unsigned type,
5757 enum amdgpu_interrupt_state state)
5758 {
5759 switch (state) {
5760 case AMDGPU_IRQ_STATE_DISABLE:
5761 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5762 CP_ECC_ERROR_INT_ENABLE, 0);
5763 DISABLE_ECC_ON_ME_PIPE(1, 0);
5764 DISABLE_ECC_ON_ME_PIPE(1, 1);
5765 DISABLE_ECC_ON_ME_PIPE(1, 2);
5766 DISABLE_ECC_ON_ME_PIPE(1, 3);
5767 break;
5768
5769 case AMDGPU_IRQ_STATE_ENABLE:
5770 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5771 CP_ECC_ERROR_INT_ENABLE, 1);
5772 ENABLE_ECC_ON_ME_PIPE(1, 0);
5773 ENABLE_ECC_ON_ME_PIPE(1, 1);
5774 ENABLE_ECC_ON_ME_PIPE(1, 2);
5775 ENABLE_ECC_ON_ME_PIPE(1, 3);
5776 break;
5777 default:
5778 break;
5779 }
5780
5781 return 0;
5782 }
5783
5784
gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)5785 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5786 struct amdgpu_irq_src *src,
5787 unsigned type,
5788 enum amdgpu_interrupt_state state)
5789 {
5790 switch (type) {
5791 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5792 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
5793 break;
5794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5795 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5796 break;
5797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5798 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5799 break;
5800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5801 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5802 break;
5803 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5804 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5805 break;
5806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5807 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5808 break;
5809 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5810 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5811 break;
5812 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5813 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5814 break;
5815 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5816 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5817 break;
5818 default:
5819 break;
5820 }
5821 return 0;
5822 }
5823
gfx_v9_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5824 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
5825 struct amdgpu_irq_src *source,
5826 struct amdgpu_iv_entry *entry)
5827 {
5828 int i;
5829 u8 me_id, pipe_id, queue_id;
5830 struct amdgpu_ring *ring;
5831
5832 DRM_DEBUG("IH: CP EOP\n");
5833 me_id = (entry->ring_id & 0x0c) >> 2;
5834 pipe_id = (entry->ring_id & 0x03) >> 0;
5835 queue_id = (entry->ring_id & 0x70) >> 4;
5836
5837 switch (me_id) {
5838 case 0:
5839 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5840 break;
5841 case 1:
5842 case 2:
5843 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5844 ring = &adev->gfx.compute_ring[i];
5845 /* Per-queue interrupt is supported for MEC starting from VI.
5846 * The interrupt can only be enabled/disabled per pipe instead of per queue.
5847 */
5848 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
5849 amdgpu_fence_process(ring);
5850 }
5851 break;
5852 }
5853 return 0;
5854 }
5855
gfx_v9_0_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)5856 static void gfx_v9_0_fault(struct amdgpu_device *adev,
5857 struct amdgpu_iv_entry *entry)
5858 {
5859 u8 me_id, pipe_id, queue_id;
5860 struct amdgpu_ring *ring;
5861 int i;
5862
5863 me_id = (entry->ring_id & 0x0c) >> 2;
5864 pipe_id = (entry->ring_id & 0x03) >> 0;
5865 queue_id = (entry->ring_id & 0x70) >> 4;
5866
5867 switch (me_id) {
5868 case 0:
5869 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
5870 break;
5871 case 1:
5872 case 2:
5873 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5874 ring = &adev->gfx.compute_ring[i];
5875 if (ring->me == me_id && ring->pipe == pipe_id &&
5876 ring->queue == queue_id)
5877 drm_sched_fault(&ring->sched);
5878 }
5879 break;
5880 }
5881 }
5882
gfx_v9_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5883 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
5884 struct amdgpu_irq_src *source,
5885 struct amdgpu_iv_entry *entry)
5886 {
5887 DRM_ERROR("Illegal register access in command stream\n");
5888 gfx_v9_0_fault(adev, entry);
5889 return 0;
5890 }
5891
gfx_v9_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)5892 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
5893 struct amdgpu_irq_src *source,
5894 struct amdgpu_iv_entry *entry)
5895 {
5896 DRM_ERROR("Illegal instruction in command stream\n");
5897 gfx_v9_0_fault(adev, entry);
5898 return 0;
5899 }
5900
5901
5902 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = {
5903 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
5904 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
5905 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
5906 },
5907 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
5908 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
5909 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)
5910 },
5911 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5912 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1),
5913 0, 0
5914 },
5915 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5916 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2),
5917 0, 0
5918 },
5919 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
5920 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
5921 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)
5922 },
5923 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5924 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT),
5925 0, 0
5926 },
5927 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5928 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
5929 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)
5930 },
5931 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
5932 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT),
5933 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)
5934 },
5935 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
5936 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1),
5937 0, 0
5938 },
5939 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
5940 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1),
5941 0, 0
5942 },
5943 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
5944 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1),
5945 0, 0
5946 },
5947 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5948 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
5949 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)
5950 },
5951 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
5952 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED),
5953 0, 0
5954 },
5955 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5956 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
5957 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)
5958 },
5959 { "GDS_OA_PHY_PHY_CMD_RAM_MEM",
5960 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5961 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
5962 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)
5963 },
5964 { "GDS_OA_PHY_PHY_DATA_RAM_MEM",
5965 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
5966 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED),
5967 0, 0
5968 },
5969 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
5970 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5971 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
5972 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)
5973 },
5974 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
5975 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5976 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
5977 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)
5978 },
5979 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
5980 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5981 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
5982 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)
5983 },
5984 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
5985 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
5986 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
5987 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)
5988 },
5989 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
5990 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT),
5991 0, 0
5992 },
5993 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5994 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
5995 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)
5996 },
5997 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
5998 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT),
5999 0, 0
6000 },
6001 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6002 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT),
6003 0, 0
6004 },
6005 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6006 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT),
6007 0, 0
6008 },
6009 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6010 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT),
6011 0, 0
6012 },
6013 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
6014 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT),
6015 0, 0
6016 },
6017 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
6018 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT),
6019 0, 0
6020 },
6021 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6022 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
6023 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)
6024 },
6025 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6026 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
6027 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)
6028 },
6029 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6030 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
6031 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)
6032 },
6033 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6034 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
6035 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)
6036 },
6037 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6038 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
6039 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)
6040 },
6041 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6042 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT),
6043 0, 0
6044 },
6045 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6046 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT),
6047 0, 0
6048 },
6049 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6050 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT),
6051 0, 0
6052 },
6053 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6054 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT),
6055 0, 0
6056 },
6057 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6058 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT),
6059 0, 0
6060 },
6061 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6062 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT),
6063 0, 0
6064 },
6065 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6066 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT),
6067 0, 0
6068 },
6069 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6070 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT),
6071 0, 0
6072 },
6073 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6074 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT),
6075 0, 0
6076 },
6077 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6078 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
6079 0, 0
6080 },
6081 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6082 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT),
6083 0, 0
6084 },
6085 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6086 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
6087 0, 0
6088 },
6089 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6090 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT),
6091 0, 0
6092 },
6093 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
6094 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT),
6095 0, 0
6096 },
6097 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6098 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
6099 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)
6100 },
6101 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6102 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
6103 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)
6104 },
6105 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6106 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT),
6107 0, 0
6108 },
6109 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6110 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
6111 0, 0
6112 },
6113 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6114 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT),
6115 0, 0
6116 },
6117 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6118 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
6119 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)
6120 },
6121 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6122 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
6123 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)
6124 },
6125 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6126 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
6127 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)
6128 },
6129 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6130 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
6131 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)
6132 },
6133 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6134 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT),
6135 0, 0
6136 },
6137 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6138 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
6139 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)
6140 },
6141 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6142 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
6143 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)
6144 },
6145 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6146 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
6147 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)
6148 },
6149 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6150 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
6151 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)
6152 },
6153 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6154 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
6155 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)
6156 },
6157 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6158 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
6159 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)
6160 },
6161 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6162 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
6163 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)
6164 },
6165 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6166 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
6167 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)
6168 },
6169 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6170 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
6171 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)
6172 },
6173 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6174 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
6175 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)
6176 },
6177 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6178 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
6179 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)
6180 },
6181 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6182 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
6183 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)
6184 },
6185 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6186 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
6187 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)
6188 },
6189 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6190 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
6191 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)
6192 },
6193 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6194 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
6195 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)
6196 },
6197 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6198 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
6199 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)
6200 },
6201 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6202 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
6203 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)
6204 },
6205 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6206 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
6207 0, 0
6208 },
6209 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6210 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT),
6211 0, 0
6212 },
6213 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6214 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT),
6215 0, 0
6216 },
6217 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6218 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT),
6219 0, 0
6220 },
6221 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6222 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT),
6223 0, 0
6224 },
6225 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6226 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
6227 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)
6228 },
6229 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6230 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
6231 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)
6232 },
6233 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6234 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
6235 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)
6236 },
6237 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6238 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
6239 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)
6240 },
6241 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6242 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
6243 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)
6244 },
6245 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6246 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
6247 0, 0
6248 },
6249 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6250 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT),
6251 0, 0
6252 },
6253 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6254 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT),
6255 0, 0
6256 },
6257 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6258 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT),
6259 0, 0
6260 },
6261 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6262 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT),
6263 0, 0
6264 },
6265 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6266 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
6267 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)
6268 },
6269 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6270 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
6271 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)
6272 },
6273 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6274 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
6275 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)
6276 },
6277 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6278 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
6279 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)
6280 },
6281 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6282 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
6283 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)
6284 },
6285 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6286 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
6287 0, 0
6288 },
6289 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6290 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
6291 0, 0
6292 },
6293 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6294 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT),
6295 0, 0
6296 },
6297 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6298 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
6299 0, 0
6300 },
6301 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6302 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
6303 0, 0
6304 },
6305 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6306 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
6307 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)
6308 },
6309 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6310 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
6311 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)
6312 },
6313 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6314 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
6315 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)
6316 },
6317 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6318 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
6319 0, 0
6320 },
6321 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6322 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
6323 0, 0
6324 },
6325 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6326 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
6327 0, 0
6328 },
6329 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6330 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
6331 0, 0
6332 },
6333 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6334 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
6335 0, 0
6336 },
6337 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6338 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
6339 0, 0
6340 }
6341 };
6342
gfx_v9_0_ras_error_inject(struct amdgpu_device * adev,void * inject_if)6343 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
6344 void *inject_if)
6345 {
6346 struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
6347 int ret;
6348 struct ta_ras_trigger_error_input block_info = { 0 };
6349
6350 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6351 return -EINVAL;
6352
6353 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
6354 return -EINVAL;
6355
6356 if (!ras_gfx_subblocks[info->head.sub_block_index].name)
6357 return -EPERM;
6358
6359 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
6360 info->head.type)) {
6361 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
6362 ras_gfx_subblocks[info->head.sub_block_index].name,
6363 info->head.type);
6364 return -EPERM;
6365 }
6366
6367 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
6368 info->head.type)) {
6369 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
6370 ras_gfx_subblocks[info->head.sub_block_index].name,
6371 info->head.type);
6372 return -EPERM;
6373 }
6374
6375 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
6376 block_info.sub_block_index =
6377 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
6378 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
6379 block_info.address = info->address;
6380 block_info.value = info->value;
6381
6382 mutex_lock(&adev->grbm_idx_mutex);
6383 ret = psp_ras_trigger_error(&adev->psp, &block_info);
6384 mutex_unlock(&adev->grbm_idx_mutex);
6385
6386 return ret;
6387 }
6388
6389 static const char *vml2_mems[] = {
6390 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
6391 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
6392 "UTC_VML2_BANK_CACHE_0_4K_MEM0",
6393 "UTC_VML2_BANK_CACHE_0_4K_MEM1",
6394 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
6395 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
6396 "UTC_VML2_BANK_CACHE_1_4K_MEM0",
6397 "UTC_VML2_BANK_CACHE_1_4K_MEM1",
6398 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
6399 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
6400 "UTC_VML2_BANK_CACHE_2_4K_MEM0",
6401 "UTC_VML2_BANK_CACHE_2_4K_MEM1",
6402 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
6403 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
6404 "UTC_VML2_BANK_CACHE_3_4K_MEM0",
6405 "UTC_VML2_BANK_CACHE_3_4K_MEM1",
6406 };
6407
6408 static const char *vml2_walker_mems[] = {
6409 "UTC_VML2_CACHE_PDE0_MEM0",
6410 "UTC_VML2_CACHE_PDE0_MEM1",
6411 "UTC_VML2_CACHE_PDE1_MEM0",
6412 "UTC_VML2_CACHE_PDE1_MEM1",
6413 "UTC_VML2_CACHE_PDE2_MEM0",
6414 "UTC_VML2_CACHE_PDE2_MEM1",
6415 "UTC_VML2_RDIF_LOG_FIFO",
6416 };
6417
6418 static const char *atc_l2_cache_2m_mems[] = {
6419 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
6420 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
6421 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
6422 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
6423 };
6424
6425 static const char *atc_l2_cache_4k_mems[] = {
6426 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
6427 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
6428 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
6429 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
6430 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
6431 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
6432 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
6433 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
6434 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
6435 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
6436 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
6437 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
6438 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
6439 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
6440 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
6441 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
6442 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
6443 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
6444 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
6445 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
6446 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
6447 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
6448 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
6449 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
6450 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
6451 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
6452 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
6453 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
6454 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
6455 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
6456 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
6457 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
6458 };
6459
gfx_v9_0_query_utc_edc_status(struct amdgpu_device * adev,struct ras_err_data * err_data)6460 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
6461 struct ras_err_data *err_data)
6462 {
6463 uint32_t i, data;
6464 uint32_t sec_count, ded_count;
6465
6466 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6467 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6468 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6469 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6470 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6471 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6472 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6473 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6474
6475 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6476 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6477 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6478
6479 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
6480 if (sec_count) {
6481 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6482 "SEC %d\n", i, vml2_mems[i], sec_count);
6483 err_data->ce_count += sec_count;
6484 }
6485
6486 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
6487 if (ded_count) {
6488 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6489 "DED %d\n", i, vml2_mems[i], ded_count);
6490 err_data->ue_count += ded_count;
6491 }
6492 }
6493
6494 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6495 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6496 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6497
6498 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6499 SEC_COUNT);
6500 if (sec_count) {
6501 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6502 "SEC %d\n", i, vml2_walker_mems[i], sec_count);
6503 err_data->ce_count += sec_count;
6504 }
6505
6506 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6507 DED_COUNT);
6508 if (ded_count) {
6509 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6510 "DED %d\n", i, vml2_walker_mems[i], ded_count);
6511 err_data->ue_count += ded_count;
6512 }
6513 }
6514
6515 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6516 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6517 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6518
6519 sec_count = (data & 0x00006000L) >> 0xd;
6520 if (sec_count) {
6521 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6522 "SEC %d\n", i, atc_l2_cache_2m_mems[i],
6523 sec_count);
6524 err_data->ce_count += sec_count;
6525 }
6526 }
6527
6528 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6529 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6530 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6531
6532 sec_count = (data & 0x00006000L) >> 0xd;
6533 if (sec_count) {
6534 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6535 "SEC %d\n", i, atc_l2_cache_4k_mems[i],
6536 sec_count);
6537 err_data->ce_count += sec_count;
6538 }
6539
6540 ded_count = (data & 0x00018000L) >> 0xf;
6541 if (ded_count) {
6542 dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6543 "DED %d\n", i, atc_l2_cache_4k_mems[i],
6544 ded_count);
6545 err_data->ue_count += ded_count;
6546 }
6547 }
6548
6549 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6550 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6551 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6552 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6553
6554 return 0;
6555 }
6556
gfx_v9_0_ras_error_count(struct amdgpu_device * adev,const struct soc15_reg_entry * reg,uint32_t se_id,uint32_t inst_id,uint32_t value,uint32_t * sec_count,uint32_t * ded_count)6557 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev,
6558 const struct soc15_reg_entry *reg,
6559 uint32_t se_id, uint32_t inst_id, uint32_t value,
6560 uint32_t *sec_count, uint32_t *ded_count)
6561 {
6562 uint32_t i;
6563 uint32_t sec_cnt, ded_cnt;
6564
6565 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) {
6566 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
6567 gfx_v9_0_ras_fields[i].seg != reg->seg ||
6568 gfx_v9_0_ras_fields[i].inst != reg->inst)
6569 continue;
6570
6571 sec_cnt = (value &
6572 gfx_v9_0_ras_fields[i].sec_count_mask) >>
6573 gfx_v9_0_ras_fields[i].sec_count_shift;
6574 if (sec_cnt) {
6575 dev_info(adev->dev, "GFX SubBlock %s, "
6576 "Instance[%d][%d], SEC %d\n",
6577 gfx_v9_0_ras_fields[i].name,
6578 se_id, inst_id,
6579 sec_cnt);
6580 *sec_count += sec_cnt;
6581 }
6582
6583 ded_cnt = (value &
6584 gfx_v9_0_ras_fields[i].ded_count_mask) >>
6585 gfx_v9_0_ras_fields[i].ded_count_shift;
6586 if (ded_cnt) {
6587 dev_info(adev->dev, "GFX SubBlock %s, "
6588 "Instance[%d][%d], DED %d\n",
6589 gfx_v9_0_ras_fields[i].name,
6590 se_id, inst_id,
6591 ded_cnt);
6592 *ded_count += ded_cnt;
6593 }
6594 }
6595
6596 return 0;
6597 }
6598
gfx_v9_0_reset_ras_error_count(struct amdgpu_device * adev)6599 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev)
6600 {
6601 int i, j, k;
6602
6603 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6604 return;
6605
6606 /* read back registers to clear the counters */
6607 mutex_lock(&adev->grbm_idx_mutex);
6608 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6609 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6610 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6611 gfx_v9_0_select_se_sh(adev, j, 0x0, k);
6612 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6613 }
6614 }
6615 }
6616 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
6617 mutex_unlock(&adev->grbm_idx_mutex);
6618
6619 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6620 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6621 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6622 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6623 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6624 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6625 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6626 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6627
6628 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6629 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6630 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6631 }
6632
6633 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6634 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6635 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6636 }
6637
6638 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6639 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6640 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6641 }
6642
6643 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6644 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6645 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6646 }
6647
6648 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6649 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6650 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6651 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6652 }
6653
gfx_v9_0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)6654 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
6655 void *ras_error_status)
6656 {
6657 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
6658 uint32_t sec_count = 0, ded_count = 0;
6659 uint32_t i, j, k;
6660 uint32_t reg_value;
6661
6662 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6663 return -EINVAL;
6664
6665 err_data->ue_count = 0;
6666 err_data->ce_count = 0;
6667
6668 mutex_lock(&adev->grbm_idx_mutex);
6669
6670 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6671 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6672 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6673 gfx_v9_0_select_se_sh(adev, j, 0, k);
6674 reg_value =
6675 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6676 if (reg_value)
6677 gfx_v9_0_ras_error_count(adev,
6678 &gfx_v9_0_edc_counter_regs[i],
6679 j, k, reg_value,
6680 &sec_count, &ded_count);
6681 }
6682 }
6683 }
6684
6685 err_data->ce_count += sec_count;
6686 err_data->ue_count += ded_count;
6687
6688 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6689 mutex_unlock(&adev->grbm_idx_mutex);
6690
6691 gfx_v9_0_query_utc_edc_status(adev, err_data);
6692
6693 return 0;
6694 }
6695
gfx_v9_0_emit_mem_sync(struct amdgpu_ring * ring)6696 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
6697 {
6698 const unsigned int cp_coher_cntl =
6699 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
6700 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
6701 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
6702 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
6703 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
6704
6705 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
6706 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6707 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
6708 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6709 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
6710 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6711 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6712 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6713 }
6714
6715 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
6716 .name = "gfx_v9_0",
6717 .early_init = gfx_v9_0_early_init,
6718 .late_init = gfx_v9_0_late_init,
6719 .sw_init = gfx_v9_0_sw_init,
6720 .sw_fini = gfx_v9_0_sw_fini,
6721 .hw_init = gfx_v9_0_hw_init,
6722 .hw_fini = gfx_v9_0_hw_fini,
6723 .suspend = gfx_v9_0_suspend,
6724 .resume = gfx_v9_0_resume,
6725 .is_idle = gfx_v9_0_is_idle,
6726 .wait_for_idle = gfx_v9_0_wait_for_idle,
6727 .soft_reset = gfx_v9_0_soft_reset,
6728 .set_clockgating_state = gfx_v9_0_set_clockgating_state,
6729 .set_powergating_state = gfx_v9_0_set_powergating_state,
6730 .get_clockgating_state = gfx_v9_0_get_clockgating_state,
6731 };
6732
6733 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
6734 .type = AMDGPU_RING_TYPE_GFX,
6735 .align_mask = 0xff,
6736 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6737 .support_64bit_ptrs = true,
6738 .vmhub = AMDGPU_GFXHUB_0,
6739 .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
6740 .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
6741 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
6742 .emit_frame_size = /* totally 242 maximum if 16 IBs */
6743 5 + /* COND_EXEC */
6744 7 + /* PIPELINE_SYNC */
6745 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6746 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6747 2 + /* VM_FLUSH */
6748 8 + /* FENCE for VM_FLUSH */
6749 20 + /* GDS switch */
6750 4 + /* double SWITCH_BUFFER,
6751 the first COND_EXEC jump to the place just
6752 prior to this double SWITCH_BUFFER */
6753 5 + /* COND_EXEC */
6754 7 + /* HDP_flush */
6755 4 + /* VGT_flush */
6756 14 + /* CE_META */
6757 31 + /* DE_META */
6758 3 + /* CNTX_CTRL */
6759 5 + /* HDP_INVL */
6760 8 + 8 + /* FENCE x2 */
6761 2 + /* SWITCH_BUFFER */
6762 7, /* gfx_v9_0_emit_mem_sync */
6763 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
6764 .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
6765 .emit_fence = gfx_v9_0_ring_emit_fence,
6766 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6767 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6768 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6769 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6770 .test_ring = gfx_v9_0_ring_test_ring,
6771 .test_ib = gfx_v9_0_ring_test_ib,
6772 .insert_nop = amdgpu_ring_insert_nop,
6773 .pad_ib = amdgpu_ring_generic_pad_ib,
6774 .emit_switch_buffer = gfx_v9_ring_emit_sb,
6775 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
6776 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
6777 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
6778 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
6779 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6780 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6781 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6782 .soft_recovery = gfx_v9_0_ring_soft_recovery,
6783 .emit_mem_sync = gfx_v9_0_emit_mem_sync,
6784 };
6785
6786 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
6787 .type = AMDGPU_RING_TYPE_COMPUTE,
6788 .align_mask = 0xff,
6789 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6790 .support_64bit_ptrs = true,
6791 .vmhub = AMDGPU_GFXHUB_0,
6792 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6793 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6794 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6795 .emit_frame_size =
6796 20 + /* gfx_v9_0_ring_emit_gds_switch */
6797 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6798 5 + /* hdp invalidate */
6799 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6800 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6801 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6802 2 + /* gfx_v9_0_ring_emit_vm_flush */
6803 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6804 7, /* gfx_v9_0_emit_mem_sync */
6805 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6806 .emit_ib = gfx_v9_0_ring_emit_ib_compute,
6807 .emit_fence = gfx_v9_0_ring_emit_fence,
6808 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6809 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6810 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6811 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6812 .test_ring = gfx_v9_0_ring_test_ring,
6813 .test_ib = gfx_v9_0_ring_test_ib,
6814 .insert_nop = amdgpu_ring_insert_nop,
6815 .pad_ib = amdgpu_ring_generic_pad_ib,
6816 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6817 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6818 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6819 .emit_mem_sync = gfx_v9_0_emit_mem_sync,
6820 };
6821
6822 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
6823 .type = AMDGPU_RING_TYPE_KIQ,
6824 .align_mask = 0xff,
6825 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6826 .support_64bit_ptrs = true,
6827 .vmhub = AMDGPU_GFXHUB_0,
6828 .get_rptr = gfx_v9_0_ring_get_rptr_compute,
6829 .get_wptr = gfx_v9_0_ring_get_wptr_compute,
6830 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
6831 .emit_frame_size =
6832 20 + /* gfx_v9_0_ring_emit_gds_switch */
6833 7 + /* gfx_v9_0_ring_emit_hdp_flush */
6834 5 + /* hdp invalidate */
6835 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6836 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6837 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6838 2 + /* gfx_v9_0_ring_emit_vm_flush */
6839 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6840 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
6841 .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
6842 .test_ring = gfx_v9_0_ring_test_ring,
6843 .insert_nop = amdgpu_ring_insert_nop,
6844 .pad_ib = amdgpu_ring_generic_pad_ib,
6845 .emit_rreg = gfx_v9_0_ring_emit_rreg,
6846 .emit_wreg = gfx_v9_0_ring_emit_wreg,
6847 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6848 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6849 };
6850
gfx_v9_0_set_ring_funcs(struct amdgpu_device * adev)6851 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
6852 {
6853 int i;
6854
6855 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
6856
6857 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6858 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
6859
6860 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6861 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
6862 }
6863
6864 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
6865 .set = gfx_v9_0_set_eop_interrupt_state,
6866 .process = gfx_v9_0_eop_irq,
6867 };
6868
6869 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
6870 .set = gfx_v9_0_set_priv_reg_fault_state,
6871 .process = gfx_v9_0_priv_reg_irq,
6872 };
6873
6874 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
6875 .set = gfx_v9_0_set_priv_inst_fault_state,
6876 .process = gfx_v9_0_priv_inst_irq,
6877 };
6878
6879 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
6880 .set = gfx_v9_0_set_cp_ecc_error_state,
6881 .process = amdgpu_gfx_cp_ecc_error_irq,
6882 };
6883
6884
gfx_v9_0_set_irq_funcs(struct amdgpu_device * adev)6885 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
6886 {
6887 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6888 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
6889
6890 adev->gfx.priv_reg_irq.num_types = 1;
6891 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
6892
6893 adev->gfx.priv_inst_irq.num_types = 1;
6894 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
6895
6896 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
6897 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
6898 }
6899
gfx_v9_0_set_rlc_funcs(struct amdgpu_device * adev)6900 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
6901 {
6902 switch (adev->asic_type) {
6903 case CHIP_VEGA10:
6904 case CHIP_VEGA12:
6905 case CHIP_VEGA20:
6906 case CHIP_RAVEN:
6907 case CHIP_ARCTURUS:
6908 case CHIP_RENOIR:
6909 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
6910 break;
6911 default:
6912 break;
6913 }
6914 }
6915
gfx_v9_0_set_gds_init(struct amdgpu_device * adev)6916 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
6917 {
6918 /* init asci gds info */
6919 switch (adev->asic_type) {
6920 case CHIP_VEGA10:
6921 case CHIP_VEGA12:
6922 case CHIP_VEGA20:
6923 adev->gds.gds_size = 0x10000;
6924 break;
6925 case CHIP_RAVEN:
6926 case CHIP_ARCTURUS:
6927 adev->gds.gds_size = 0x1000;
6928 break;
6929 default:
6930 adev->gds.gds_size = 0x10000;
6931 break;
6932 }
6933
6934 switch (adev->asic_type) {
6935 case CHIP_VEGA10:
6936 case CHIP_VEGA20:
6937 adev->gds.gds_compute_max_wave_id = 0x7ff;
6938 break;
6939 case CHIP_VEGA12:
6940 adev->gds.gds_compute_max_wave_id = 0x27f;
6941 break;
6942 case CHIP_RAVEN:
6943 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
6944 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
6945 else
6946 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
6947 break;
6948 case CHIP_ARCTURUS:
6949 adev->gds.gds_compute_max_wave_id = 0xfff;
6950 break;
6951 default:
6952 /* this really depends on the chip */
6953 adev->gds.gds_compute_max_wave_id = 0x7ff;
6954 break;
6955 }
6956
6957 adev->gds.gws_size = 64;
6958 adev->gds.oa_size = 16;
6959 }
6960
gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)6961 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
6962 u32 bitmap)
6963 {
6964 u32 data;
6965
6966 if (!bitmap)
6967 return;
6968
6969 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6970 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6971
6972 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
6973 }
6974
gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device * adev)6975 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
6976 {
6977 u32 data, mask;
6978
6979 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
6980 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
6981
6982 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
6983 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
6984
6985 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
6986
6987 return (~data) & mask;
6988 }
6989
gfx_v9_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)6990 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
6991 struct amdgpu_cu_info *cu_info)
6992 {
6993 int i, j, k, counter, active_cu_number = 0;
6994 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
6995 unsigned disable_masks[4 * 4];
6996
6997 if (!adev || !cu_info)
6998 return -EINVAL;
6999
7000 /*
7001 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
7002 */
7003 if (adev->gfx.config.max_shader_engines *
7004 adev->gfx.config.max_sh_per_se > 16)
7005 return -EINVAL;
7006
7007 amdgpu_gfx_parse_disable_cu(disable_masks,
7008 adev->gfx.config.max_shader_engines,
7009 adev->gfx.config.max_sh_per_se);
7010
7011 mutex_lock(&adev->grbm_idx_mutex);
7012 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7013 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7014 mask = 1;
7015 ao_bitmap = 0;
7016 counter = 0;
7017 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
7018 gfx_v9_0_set_user_cu_inactive_bitmap(
7019 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
7020 bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
7021
7022 /*
7023 * The bitmap(and ao_cu_bitmap) in cu_info structure is
7024 * 4x4 size array, and it's usually suitable for Vega
7025 * ASICs which has 4*2 SE/SH layout.
7026 * But for Arcturus, SE/SH layout is changed to 8*1.
7027 * To mostly reduce the impact, we make it compatible
7028 * with current bitmap array as below:
7029 * SE4,SH0 --> bitmap[0][1]
7030 * SE5,SH0 --> bitmap[1][1]
7031 * SE6,SH0 --> bitmap[2][1]
7032 * SE7,SH0 --> bitmap[3][1]
7033 */
7034 cu_info->bitmap[i % 4][j + i / 4] = bitmap;
7035
7036 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7037 if (bitmap & mask) {
7038 if (counter < adev->gfx.config.max_cu_per_sh)
7039 ao_bitmap |= mask;
7040 counter ++;
7041 }
7042 mask <<= 1;
7043 }
7044 active_cu_number += counter;
7045 if (i < 2 && j < 2)
7046 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7047 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
7048 }
7049 }
7050 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7051 mutex_unlock(&adev->grbm_idx_mutex);
7052
7053 cu_info->number = active_cu_number;
7054 cu_info->ao_cu_mask = ao_cu_mask;
7055 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7056
7057 return 0;
7058 }
7059
7060 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
7061 {
7062 .type = AMD_IP_BLOCK_TYPE_GFX,
7063 .major = 9,
7064 .minor = 0,
7065 .rev = 0,
7066 .funcs = &gfx_v9_0_ip_funcs,
7067 };
7068