1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/i2c.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/of_graph.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_dp_helper.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_print.h>
28 #include <drm/drm_probe_helper.h>
29
30 #define SN_DEVICE_REV_REG 0x08
31 #define SN_DPPLL_SRC_REG 0x0A
32 #define DPPLL_CLK_SRC_DSICLK BIT(0)
33 #define REFCLK_FREQ_MASK GENMASK(3, 1)
34 #define REFCLK_FREQ(x) ((x) << 1)
35 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
36 #define SN_PLL_ENABLE_REG 0x0D
37 #define SN_DSI_LANES_REG 0x10
38 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
39 #define CHA_DSI_LANES(x) ((x) << 3)
40 #define SN_DSIA_CLK_FREQ_REG 0x12
41 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
42 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
43 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
44 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
45 #define CHA_HSYNC_POLARITY BIT(7)
46 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
47 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
48 #define CHA_VSYNC_POLARITY BIT(7)
49 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
50 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
51 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
52 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
53 #define SN_LN_ASSIGN_REG 0x59
54 #define LN_ASSIGN_WIDTH 2
55 #define SN_ENH_FRAME_REG 0x5A
56 #define VSTREAM_ENABLE BIT(3)
57 #define LN_POLRS_OFFSET 4
58 #define LN_POLRS_MASK 0xf0
59 #define SN_DATA_FORMAT_REG 0x5B
60 #define BPP_18_RGB BIT(0)
61 #define SN_HPD_DISABLE_REG 0x5C
62 #define HPD_DISABLE BIT(0)
63 #define SN_GPIO_IO_REG 0x5E
64 #define SN_GPIO_INPUT_SHIFT 4
65 #define SN_GPIO_OUTPUT_SHIFT 0
66 #define SN_GPIO_CTRL_REG 0x5F
67 #define SN_GPIO_MUX_INPUT 0
68 #define SN_GPIO_MUX_OUTPUT 1
69 #define SN_GPIO_MUX_SPECIAL 2
70 #define SN_GPIO_MUX_MASK 0x3
71 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
72 #define SN_AUX_ADDR_19_16_REG 0x74
73 #define SN_AUX_ADDR_15_8_REG 0x75
74 #define SN_AUX_ADDR_7_0_REG 0x76
75 #define SN_AUX_LENGTH_REG 0x77
76 #define SN_AUX_CMD_REG 0x78
77 #define AUX_CMD_SEND BIT(0)
78 #define AUX_CMD_REQ(x) ((x) << 4)
79 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
80 #define SN_SSC_CONFIG_REG 0x93
81 #define DP_NUM_LANES_MASK GENMASK(5, 4)
82 #define DP_NUM_LANES(x) ((x) << 4)
83 #define SN_DATARATE_CONFIG_REG 0x94
84 #define DP_DATARATE_MASK GENMASK(7, 5)
85 #define DP_DATARATE(x) ((x) << 5)
86 #define SN_ML_TX_MODE_REG 0x96
87 #define ML_TX_MAIN_LINK_OFF 0
88 #define ML_TX_NORMAL_MODE BIT(0)
89 #define SN_AUX_CMD_STATUS_REG 0xF4
90 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
91 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
92 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
93
94 #define MIN_DSI_CLK_FREQ_MHZ 40
95
96 /* fudge factor required to account for 8b/10b encoding */
97 #define DP_CLK_FUDGE_NUM 10
98 #define DP_CLK_FUDGE_DEN 8
99
100 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
101 #define SN_AUX_MAX_PAYLOAD_BYTES 16
102
103 #define SN_REGULATOR_SUPPLY_NUM 4
104
105 #define SN_MAX_DP_LANES 4
106 #define SN_NUM_GPIOS 4
107 #define SN_GPIO_PHYSICAL_OFFSET 1
108
109 /**
110 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
111 * @dev: Pointer to our device.
112 * @regmap: Regmap for accessing i2c.
113 * @aux: Our aux channel.
114 * @bridge: Our bridge.
115 * @connector: Our connector.
116 * @debugfs: Used for managing our debugfs.
117 * @host_node: Remote DSI node.
118 * @dsi: Our MIPI DSI source.
119 * @refclk: Our reference clock.
120 * @panel: Our panel.
121 * @enable_gpio: The GPIO we toggle to enable the bridge.
122 * @supplies: Data for bulk enabling/disabling our regulators.
123 * @dp_lanes: Count of dp_lanes we're using.
124 * @ln_assign: Value to program to the LN_ASSIGN register.
125 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
126 *
127 * @gchip: If we expose our GPIOs, this is used.
128 * @gchip_output: A cache of whether we've set GPIOs to output. This
129 * serves double-duty of keeping track of the direction and
130 * also keeping track of whether we've incremented the
131 * pm_runtime reference count for this pin, which we do
132 * whenever a pin is configured as an output. This is a
133 * bitmap so we can do atomic ops on it without an extra
134 * lock so concurrent users of our 4 GPIOs don't stomp on
135 * each other's read-modify-write.
136 */
137 struct ti_sn_bridge {
138 struct device *dev;
139 struct regmap *regmap;
140 struct drm_dp_aux aux;
141 struct drm_bridge bridge;
142 struct drm_connector connector;
143 struct dentry *debugfs;
144 struct device_node *host_node;
145 struct mipi_dsi_device *dsi;
146 struct clk *refclk;
147 struct drm_panel *panel;
148 struct gpio_desc *enable_gpio;
149 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
150 int dp_lanes;
151 u8 ln_assign;
152 u8 ln_polrs;
153
154 #if defined(CONFIG_OF_GPIO)
155 struct gpio_chip gchip;
156 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
157 #endif
158 };
159
160 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
161 { .range_min = 0, .range_max = 0xFF },
162 };
163
164 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
165 .yes_ranges = ti_sn_bridge_volatile_ranges,
166 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
167 };
168
169 static const struct regmap_config ti_sn_bridge_regmap_config = {
170 .reg_bits = 8,
171 .val_bits = 8,
172 .volatile_table = &ti_sn_bridge_volatile_table,
173 .cache_type = REGCACHE_NONE,
174 .max_register = 0xFF,
175 };
176
ti_sn_bridge_write_u16(struct ti_sn_bridge * pdata,unsigned int reg,u16 val)177 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
178 unsigned int reg, u16 val)
179 {
180 regmap_write(pdata->regmap, reg, val & 0xFF);
181 regmap_write(pdata->regmap, reg + 1, val >> 8);
182 }
183
ti_sn_bridge_resume(struct device * dev)184 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
185 {
186 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
187 int ret;
188
189 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
190 if (ret) {
191 DRM_ERROR("failed to enable supplies %d\n", ret);
192 return ret;
193 }
194
195 gpiod_set_value(pdata->enable_gpio, 1);
196
197 return ret;
198 }
199
ti_sn_bridge_suspend(struct device * dev)200 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
201 {
202 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
203 int ret;
204
205 gpiod_set_value(pdata->enable_gpio, 0);
206
207 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
208 if (ret)
209 DRM_ERROR("failed to disable supplies %d\n", ret);
210
211 return ret;
212 }
213
214 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
215 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
216 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
217 pm_runtime_force_resume)
218 };
219
status_show(struct seq_file * s,void * data)220 static int status_show(struct seq_file *s, void *data)
221 {
222 struct ti_sn_bridge *pdata = s->private;
223 unsigned int reg, val;
224
225 seq_puts(s, "STATUS REGISTERS:\n");
226
227 pm_runtime_get_sync(pdata->dev);
228
229 /* IRQ Status Registers, see Table 31 in datasheet */
230 for (reg = 0xf0; reg <= 0xf8; reg++) {
231 regmap_read(pdata->regmap, reg, &val);
232 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
233 }
234
235 pm_runtime_put(pdata->dev);
236
237 return 0;
238 }
239
240 DEFINE_SHOW_ATTRIBUTE(status);
241
ti_sn_debugfs_init(struct ti_sn_bridge * pdata)242 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
243 {
244 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
245
246 debugfs_create_file("status", 0600, pdata->debugfs, pdata,
247 &status_fops);
248 }
249
ti_sn_debugfs_remove(struct ti_sn_bridge * pdata)250 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
251 {
252 debugfs_remove_recursive(pdata->debugfs);
253 pdata->debugfs = NULL;
254 }
255
256 /* Connector funcs */
257 static struct ti_sn_bridge *
connector_to_ti_sn_bridge(struct drm_connector * connector)258 connector_to_ti_sn_bridge(struct drm_connector *connector)
259 {
260 return container_of(connector, struct ti_sn_bridge, connector);
261 }
262
ti_sn_bridge_connector_get_modes(struct drm_connector * connector)263 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
264 {
265 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
266
267 return drm_panel_get_modes(pdata->panel, connector);
268 }
269
270 static enum drm_mode_status
ti_sn_bridge_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)271 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
272 struct drm_display_mode *mode)
273 {
274 /* maximum supported resolution is 4K at 60 fps */
275 if (mode->clock > 594000)
276 return MODE_CLOCK_HIGH;
277
278 return MODE_OK;
279 }
280
281 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
282 .get_modes = ti_sn_bridge_connector_get_modes,
283 .mode_valid = ti_sn_bridge_connector_mode_valid,
284 };
285
286 static enum drm_connector_status
ti_sn_bridge_connector_detect(struct drm_connector * connector,bool force)287 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
288 {
289 /**
290 * TODO: Currently if drm_panel is present, then always
291 * return the status as connected. Need to add support to detect
292 * device state for hot pluggable scenarios.
293 */
294 return connector_status_connected;
295 }
296
297 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
298 .fill_modes = drm_helper_probe_single_connector_modes,
299 .detect = ti_sn_bridge_connector_detect,
300 .destroy = drm_connector_cleanup,
301 .reset = drm_atomic_helper_connector_reset,
302 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
303 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
304 };
305
bridge_to_ti_sn_bridge(struct drm_bridge * bridge)306 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
307 {
308 return container_of(bridge, struct ti_sn_bridge, bridge);
309 }
310
ti_sn_bridge_parse_regulators(struct ti_sn_bridge * pdata)311 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
312 {
313 unsigned int i;
314 const char * const ti_sn_bridge_supply_names[] = {
315 "vcca", "vcc", "vccio", "vpll",
316 };
317
318 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
319 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
320
321 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
322 pdata->supplies);
323 }
324
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)325 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
326 enum drm_bridge_attach_flags flags)
327 {
328 int ret, val;
329 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
330 struct mipi_dsi_host *host;
331 struct mipi_dsi_device *dsi;
332 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
333 .channel = 0,
334 .node = NULL,
335 };
336
337 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
338 DRM_ERROR("Fix bridge driver to make connector optional!");
339 return -EINVAL;
340 }
341
342 ret = drm_connector_init(bridge->dev, &pdata->connector,
343 &ti_sn_bridge_connector_funcs,
344 DRM_MODE_CONNECTOR_eDP);
345 if (ret) {
346 DRM_ERROR("Failed to initialize connector with drm\n");
347 return ret;
348 }
349
350 drm_connector_helper_add(&pdata->connector,
351 &ti_sn_bridge_connector_helper_funcs);
352 drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
353
354 /*
355 * TODO: ideally finding host resource and dsi dev registration needs
356 * to be done in bridge probe. But some existing DSI host drivers will
357 * wait for any of the drm_bridge/drm_panel to get added to the global
358 * bridge/panel list, before completing their probe. So if we do the
359 * dsi dev registration part in bridge probe, before populating in
360 * the global bridge list, then it will cause deadlock as dsi host probe
361 * will never complete, neither our bridge probe. So keeping it here
362 * will satisfy most of the existing host drivers. Once the host driver
363 * is fixed we can move the below code to bridge probe safely.
364 */
365 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
366 if (!host) {
367 DRM_ERROR("failed to find dsi host\n");
368 ret = -ENODEV;
369 goto err_dsi_host;
370 }
371
372 dsi = mipi_dsi_device_register_full(host, &info);
373 if (IS_ERR(dsi)) {
374 DRM_ERROR("failed to create dsi device\n");
375 ret = PTR_ERR(dsi);
376 goto err_dsi_host;
377 }
378
379 /* TODO: setting to 4 MIPI lanes always for now */
380 dsi->lanes = 4;
381 dsi->format = MIPI_DSI_FMT_RGB888;
382 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
383
384 /* check if continuous dsi clock is required or not */
385 pm_runtime_get_sync(pdata->dev);
386 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
387 pm_runtime_put(pdata->dev);
388 if (!(val & DPPLL_CLK_SRC_DSICLK))
389 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
390
391 ret = mipi_dsi_attach(dsi);
392 if (ret < 0) {
393 DRM_ERROR("failed to attach dsi to host\n");
394 goto err_dsi_attach;
395 }
396 pdata->dsi = dsi;
397
398 return 0;
399
400 err_dsi_attach:
401 mipi_dsi_device_unregister(dsi);
402 err_dsi_host:
403 drm_connector_cleanup(&pdata->connector);
404 return ret;
405 }
406
ti_sn_bridge_disable(struct drm_bridge * bridge)407 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
408 {
409 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
410
411 drm_panel_disable(pdata->panel);
412
413 /* disable video stream */
414 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
415 /* semi auto link training mode OFF */
416 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
417 /* disable DP PLL */
418 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
419
420 drm_panel_unprepare(pdata->panel);
421 }
422
ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge * pdata)423 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
424 {
425 u32 bit_rate_khz, clk_freq_khz;
426 struct drm_display_mode *mode =
427 &pdata->bridge.encoder->crtc->state->adjusted_mode;
428
429 bit_rate_khz = mode->clock *
430 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
431 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
432
433 return clk_freq_khz;
434 }
435
436 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
437 static const u32 ti_sn_bridge_refclk_lut[] = {
438 12000000,
439 19200000,
440 26000000,
441 27000000,
442 38400000,
443 };
444
445 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
446 static const u32 ti_sn_bridge_dsiclk_lut[] = {
447 468000000,
448 384000000,
449 416000000,
450 486000000,
451 460800000,
452 };
453
ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge * pdata)454 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
455 {
456 int i;
457 u32 refclk_rate;
458 const u32 *refclk_lut;
459 size_t refclk_lut_size;
460
461 if (pdata->refclk) {
462 refclk_rate = clk_get_rate(pdata->refclk);
463 refclk_lut = ti_sn_bridge_refclk_lut;
464 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
465 clk_prepare_enable(pdata->refclk);
466 } else {
467 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
468 refclk_lut = ti_sn_bridge_dsiclk_lut;
469 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
470 }
471
472 /* for i equals to refclk_lut_size means default frequency */
473 for (i = 0; i < refclk_lut_size; i++)
474 if (refclk_lut[i] == refclk_rate)
475 break;
476
477 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
478 REFCLK_FREQ(i));
479 }
480
ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge * pdata)481 static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
482 {
483 unsigned int bit_rate_mhz, clk_freq_mhz;
484 unsigned int val;
485 struct drm_display_mode *mode =
486 &pdata->bridge.encoder->crtc->state->adjusted_mode;
487
488 /* set DSIA clk frequency */
489 bit_rate_mhz = (mode->clock / 1000) *
490 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
491 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
492
493 /* for each increment in val, frequency increases by 5MHz */
494 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
495 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
496 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
497 }
498
ti_sn_bridge_get_bpp(struct ti_sn_bridge * pdata)499 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
500 {
501 if (pdata->connector.display_info.bpc <= 6)
502 return 18;
503 else
504 return 24;
505 }
506
507 /*
508 * LUT index corresponds to register value and
509 * LUT values corresponds to dp data rate supported
510 * by the bridge in Mbps unit.
511 */
512 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
513 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
514 };
515
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge * pdata)516 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata)
517 {
518 unsigned int bit_rate_khz, dp_rate_mhz;
519 unsigned int i;
520 struct drm_display_mode *mode =
521 &pdata->bridge.encoder->crtc->state->adjusted_mode;
522
523 /* Calculate minimum bit rate based on our pixel clock. */
524 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
525
526 /* Calculate minimum DP data rate, taking 80% as per DP spec */
527 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
528 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
529
530 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
531 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
532 break;
533
534 return i;
535 }
536
ti_sn_bridge_read_valid_rates(struct ti_sn_bridge * pdata,bool rate_valid[])537 static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata,
538 bool rate_valid[])
539 {
540 unsigned int rate_per_200khz;
541 unsigned int rate_mhz;
542 u8 dpcd_val;
543 int ret;
544 int i, j;
545
546 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
547 if (ret != 1) {
548 DRM_DEV_ERROR(pdata->dev,
549 "Can't read eDP rev (%d), assuming 1.1\n", ret);
550 dpcd_val = DP_EDP_11;
551 }
552
553 if (dpcd_val >= DP_EDP_14) {
554 /* eDP 1.4 devices must provide a custom table */
555 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
556
557 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
558 sink_rates, sizeof(sink_rates));
559
560 if (ret != sizeof(sink_rates)) {
561 DRM_DEV_ERROR(pdata->dev,
562 "Can't read supported rate table (%d)\n", ret);
563
564 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
565 memset(sink_rates, 0, sizeof(sink_rates));
566 }
567
568 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
569 rate_per_200khz = le16_to_cpu(sink_rates[i]);
570
571 if (!rate_per_200khz)
572 break;
573
574 rate_mhz = rate_per_200khz * 200 / 1000;
575 for (j = 0;
576 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
577 j++) {
578 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
579 rate_valid[j] = true;
580 }
581 }
582
583 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
584 if (rate_valid[i])
585 return;
586 }
587 DRM_DEV_ERROR(pdata->dev,
588 "No matching eDP rates in table; falling back\n");
589 }
590
591 /* On older versions best we can do is use DP_MAX_LINK_RATE */
592 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
593 if (ret != 1) {
594 DRM_DEV_ERROR(pdata->dev,
595 "Can't read max rate (%d); assuming 5.4 GHz\n",
596 ret);
597 dpcd_val = DP_LINK_BW_5_4;
598 }
599
600 switch (dpcd_val) {
601 default:
602 DRM_DEV_ERROR(pdata->dev,
603 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
604 (int)dpcd_val);
605 fallthrough;
606 case DP_LINK_BW_5_4:
607 rate_valid[7] = 1;
608 fallthrough;
609 case DP_LINK_BW_2_7:
610 rate_valid[4] = 1;
611 fallthrough;
612 case DP_LINK_BW_1_62:
613 rate_valid[1] = 1;
614 break;
615 }
616 }
617
ti_sn_bridge_set_video_timings(struct ti_sn_bridge * pdata)618 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
619 {
620 struct drm_display_mode *mode =
621 &pdata->bridge.encoder->crtc->state->adjusted_mode;
622 u8 hsync_polarity = 0, vsync_polarity = 0;
623
624 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
625 hsync_polarity = CHA_HSYNC_POLARITY;
626 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
627 vsync_polarity = CHA_VSYNC_POLARITY;
628
629 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
630 mode->hdisplay);
631 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
632 mode->vdisplay);
633 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
634 (mode->hsync_end - mode->hsync_start) & 0xFF);
635 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
636 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
637 hsync_polarity);
638 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
639 (mode->vsync_end - mode->vsync_start) & 0xFF);
640 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
641 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
642 vsync_polarity);
643
644 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
645 (mode->htotal - mode->hsync_end) & 0xFF);
646 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
647 (mode->vtotal - mode->vsync_end) & 0xFF);
648
649 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
650 (mode->hsync_start - mode->hdisplay) & 0xFF);
651 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
652 (mode->vsync_start - mode->vdisplay) & 0xFF);
653
654 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
655 }
656
ti_sn_get_max_lanes(struct ti_sn_bridge * pdata)657 static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
658 {
659 u8 data;
660 int ret;
661
662 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
663 if (ret != 1) {
664 DRM_DEV_ERROR(pdata->dev,
665 "Can't read lane count (%d); assuming 4\n", ret);
666 return 4;
667 }
668
669 return data & DP_LANE_COUNT_MASK;
670 }
671
ti_sn_link_training(struct ti_sn_bridge * pdata,int dp_rate_idx,const char ** last_err_str)672 static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
673 const char **last_err_str)
674 {
675 unsigned int val;
676 int ret;
677
678 /* set dp clk frequency value */
679 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
680 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
681
682 /* enable DP PLL */
683 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
684
685 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
686 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
687 50 * 1000);
688 if (ret) {
689 *last_err_str = "DP_PLL_LOCK polling failed";
690 goto exit;
691 }
692
693 /* Semi auto link training mode */
694 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
695 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
696 val == ML_TX_MAIN_LINK_OFF ||
697 val == ML_TX_NORMAL_MODE, 1000,
698 500 * 1000);
699 if (ret) {
700 *last_err_str = "Training complete polling failed";
701 } else if (val == ML_TX_MAIN_LINK_OFF) {
702 *last_err_str = "Link training failed, link is off";
703 ret = -EIO;
704 }
705
706 exit:
707 /* Disable the PLL if we failed */
708 if (ret)
709 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
710
711 return ret;
712 }
713
ti_sn_bridge_enable(struct drm_bridge * bridge)714 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
715 {
716 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
717 bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { };
718 const char *last_err_str = "No supported DP rate";
719 int dp_rate_idx;
720 unsigned int val;
721 int ret = -EINVAL;
722 int max_dp_lanes;
723
724 max_dp_lanes = ti_sn_get_max_lanes(pdata);
725 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
726
727 /* DSI_A lane config */
728 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
729 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
730 CHA_DSI_LANES_MASK, val);
731
732 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
733 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
734 pdata->ln_polrs << LN_POLRS_OFFSET);
735
736 /* set dsi clk frequency value */
737 ti_sn_bridge_set_dsi_rate(pdata);
738
739 /**
740 * The SN65DSI86 only supports ASSR Display Authentication method and
741 * this method is enabled by default. An eDP panel must support this
742 * authentication method. We need to enable this method in the eDP panel
743 * at DisplayPort address 0x0010A prior to link training.
744 */
745 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
746 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
747
748 /* Set the DP output format (18 bpp or 24 bpp) */
749 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
750 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
751
752 /* DP lane config */
753 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
754 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
755 val);
756
757 ti_sn_bridge_read_valid_rates(pdata, rate_valid);
758
759 /* Train until we run out of rates */
760 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
761 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
762 dp_rate_idx++) {
763 if (!rate_valid[dp_rate_idx])
764 continue;
765
766 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
767 if (!ret)
768 break;
769 }
770 if (ret) {
771 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
772 return;
773 }
774
775 /* config video parameters */
776 ti_sn_bridge_set_video_timings(pdata);
777
778 /* enable video stream */
779 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
780 VSTREAM_ENABLE);
781
782 drm_panel_enable(pdata->panel);
783 }
784
ti_sn_bridge_pre_enable(struct drm_bridge * bridge)785 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
786 {
787 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
788
789 pm_runtime_get_sync(pdata->dev);
790
791 /* configure bridge ref_clk */
792 ti_sn_bridge_set_refclk_freq(pdata);
793
794 /*
795 * HPD on this bridge chip is a bit useless. This is an eDP bridge
796 * so the HPD is an internal signal that's only there to signal that
797 * the panel is done powering up. ...but the bridge chip debounces
798 * this signal by between 100 ms and 400 ms (depending on process,
799 * voltage, and temperate--I measured it at about 200 ms). One
800 * particular panel asserted HPD 84 ms after it was powered on meaning
801 * that we saw HPD 284 ms after power on. ...but the same panel said
802 * that instead of looking at HPD you could just hardcode a delay of
803 * 200 ms. We'll assume that the panel driver will have the hardcoded
804 * delay in its prepare and always disable HPD.
805 *
806 * If HPD somehow makes sense on some future panel we'll have to
807 * change this to be conditional on someone specifying that HPD should
808 * be used.
809 */
810 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
811 HPD_DISABLE);
812
813 drm_panel_prepare(pdata->panel);
814 }
815
ti_sn_bridge_post_disable(struct drm_bridge * bridge)816 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
817 {
818 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
819
820 if (pdata->refclk)
821 clk_disable_unprepare(pdata->refclk);
822
823 pm_runtime_put_sync(pdata->dev);
824 }
825
826 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
827 .attach = ti_sn_bridge_attach,
828 .pre_enable = ti_sn_bridge_pre_enable,
829 .enable = ti_sn_bridge_enable,
830 .disable = ti_sn_bridge_disable,
831 .post_disable = ti_sn_bridge_post_disable,
832 };
833
aux_to_ti_sn_bridge(struct drm_dp_aux * aux)834 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
835 {
836 return container_of(aux, struct ti_sn_bridge, aux);
837 }
838
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)839 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
840 struct drm_dp_aux_msg *msg)
841 {
842 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
843 u32 request = msg->request & ~DP_AUX_I2C_MOT;
844 u32 request_val = AUX_CMD_REQ(msg->request);
845 u8 *buf = (u8 *)msg->buffer;
846 unsigned int val;
847 int ret, i;
848
849 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
850 return -EINVAL;
851
852 switch (request) {
853 case DP_AUX_NATIVE_WRITE:
854 case DP_AUX_I2C_WRITE:
855 case DP_AUX_NATIVE_READ:
856 case DP_AUX_I2C_READ:
857 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
858 break;
859 default:
860 return -EINVAL;
861 }
862
863 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
864 (msg->address >> 16) & 0xF);
865 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
866 (msg->address >> 8) & 0xFF);
867 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
868
869 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
870
871 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
872 for (i = 0; i < msg->size; i++)
873 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
874 buf[i]);
875 }
876
877 /* Clear old status bits before start so we don't get confused */
878 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
879 AUX_IRQ_STATUS_NAT_I2C_FAIL |
880 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
881 AUX_IRQ_STATUS_AUX_SHORT);
882
883 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
884
885 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
886 !(val & AUX_CMD_SEND), 200,
887 50 * 1000);
888 if (ret)
889 return ret;
890
891 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
892 if (ret)
893 return ret;
894 else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
895 || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
896 || (val & AUX_IRQ_STATUS_AUX_SHORT))
897 return -ENXIO;
898
899 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
900 return msg->size;
901
902 for (i = 0; i < msg->size; i++) {
903 unsigned int val;
904 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
905 &val);
906 if (ret)
907 return ret;
908
909 WARN_ON(val & ~0xFF);
910 buf[i] = (u8)(val & 0xFF);
911 }
912
913 return msg->size;
914 }
915
ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge * pdata)916 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
917 {
918 struct device_node *np = pdata->dev->of_node;
919
920 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
921
922 if (!pdata->host_node) {
923 DRM_ERROR("remote dsi host node not found\n");
924 return -ENODEV;
925 }
926
927 return 0;
928 }
929
930 #if defined(CONFIG_OF_GPIO)
931
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)932 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
933 const struct of_phandle_args *gpiospec,
934 u32 *flags)
935 {
936 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
937 return -EINVAL;
938
939 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
940 return -EINVAL;
941
942 if (flags)
943 *flags = gpiospec->args[1];
944
945 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
946 }
947
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)948 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
949 unsigned int offset)
950 {
951 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
952
953 /*
954 * We already have to keep track of the direction because we use
955 * that to figure out whether we've powered the device. We can
956 * just return that rather than (maybe) powering up the device
957 * to ask its direction.
958 */
959 return test_bit(offset, pdata->gchip_output) ?
960 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
961 }
962
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)963 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
964 {
965 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
966 unsigned int val;
967 int ret;
968
969 /*
970 * When the pin is an input we don't forcibly keep the bridge
971 * powered--we just power it on to read the pin. NOTE: part of
972 * the reason this works is that the bridge defaults (when
973 * powered back on) to all 4 GPIOs being configured as GPIO input.
974 * Also note that if something else is keeping the chip powered the
975 * pm_runtime functions are lightweight increments of a refcount.
976 */
977 pm_runtime_get_sync(pdata->dev);
978 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
979 pm_runtime_put(pdata->dev);
980
981 if (ret)
982 return ret;
983
984 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
985 }
986
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)987 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
988 int val)
989 {
990 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
991 int ret;
992
993 if (!test_bit(offset, pdata->gchip_output)) {
994 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
995 return;
996 }
997
998 val &= 1;
999 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1000 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1001 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1002 if (ret)
1003 dev_warn(pdata->dev,
1004 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1005 }
1006
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1007 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1008 unsigned int offset)
1009 {
1010 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1011 int shift = offset * 2;
1012 int ret;
1013
1014 if (!test_and_clear_bit(offset, pdata->gchip_output))
1015 return 0;
1016
1017 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1018 SN_GPIO_MUX_MASK << shift,
1019 SN_GPIO_MUX_INPUT << shift);
1020 if (ret) {
1021 set_bit(offset, pdata->gchip_output);
1022 return ret;
1023 }
1024
1025 /*
1026 * NOTE: if nobody else is powering the device this may fully power
1027 * it off and when it comes back it will have lost all state, but
1028 * that's OK because the default is input and we're now an input.
1029 */
1030 pm_runtime_put(pdata->dev);
1031
1032 return 0;
1033 }
1034
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1035 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1036 unsigned int offset, int val)
1037 {
1038 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1039 int shift = offset * 2;
1040 int ret;
1041
1042 if (test_and_set_bit(offset, pdata->gchip_output))
1043 return 0;
1044
1045 pm_runtime_get_sync(pdata->dev);
1046
1047 /* Set value first to avoid glitching */
1048 ti_sn_bridge_gpio_set(chip, offset, val);
1049
1050 /* Set direction */
1051 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1052 SN_GPIO_MUX_MASK << shift,
1053 SN_GPIO_MUX_OUTPUT << shift);
1054 if (ret) {
1055 clear_bit(offset, pdata->gchip_output);
1056 pm_runtime_put(pdata->dev);
1057 }
1058
1059 return ret;
1060 }
1061
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1062 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1063 {
1064 /* We won't keep pm_runtime if we're input, so switch there on free */
1065 ti_sn_bridge_gpio_direction_input(chip, offset);
1066 }
1067
1068 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1069 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1070 };
1071
ti_sn_setup_gpio_controller(struct ti_sn_bridge * pdata)1072 static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1073 {
1074 int ret;
1075
1076 /* Only init if someone is going to use us as a GPIO controller */
1077 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1078 return 0;
1079
1080 pdata->gchip.label = dev_name(pdata->dev);
1081 pdata->gchip.parent = pdata->dev;
1082 pdata->gchip.owner = THIS_MODULE;
1083 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1084 pdata->gchip.of_gpio_n_cells = 2;
1085 pdata->gchip.free = ti_sn_bridge_gpio_free;
1086 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1087 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1088 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1089 pdata->gchip.get = ti_sn_bridge_gpio_get;
1090 pdata->gchip.set = ti_sn_bridge_gpio_set;
1091 pdata->gchip.can_sleep = true;
1092 pdata->gchip.names = ti_sn_bridge_gpio_names;
1093 pdata->gchip.ngpio = SN_NUM_GPIOS;
1094 pdata->gchip.base = -1;
1095 ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata);
1096 if (ret)
1097 dev_err(pdata->dev, "can't add gpio chip\n");
1098
1099 return ret;
1100 }
1101
1102 #else
1103
ti_sn_setup_gpio_controller(struct ti_sn_bridge * pdata)1104 static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1105 {
1106 return 0;
1107 }
1108
1109 #endif
1110
ti_sn_bridge_parse_lanes(struct ti_sn_bridge * pdata,struct device_node * np)1111 static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata,
1112 struct device_node *np)
1113 {
1114 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1115 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1116 struct device_node *endpoint;
1117 u8 ln_assign = 0;
1118 u8 ln_polrs = 0;
1119 int dp_lanes;
1120 int i;
1121
1122 /*
1123 * Read config from the device tree about lane remapping and lane
1124 * polarities. These are optional and we assume identity map and
1125 * normal polarity if nothing is specified. It's OK to specify just
1126 * data-lanes but not lane-polarities but not vice versa.
1127 *
1128 * Error checking is light (we just make sure we don't crash or
1129 * buffer overrun) and we assume dts is well formed and specifying
1130 * mappings that the hardware supports.
1131 */
1132 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1133 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1134 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1135 of_property_read_u32_array(endpoint, "data-lanes",
1136 lane_assignments, dp_lanes);
1137 of_property_read_u32_array(endpoint, "lane-polarities",
1138 lane_polarities, dp_lanes);
1139 } else {
1140 dp_lanes = SN_MAX_DP_LANES;
1141 }
1142 of_node_put(endpoint);
1143
1144 /*
1145 * Convert into register format. Loop over all lanes even if
1146 * data-lanes had fewer elements so that we nicely initialize
1147 * the LN_ASSIGN register.
1148 */
1149 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1150 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1151 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1152 }
1153
1154 /* Stash in our struct for when we power on */
1155 pdata->dp_lanes = dp_lanes;
1156 pdata->ln_assign = ln_assign;
1157 pdata->ln_polrs = ln_polrs;
1158 }
1159
ti_sn_bridge_probe(struct i2c_client * client,const struct i2c_device_id * id)1160 static int ti_sn_bridge_probe(struct i2c_client *client,
1161 const struct i2c_device_id *id)
1162 {
1163 struct ti_sn_bridge *pdata;
1164 int ret;
1165
1166 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1167 DRM_ERROR("device doesn't support I2C\n");
1168 return -ENODEV;
1169 }
1170
1171 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
1172 GFP_KERNEL);
1173 if (!pdata)
1174 return -ENOMEM;
1175
1176 pdata->regmap = devm_regmap_init_i2c(client,
1177 &ti_sn_bridge_regmap_config);
1178 if (IS_ERR(pdata->regmap)) {
1179 DRM_ERROR("regmap i2c init failed\n");
1180 return PTR_ERR(pdata->regmap);
1181 }
1182
1183 pdata->dev = &client->dev;
1184
1185 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
1186 &pdata->panel, NULL);
1187 if (ret) {
1188 DRM_ERROR("could not find any panel node\n");
1189 return ret;
1190 }
1191
1192 dev_set_drvdata(&client->dev, pdata);
1193
1194 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
1195 GPIOD_OUT_LOW);
1196 if (IS_ERR(pdata->enable_gpio)) {
1197 DRM_ERROR("failed to get enable gpio from DT\n");
1198 ret = PTR_ERR(pdata->enable_gpio);
1199 return ret;
1200 }
1201
1202 ti_sn_bridge_parse_lanes(pdata, client->dev.of_node);
1203
1204 ret = ti_sn_bridge_parse_regulators(pdata);
1205 if (ret) {
1206 DRM_ERROR("failed to parse regulators\n");
1207 return ret;
1208 }
1209
1210 pdata->refclk = devm_clk_get(pdata->dev, "refclk");
1211 if (IS_ERR(pdata->refclk)) {
1212 ret = PTR_ERR(pdata->refclk);
1213 if (ret == -EPROBE_DEFER)
1214 return ret;
1215 DRM_DEBUG_KMS("refclk not found\n");
1216 pdata->refclk = NULL;
1217 }
1218
1219 ret = ti_sn_bridge_parse_dsi_host(pdata);
1220 if (ret)
1221 return ret;
1222
1223 pm_runtime_enable(pdata->dev);
1224
1225 ret = ti_sn_setup_gpio_controller(pdata);
1226 if (ret) {
1227 pm_runtime_disable(pdata->dev);
1228 return ret;
1229 }
1230
1231 i2c_set_clientdata(client, pdata);
1232
1233 pdata->aux.name = "ti-sn65dsi86-aux";
1234 pdata->aux.dev = pdata->dev;
1235 pdata->aux.transfer = ti_sn_aux_transfer;
1236 drm_dp_aux_register(&pdata->aux);
1237
1238 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1239 pdata->bridge.of_node = client->dev.of_node;
1240
1241 drm_bridge_add(&pdata->bridge);
1242
1243 ti_sn_debugfs_init(pdata);
1244
1245 return 0;
1246 }
1247
ti_sn_bridge_remove(struct i2c_client * client)1248 static int ti_sn_bridge_remove(struct i2c_client *client)
1249 {
1250 struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
1251
1252 if (!pdata)
1253 return -EINVAL;
1254
1255 ti_sn_debugfs_remove(pdata);
1256
1257 of_node_put(pdata->host_node);
1258
1259 pm_runtime_disable(pdata->dev);
1260
1261 if (pdata->dsi) {
1262 mipi_dsi_detach(pdata->dsi);
1263 mipi_dsi_device_unregister(pdata->dsi);
1264 }
1265
1266 drm_bridge_remove(&pdata->bridge);
1267
1268 return 0;
1269 }
1270
1271 static struct i2c_device_id ti_sn_bridge_id[] = {
1272 { "ti,sn65dsi86", 0},
1273 {},
1274 };
1275 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
1276
1277 static const struct of_device_id ti_sn_bridge_match_table[] = {
1278 {.compatible = "ti,sn65dsi86"},
1279 {},
1280 };
1281 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
1282
1283 static struct i2c_driver ti_sn_bridge_driver = {
1284 .driver = {
1285 .name = "ti_sn65dsi86",
1286 .of_match_table = ti_sn_bridge_match_table,
1287 .pm = &ti_sn_bridge_pm_ops,
1288 },
1289 .probe = ti_sn_bridge_probe,
1290 .remove = ti_sn_bridge_remove,
1291 .id_table = ti_sn_bridge_id,
1292 };
1293 module_i2c_driver(ti_sn_bridge_driver);
1294
1295 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1296 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1297 MODULE_LICENSE("GPL v2");
1298