1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/console.h>
26 #include <linux/vga_switcheroo.h>
27
28 #include <drm/drm_drv.h>
29 #include <drm/i915_pciids.h>
30
31 #include "display/intel_fbdev.h"
32
33 #include "i915_drv.h"
34 #include "i915_perf.h"
35 #include "i915_globals.h"
36 #include "i915_selftest.h"
37
38 #define PLATFORM(x) .platform = (x)
39 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
40
41 #define I845_PIPE_OFFSETS \
42 .pipe_offsets = { \
43 [TRANSCODER_A] = PIPE_A_OFFSET, \
44 }, \
45 .trans_offsets = { \
46 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
47 }
48
49 #define I9XX_PIPE_OFFSETS \
50 .pipe_offsets = { \
51 [TRANSCODER_A] = PIPE_A_OFFSET, \
52 [TRANSCODER_B] = PIPE_B_OFFSET, \
53 }, \
54 .trans_offsets = { \
55 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
56 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
57 }
58
59 #define IVB_PIPE_OFFSETS \
60 .pipe_offsets = { \
61 [TRANSCODER_A] = PIPE_A_OFFSET, \
62 [TRANSCODER_B] = PIPE_B_OFFSET, \
63 [TRANSCODER_C] = PIPE_C_OFFSET, \
64 }, \
65 .trans_offsets = { \
66 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
67 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
68 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
69 }
70
71 #define HSW_PIPE_OFFSETS \
72 .pipe_offsets = { \
73 [TRANSCODER_A] = PIPE_A_OFFSET, \
74 [TRANSCODER_B] = PIPE_B_OFFSET, \
75 [TRANSCODER_C] = PIPE_C_OFFSET, \
76 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
77 }, \
78 .trans_offsets = { \
79 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
83 }
84
85 #define CHV_PIPE_OFFSETS \
86 .pipe_offsets = { \
87 [TRANSCODER_A] = PIPE_A_OFFSET, \
88 [TRANSCODER_B] = PIPE_B_OFFSET, \
89 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
90 }, \
91 .trans_offsets = { \
92 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
95 }
96
97 #define I845_CURSOR_OFFSETS \
98 .cursor_offsets = { \
99 [PIPE_A] = CURSOR_A_OFFSET, \
100 }
101
102 #define I9XX_CURSOR_OFFSETS \
103 .cursor_offsets = { \
104 [PIPE_A] = CURSOR_A_OFFSET, \
105 [PIPE_B] = CURSOR_B_OFFSET, \
106 }
107
108 #define CHV_CURSOR_OFFSETS \
109 .cursor_offsets = { \
110 [PIPE_A] = CURSOR_A_OFFSET, \
111 [PIPE_B] = CURSOR_B_OFFSET, \
112 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
113 }
114
115 #define IVB_CURSOR_OFFSETS \
116 .cursor_offsets = { \
117 [PIPE_A] = CURSOR_A_OFFSET, \
118 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
119 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
120 }
121
122 #define TGL_CURSOR_OFFSETS \
123 .cursor_offsets = { \
124 [PIPE_A] = CURSOR_A_OFFSET, \
125 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
126 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
127 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
128 }
129
130 #define I9XX_COLORS \
131 .color = { .gamma_lut_size = 256 }
132 #define I965_COLORS \
133 .color = { .gamma_lut_size = 129, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135 }
136 #define ILK_COLORS \
137 .color = { .gamma_lut_size = 1024 }
138 #define IVB_COLORS \
139 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
140 #define CHV_COLORS \
141 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
142 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
144 }
145 #define GLK_COLORS \
146 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
147 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
148 DRM_COLOR_LUT_EQUAL_CHANNELS, \
149 }
150
151 /* Keep in gen based order, and chronological order within a gen */
152
153 #define GEN_DEFAULT_PAGE_SIZES \
154 .page_sizes = I915_GTT_PAGE_SIZE_4K
155
156 #define GEN_DEFAULT_REGIONS \
157 .memory_regions = REGION_SMEM | REGION_STOLEN
158
159 #define I830_FEATURES \
160 GEN(2), \
161 .is_mobile = 1, \
162 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
163 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
164 .display.has_overlay = 1, \
165 .display.cursor_needs_physical = 1, \
166 .display.overlay_needs_physical = 1, \
167 .display.has_gmch = 1, \
168 .gpu_reset_clobbers_display = true, \
169 .hws_needs_physical = 1, \
170 .unfenced_needs_alignment = 1, \
171 .platform_engine_mask = BIT(RCS0), \
172 .has_snoop = true, \
173 .has_coherent_ggtt = false, \
174 .dma_mask_size = 32, \
175 I9XX_PIPE_OFFSETS, \
176 I9XX_CURSOR_OFFSETS, \
177 I9XX_COLORS, \
178 GEN_DEFAULT_PAGE_SIZES, \
179 GEN_DEFAULT_REGIONS
180
181 #define I845_FEATURES \
182 GEN(2), \
183 .pipe_mask = BIT(PIPE_A), \
184 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
185 .display.has_overlay = 1, \
186 .display.overlay_needs_physical = 1, \
187 .display.has_gmch = 1, \
188 .gpu_reset_clobbers_display = true, \
189 .hws_needs_physical = 1, \
190 .unfenced_needs_alignment = 1, \
191 .platform_engine_mask = BIT(RCS0), \
192 .has_snoop = true, \
193 .has_coherent_ggtt = false, \
194 .dma_mask_size = 32, \
195 I845_PIPE_OFFSETS, \
196 I845_CURSOR_OFFSETS, \
197 I9XX_COLORS, \
198 GEN_DEFAULT_PAGE_SIZES, \
199 GEN_DEFAULT_REGIONS
200
201 static const struct intel_device_info i830_info = {
202 I830_FEATURES,
203 PLATFORM(INTEL_I830),
204 };
205
206 static const struct intel_device_info i845g_info = {
207 I845_FEATURES,
208 PLATFORM(INTEL_I845G),
209 };
210
211 static const struct intel_device_info i85x_info = {
212 I830_FEATURES,
213 PLATFORM(INTEL_I85X),
214 .display.has_fbc = 1,
215 };
216
217 static const struct intel_device_info i865g_info = {
218 I845_FEATURES,
219 PLATFORM(INTEL_I865G),
220 .display.has_fbc = 1,
221 };
222
223 #define GEN3_FEATURES \
224 GEN(3), \
225 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
226 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
227 .display.has_gmch = 1, \
228 .gpu_reset_clobbers_display = true, \
229 .platform_engine_mask = BIT(RCS0), \
230 .has_snoop = true, \
231 .has_coherent_ggtt = true, \
232 .dma_mask_size = 32, \
233 I9XX_PIPE_OFFSETS, \
234 I9XX_CURSOR_OFFSETS, \
235 I9XX_COLORS, \
236 GEN_DEFAULT_PAGE_SIZES, \
237 GEN_DEFAULT_REGIONS
238
239 static const struct intel_device_info i915g_info = {
240 GEN3_FEATURES,
241 PLATFORM(INTEL_I915G),
242 .has_coherent_ggtt = false,
243 .display.cursor_needs_physical = 1,
244 .display.has_overlay = 1,
245 .display.overlay_needs_physical = 1,
246 .hws_needs_physical = 1,
247 .unfenced_needs_alignment = 1,
248 };
249
250 static const struct intel_device_info i915gm_info = {
251 GEN3_FEATURES,
252 PLATFORM(INTEL_I915GM),
253 .is_mobile = 1,
254 .display.cursor_needs_physical = 1,
255 .display.has_overlay = 1,
256 .display.overlay_needs_physical = 1,
257 .display.supports_tv = 1,
258 .display.has_fbc = 1,
259 .hws_needs_physical = 1,
260 .unfenced_needs_alignment = 1,
261 };
262
263 static const struct intel_device_info i945g_info = {
264 GEN3_FEATURES,
265 PLATFORM(INTEL_I945G),
266 .display.has_hotplug = 1,
267 .display.cursor_needs_physical = 1,
268 .display.has_overlay = 1,
269 .display.overlay_needs_physical = 1,
270 .hws_needs_physical = 1,
271 .unfenced_needs_alignment = 1,
272 };
273
274 static const struct intel_device_info i945gm_info = {
275 GEN3_FEATURES,
276 PLATFORM(INTEL_I945GM),
277 .is_mobile = 1,
278 .display.has_hotplug = 1,
279 .display.cursor_needs_physical = 1,
280 .display.has_overlay = 1,
281 .display.overlay_needs_physical = 1,
282 .display.supports_tv = 1,
283 .display.has_fbc = 1,
284 .hws_needs_physical = 1,
285 .unfenced_needs_alignment = 1,
286 };
287
288 static const struct intel_device_info g33_info = {
289 GEN3_FEATURES,
290 PLATFORM(INTEL_G33),
291 .display.has_hotplug = 1,
292 .display.has_overlay = 1,
293 .dma_mask_size = 36,
294 };
295
296 static const struct intel_device_info pnv_g_info = {
297 GEN3_FEATURES,
298 PLATFORM(INTEL_PINEVIEW),
299 .display.has_hotplug = 1,
300 .display.has_overlay = 1,
301 .dma_mask_size = 36,
302 };
303
304 static const struct intel_device_info pnv_m_info = {
305 GEN3_FEATURES,
306 PLATFORM(INTEL_PINEVIEW),
307 .is_mobile = 1,
308 .display.has_hotplug = 1,
309 .display.has_overlay = 1,
310 .dma_mask_size = 36,
311 };
312
313 #define GEN4_FEATURES \
314 GEN(4), \
315 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
316 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
317 .display.has_hotplug = 1, \
318 .display.has_gmch = 1, \
319 .gpu_reset_clobbers_display = true, \
320 .platform_engine_mask = BIT(RCS0), \
321 .has_snoop = true, \
322 .has_coherent_ggtt = true, \
323 .dma_mask_size = 36, \
324 I9XX_PIPE_OFFSETS, \
325 I9XX_CURSOR_OFFSETS, \
326 I965_COLORS, \
327 GEN_DEFAULT_PAGE_SIZES, \
328 GEN_DEFAULT_REGIONS
329
330 static const struct intel_device_info i965g_info = {
331 GEN4_FEATURES,
332 PLATFORM(INTEL_I965G),
333 .display.has_overlay = 1,
334 .hws_needs_physical = 1,
335 .has_snoop = false,
336 };
337
338 static const struct intel_device_info i965gm_info = {
339 GEN4_FEATURES,
340 PLATFORM(INTEL_I965GM),
341 .is_mobile = 1,
342 .display.has_fbc = 1,
343 .display.has_overlay = 1,
344 .display.supports_tv = 1,
345 .hws_needs_physical = 1,
346 .has_snoop = false,
347 };
348
349 static const struct intel_device_info g45_info = {
350 GEN4_FEATURES,
351 PLATFORM(INTEL_G45),
352 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
353 .gpu_reset_clobbers_display = false,
354 };
355
356 static const struct intel_device_info gm45_info = {
357 GEN4_FEATURES,
358 PLATFORM(INTEL_GM45),
359 .is_mobile = 1,
360 .display.has_fbc = 1,
361 .display.supports_tv = 1,
362 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
363 .gpu_reset_clobbers_display = false,
364 };
365
366 #define GEN5_FEATURES \
367 GEN(5), \
368 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
369 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
370 .display.has_hotplug = 1, \
371 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
372 .has_snoop = true, \
373 .has_coherent_ggtt = true, \
374 /* ilk does support rc6, but we do not implement [power] contexts */ \
375 .has_rc6 = 0, \
376 .dma_mask_size = 36, \
377 I9XX_PIPE_OFFSETS, \
378 I9XX_CURSOR_OFFSETS, \
379 ILK_COLORS, \
380 GEN_DEFAULT_PAGE_SIZES, \
381 GEN_DEFAULT_REGIONS
382
383 static const struct intel_device_info ilk_d_info = {
384 GEN5_FEATURES,
385 PLATFORM(INTEL_IRONLAKE),
386 };
387
388 static const struct intel_device_info ilk_m_info = {
389 GEN5_FEATURES,
390 PLATFORM(INTEL_IRONLAKE),
391 .is_mobile = 1,
392 .has_rps = true,
393 .display.has_fbc = 1,
394 };
395
396 #define GEN6_FEATURES \
397 GEN(6), \
398 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
399 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
400 .display.has_hotplug = 1, \
401 .display.has_fbc = 1, \
402 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
403 .has_coherent_ggtt = true, \
404 .has_llc = 1, \
405 .has_rc6 = 1, \
406 /* snb does support rc6p, but enabling it causes various issues */ \
407 .has_rc6p = 0, \
408 .has_rps = true, \
409 .dma_mask_size = 40, \
410 .ppgtt_type = INTEL_PPGTT_ALIASING, \
411 .ppgtt_size = 31, \
412 I9XX_PIPE_OFFSETS, \
413 I9XX_CURSOR_OFFSETS, \
414 ILK_COLORS, \
415 GEN_DEFAULT_PAGE_SIZES, \
416 GEN_DEFAULT_REGIONS
417
418 #define SNB_D_PLATFORM \
419 GEN6_FEATURES, \
420 PLATFORM(INTEL_SANDYBRIDGE)
421
422 static const struct intel_device_info snb_d_gt1_info = {
423 SNB_D_PLATFORM,
424 .gt = 1,
425 };
426
427 static const struct intel_device_info snb_d_gt2_info = {
428 SNB_D_PLATFORM,
429 .gt = 2,
430 };
431
432 #define SNB_M_PLATFORM \
433 GEN6_FEATURES, \
434 PLATFORM(INTEL_SANDYBRIDGE), \
435 .is_mobile = 1
436
437
438 static const struct intel_device_info snb_m_gt1_info = {
439 SNB_M_PLATFORM,
440 .gt = 1,
441 };
442
443 static const struct intel_device_info snb_m_gt2_info = {
444 SNB_M_PLATFORM,
445 .gt = 2,
446 };
447
448 #define GEN7_FEATURES \
449 GEN(7), \
450 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
451 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
452 .display.has_hotplug = 1, \
453 .display.has_fbc = 1, \
454 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
455 .has_coherent_ggtt = true, \
456 .has_llc = 1, \
457 .has_rc6 = 1, \
458 .has_rc6p = 1, \
459 .has_rps = true, \
460 .dma_mask_size = 40, \
461 .ppgtt_type = INTEL_PPGTT_ALIASING, \
462 .ppgtt_size = 31, \
463 IVB_PIPE_OFFSETS, \
464 IVB_CURSOR_OFFSETS, \
465 IVB_COLORS, \
466 GEN_DEFAULT_PAGE_SIZES, \
467 GEN_DEFAULT_REGIONS
468
469 #define IVB_D_PLATFORM \
470 GEN7_FEATURES, \
471 PLATFORM(INTEL_IVYBRIDGE), \
472 .has_l3_dpf = 1
473
474 static const struct intel_device_info ivb_d_gt1_info = {
475 IVB_D_PLATFORM,
476 .gt = 1,
477 };
478
479 static const struct intel_device_info ivb_d_gt2_info = {
480 IVB_D_PLATFORM,
481 .gt = 2,
482 };
483
484 #define IVB_M_PLATFORM \
485 GEN7_FEATURES, \
486 PLATFORM(INTEL_IVYBRIDGE), \
487 .is_mobile = 1, \
488 .has_l3_dpf = 1
489
490 static const struct intel_device_info ivb_m_gt1_info = {
491 IVB_M_PLATFORM,
492 .gt = 1,
493 };
494
495 static const struct intel_device_info ivb_m_gt2_info = {
496 IVB_M_PLATFORM,
497 .gt = 2,
498 };
499
500 static const struct intel_device_info ivb_q_info = {
501 GEN7_FEATURES,
502 PLATFORM(INTEL_IVYBRIDGE),
503 .gt = 2,
504 .pipe_mask = 0, /* legal, last one wins */
505 .cpu_transcoder_mask = 0,
506 .has_l3_dpf = 1,
507 };
508
509 static const struct intel_device_info vlv_info = {
510 PLATFORM(INTEL_VALLEYVIEW),
511 GEN(7),
512 .is_lp = 1,
513 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
514 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
515 .has_runtime_pm = 1,
516 .has_rc6 = 1,
517 .has_rps = true,
518 .display.has_gmch = 1,
519 .display.has_hotplug = 1,
520 .dma_mask_size = 40,
521 .ppgtt_type = INTEL_PPGTT_ALIASING,
522 .ppgtt_size = 31,
523 .has_snoop = true,
524 .has_coherent_ggtt = false,
525 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
526 .display_mmio_offset = VLV_DISPLAY_BASE,
527 I9XX_PIPE_OFFSETS,
528 I9XX_CURSOR_OFFSETS,
529 I965_COLORS,
530 GEN_DEFAULT_PAGE_SIZES,
531 GEN_DEFAULT_REGIONS,
532 };
533
534 #define G75_FEATURES \
535 GEN7_FEATURES, \
536 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
537 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
538 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
539 .display.has_ddi = 1, \
540 .has_fpga_dbg = 1, \
541 .display.has_psr = 1, \
542 .display.has_psr_hw_tracking = 1, \
543 .display.has_dp_mst = 1, \
544 .has_rc6p = 0 /* RC6p removed-by HSW */, \
545 HSW_PIPE_OFFSETS, \
546 .has_runtime_pm = 1
547
548 #define HSW_PLATFORM \
549 G75_FEATURES, \
550 PLATFORM(INTEL_HASWELL), \
551 .has_l3_dpf = 1
552
553 static const struct intel_device_info hsw_gt1_info = {
554 HSW_PLATFORM,
555 .gt = 1,
556 };
557
558 static const struct intel_device_info hsw_gt2_info = {
559 HSW_PLATFORM,
560 .gt = 2,
561 };
562
563 static const struct intel_device_info hsw_gt3_info = {
564 HSW_PLATFORM,
565 .gt = 3,
566 };
567
568 #define GEN8_FEATURES \
569 G75_FEATURES, \
570 GEN(8), \
571 .has_logical_ring_contexts = 1, \
572 .dma_mask_size = 39, \
573 .ppgtt_type = INTEL_PPGTT_FULL, \
574 .ppgtt_size = 48, \
575 .has_64bit_reloc = 1, \
576 .has_reset_engine = 1
577
578 #define BDW_PLATFORM \
579 GEN8_FEATURES, \
580 PLATFORM(INTEL_BROADWELL)
581
582 static const struct intel_device_info bdw_gt1_info = {
583 BDW_PLATFORM,
584 .gt = 1,
585 };
586
587 static const struct intel_device_info bdw_gt2_info = {
588 BDW_PLATFORM,
589 .gt = 2,
590 };
591
592 static const struct intel_device_info bdw_rsvd_info = {
593 BDW_PLATFORM,
594 .gt = 3,
595 /* According to the device ID those devices are GT3, they were
596 * previously treated as not GT3, keep it like that.
597 */
598 };
599
600 static const struct intel_device_info bdw_gt3_info = {
601 BDW_PLATFORM,
602 .gt = 3,
603 .platform_engine_mask =
604 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
605 };
606
607 static const struct intel_device_info chv_info = {
608 PLATFORM(INTEL_CHERRYVIEW),
609 GEN(8),
610 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
611 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
612 .display.has_hotplug = 1,
613 .is_lp = 1,
614 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
615 .has_64bit_reloc = 1,
616 .has_runtime_pm = 1,
617 .has_rc6 = 1,
618 .has_rps = true,
619 .has_logical_ring_contexts = 1,
620 .display.has_gmch = 1,
621 .dma_mask_size = 39,
622 .ppgtt_type = INTEL_PPGTT_FULL,
623 .ppgtt_size = 32,
624 .has_reset_engine = 1,
625 .has_snoop = true,
626 .has_coherent_ggtt = false,
627 .display_mmio_offset = VLV_DISPLAY_BASE,
628 CHV_PIPE_OFFSETS,
629 CHV_CURSOR_OFFSETS,
630 CHV_COLORS,
631 GEN_DEFAULT_PAGE_SIZES,
632 GEN_DEFAULT_REGIONS,
633 };
634
635 #define GEN9_DEFAULT_PAGE_SIZES \
636 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
637 I915_GTT_PAGE_SIZE_64K
638
639 #define GEN9_FEATURES \
640 GEN8_FEATURES, \
641 GEN(9), \
642 GEN9_DEFAULT_PAGE_SIZES, \
643 .has_logical_ring_preemption = 1, \
644 .display.has_csr = 1, \
645 .has_gt_uc = 1, \
646 .display.has_hdcp = 1, \
647 .display.has_ipc = 1, \
648 .ddb_size = 896, \
649 .num_supported_dbuf_slices = 1
650
651 #define SKL_PLATFORM \
652 GEN9_FEATURES, \
653 PLATFORM(INTEL_SKYLAKE)
654
655 static const struct intel_device_info skl_gt1_info = {
656 SKL_PLATFORM,
657 .gt = 1,
658 };
659
660 static const struct intel_device_info skl_gt2_info = {
661 SKL_PLATFORM,
662 .gt = 2,
663 };
664
665 #define SKL_GT3_PLUS_PLATFORM \
666 SKL_PLATFORM, \
667 .platform_engine_mask = \
668 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
669
670
671 static const struct intel_device_info skl_gt3_info = {
672 SKL_GT3_PLUS_PLATFORM,
673 .gt = 3,
674 };
675
676 static const struct intel_device_info skl_gt4_info = {
677 SKL_GT3_PLUS_PLATFORM,
678 .gt = 4,
679 };
680
681 #define GEN9_LP_FEATURES \
682 GEN(9), \
683 .is_lp = 1, \
684 .num_supported_dbuf_slices = 1, \
685 .display.has_hotplug = 1, \
686 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
687 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
688 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
689 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
690 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
691 .has_64bit_reloc = 1, \
692 .display.has_ddi = 1, \
693 .has_fpga_dbg = 1, \
694 .display.has_fbc = 1, \
695 .display.has_hdcp = 1, \
696 .display.has_psr = 1, \
697 .display.has_psr_hw_tracking = 1, \
698 .has_runtime_pm = 1, \
699 .display.has_csr = 1, \
700 .has_rc6 = 1, \
701 .has_rps = true, \
702 .display.has_dp_mst = 1, \
703 .has_logical_ring_contexts = 1, \
704 .has_logical_ring_preemption = 1, \
705 .has_gt_uc = 1, \
706 .dma_mask_size = 39, \
707 .ppgtt_type = INTEL_PPGTT_FULL, \
708 .ppgtt_size = 48, \
709 .has_reset_engine = 1, \
710 .has_snoop = true, \
711 .has_coherent_ggtt = false, \
712 .display.has_ipc = 1, \
713 HSW_PIPE_OFFSETS, \
714 IVB_CURSOR_OFFSETS, \
715 IVB_COLORS, \
716 GEN9_DEFAULT_PAGE_SIZES, \
717 GEN_DEFAULT_REGIONS
718
719 static const struct intel_device_info bxt_info = {
720 GEN9_LP_FEATURES,
721 PLATFORM(INTEL_BROXTON),
722 .ddb_size = 512,
723 };
724
725 static const struct intel_device_info glk_info = {
726 GEN9_LP_FEATURES,
727 PLATFORM(INTEL_GEMINILAKE),
728 .ddb_size = 1024,
729 GLK_COLORS,
730 };
731
732 #define KBL_PLATFORM \
733 GEN9_FEATURES, \
734 PLATFORM(INTEL_KABYLAKE)
735
736 static const struct intel_device_info kbl_gt1_info = {
737 KBL_PLATFORM,
738 .gt = 1,
739 };
740
741 static const struct intel_device_info kbl_gt2_info = {
742 KBL_PLATFORM,
743 .gt = 2,
744 };
745
746 static const struct intel_device_info kbl_gt3_info = {
747 KBL_PLATFORM,
748 .gt = 3,
749 .platform_engine_mask =
750 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
751 };
752
753 #define CFL_PLATFORM \
754 GEN9_FEATURES, \
755 PLATFORM(INTEL_COFFEELAKE)
756
757 static const struct intel_device_info cfl_gt1_info = {
758 CFL_PLATFORM,
759 .gt = 1,
760 };
761
762 static const struct intel_device_info cfl_gt2_info = {
763 CFL_PLATFORM,
764 .gt = 2,
765 };
766
767 static const struct intel_device_info cfl_gt3_info = {
768 CFL_PLATFORM,
769 .gt = 3,
770 .platform_engine_mask =
771 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
772 };
773
774 #define CML_PLATFORM \
775 GEN9_FEATURES, \
776 PLATFORM(INTEL_COMETLAKE)
777
778 static const struct intel_device_info cml_gt1_info = {
779 CML_PLATFORM,
780 .gt = 1,
781 };
782
783 static const struct intel_device_info cml_gt2_info = {
784 CML_PLATFORM,
785 .gt = 2,
786 };
787
788 #define GEN10_FEATURES \
789 GEN9_FEATURES, \
790 GEN(10), \
791 .ddb_size = 1024, \
792 .display.has_dsc = 1, \
793 .has_coherent_ggtt = false, \
794 GLK_COLORS
795
796 static const struct intel_device_info cnl_info = {
797 GEN10_FEATURES,
798 PLATFORM(INTEL_CANNONLAKE),
799 .gt = 2,
800 };
801
802 #define GEN11_DEFAULT_PAGE_SIZES \
803 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
804 I915_GTT_PAGE_SIZE_64K | \
805 I915_GTT_PAGE_SIZE_2M
806
807 #define GEN11_FEATURES \
808 GEN10_FEATURES, \
809 GEN11_DEFAULT_PAGE_SIZES, \
810 .abox_mask = BIT(0), \
811 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
812 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
813 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
814 .pipe_offsets = { \
815 [TRANSCODER_A] = PIPE_A_OFFSET, \
816 [TRANSCODER_B] = PIPE_B_OFFSET, \
817 [TRANSCODER_C] = PIPE_C_OFFSET, \
818 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
819 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
820 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
821 }, \
822 .trans_offsets = { \
823 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
824 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
825 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
826 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
827 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
828 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
829 }, \
830 GEN(11), \
831 .ddb_size = 2048, \
832 .num_supported_dbuf_slices = 2, \
833 .has_logical_ring_elsq = 1, \
834 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
835
836 static const struct intel_device_info icl_info = {
837 GEN11_FEATURES,
838 PLATFORM(INTEL_ICELAKE),
839 .platform_engine_mask =
840 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
841 };
842
843 static const struct intel_device_info ehl_info = {
844 GEN11_FEATURES,
845 PLATFORM(INTEL_ELKHARTLAKE),
846 .require_force_probe = 1,
847 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
848 .ppgtt_size = 36,
849 };
850
851 #define GEN12_FEATURES \
852 GEN11_FEATURES, \
853 GEN(12), \
854 .abox_mask = GENMASK(2, 1), \
855 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
856 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
857 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
858 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
859 .pipe_offsets = { \
860 [TRANSCODER_A] = PIPE_A_OFFSET, \
861 [TRANSCODER_B] = PIPE_B_OFFSET, \
862 [TRANSCODER_C] = PIPE_C_OFFSET, \
863 [TRANSCODER_D] = PIPE_D_OFFSET, \
864 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
865 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
866 }, \
867 .trans_offsets = { \
868 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
869 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
870 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
871 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
872 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
873 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
874 }, \
875 TGL_CURSOR_OFFSETS, \
876 .has_global_mocs = 1, \
877 .display.has_dsb = 1
878
879 static const struct intel_device_info tgl_info = {
880 GEN12_FEATURES,
881 PLATFORM(INTEL_TIGERLAKE),
882 .display.has_modular_fia = 1,
883 .platform_engine_mask =
884 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
885 };
886
887 static const struct intel_device_info rkl_info = {
888 GEN12_FEATURES,
889 PLATFORM(INTEL_ROCKETLAKE),
890 .abox_mask = BIT(0),
891 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
892 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
893 BIT(TRANSCODER_C),
894 .require_force_probe = 1,
895 .display.has_hti = 1,
896 .display.has_psr_hw_tracking = 0,
897 .platform_engine_mask =
898 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
899 };
900
901 #define GEN12_DGFX_FEATURES \
902 GEN12_FEATURES, \
903 .memory_regions = REGION_SMEM | REGION_LMEM, \
904 .has_master_unit_irq = 1, \
905 .is_dgfx = 1
906
907 static const struct intel_device_info dg1_info __maybe_unused = {
908 GEN12_DGFX_FEATURES,
909 PLATFORM(INTEL_DG1),
910 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
911 .require_force_probe = 1,
912 .platform_engine_mask =
913 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
914 BIT(VCS0) | BIT(VCS2),
915 };
916
917 #undef GEN
918 #undef PLATFORM
919
920 /*
921 * Make sure any device matches here are from most specific to most
922 * general. For example, since the Quanta match is based on the subsystem
923 * and subvendor IDs, we need it to come before the more general IVB
924 * PCI ID matches, otherwise we'll use the wrong info struct above.
925 */
926 static const struct pci_device_id pciidlist[] = {
927 INTEL_I830_IDS(&i830_info),
928 INTEL_I845G_IDS(&i845g_info),
929 INTEL_I85X_IDS(&i85x_info),
930 INTEL_I865G_IDS(&i865g_info),
931 INTEL_I915G_IDS(&i915g_info),
932 INTEL_I915GM_IDS(&i915gm_info),
933 INTEL_I945G_IDS(&i945g_info),
934 INTEL_I945GM_IDS(&i945gm_info),
935 INTEL_I965G_IDS(&i965g_info),
936 INTEL_G33_IDS(&g33_info),
937 INTEL_I965GM_IDS(&i965gm_info),
938 INTEL_GM45_IDS(&gm45_info),
939 INTEL_G45_IDS(&g45_info),
940 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
941 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
942 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
943 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
944 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
945 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
946 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
947 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
948 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
949 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
950 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
951 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
952 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
953 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
954 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
955 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
956 INTEL_VLV_IDS(&vlv_info),
957 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
958 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
959 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
960 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
961 INTEL_CHV_IDS(&chv_info),
962 INTEL_SKL_GT1_IDS(&skl_gt1_info),
963 INTEL_SKL_GT2_IDS(&skl_gt2_info),
964 INTEL_SKL_GT3_IDS(&skl_gt3_info),
965 INTEL_SKL_GT4_IDS(&skl_gt4_info),
966 INTEL_BXT_IDS(&bxt_info),
967 INTEL_GLK_IDS(&glk_info),
968 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
969 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
970 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
971 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
972 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
973 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
974 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
975 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
976 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
977 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
978 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
979 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
980 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
981 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
982 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
983 INTEL_CML_GT1_IDS(&cml_gt1_info),
984 INTEL_CML_GT2_IDS(&cml_gt2_info),
985 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
986 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
987 INTEL_CNL_IDS(&cnl_info),
988 INTEL_ICL_11_IDS(&icl_info),
989 INTEL_EHL_IDS(&ehl_info),
990 INTEL_TGL_12_IDS(&tgl_info),
991 INTEL_RKL_IDS(&rkl_info),
992 {0, 0, 0}
993 };
994 MODULE_DEVICE_TABLE(pci, pciidlist);
995
i915_pci_remove(struct pci_dev * pdev)996 static void i915_pci_remove(struct pci_dev *pdev)
997 {
998 struct drm_i915_private *i915;
999
1000 i915 = pci_get_drvdata(pdev);
1001 if (!i915) /* driver load aborted, nothing to cleanup */
1002 return;
1003
1004 i915_driver_remove(i915);
1005 pci_set_drvdata(pdev, NULL);
1006 }
1007
1008 /* is device_id present in comma separated list of ids */
force_probe(u16 device_id,const char * devices)1009 static bool force_probe(u16 device_id, const char *devices)
1010 {
1011 char *s, *p, *tok;
1012 bool ret;
1013
1014 if (!devices || !*devices)
1015 return false;
1016
1017 /* match everything */
1018 if (strcmp(devices, "*") == 0)
1019 return true;
1020
1021 s = kstrdup(devices, GFP_KERNEL);
1022 if (!s)
1023 return false;
1024
1025 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1026 u16 val;
1027
1028 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1029 ret = true;
1030 break;
1031 }
1032 }
1033
1034 kfree(s);
1035
1036 return ret;
1037 }
1038
i915_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1039 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1040 {
1041 struct intel_device_info *intel_info =
1042 (struct intel_device_info *) ent->driver_data;
1043 int err;
1044
1045 if (intel_info->require_force_probe &&
1046 !force_probe(pdev->device, i915_modparams.force_probe)) {
1047 dev_info(&pdev->dev,
1048 "Your graphics device %04x is not properly supported by the driver in this\n"
1049 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1050 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1051 "or (recommended) check for kernel updates.\n",
1052 pdev->device, pdev->device, pdev->device);
1053 return -ENODEV;
1054 }
1055
1056 /* Only bind to function 0 of the device. Early generations
1057 * used function 1 as a placeholder for multi-head. This causes
1058 * us confusion instead, especially on the systems where both
1059 * functions have the same PCI-ID!
1060 */
1061 if (PCI_FUNC(pdev->devfn))
1062 return -ENODEV;
1063
1064 /*
1065 * apple-gmux is needed on dual GPU MacBook Pro
1066 * to probe the panel if we're the inactive GPU.
1067 */
1068 if (vga_switcheroo_client_probe_defer(pdev))
1069 return -EPROBE_DEFER;
1070
1071 err = i915_driver_probe(pdev, ent);
1072 if (err)
1073 return err;
1074
1075 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1076 i915_pci_remove(pdev);
1077 return -ENODEV;
1078 }
1079
1080 err = i915_live_selftests(pdev);
1081 if (err) {
1082 i915_pci_remove(pdev);
1083 return err > 0 ? -ENOTTY : err;
1084 }
1085
1086 err = i915_perf_selftests(pdev);
1087 if (err) {
1088 i915_pci_remove(pdev);
1089 return err > 0 ? -ENOTTY : err;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static struct pci_driver i915_pci_driver = {
1096 .name = DRIVER_NAME,
1097 .id_table = pciidlist,
1098 .probe = i915_pci_probe,
1099 .remove = i915_pci_remove,
1100 .driver.pm = &i915_pm_ops,
1101 };
1102
i915_init(void)1103 static int __init i915_init(void)
1104 {
1105 bool use_kms = true;
1106 int err;
1107
1108 err = i915_globals_init();
1109 if (err)
1110 return err;
1111
1112 err = i915_mock_selftests();
1113 if (err)
1114 return err > 0 ? 0 : err;
1115
1116 /*
1117 * Enable KMS by default, unless explicitly overriden by
1118 * either the i915.modeset prarameter or by the
1119 * vga_text_mode_force boot option.
1120 */
1121
1122 if (i915_modparams.modeset == 0)
1123 use_kms = false;
1124
1125 if (vgacon_text_force() && i915_modparams.modeset == -1)
1126 use_kms = false;
1127
1128 if (!use_kms) {
1129 /* Silently fail loading to not upset userspace. */
1130 DRM_DEBUG_DRIVER("KMS disabled.\n");
1131 return 0;
1132 }
1133
1134 err = pci_register_driver(&i915_pci_driver);
1135 if (err)
1136 return err;
1137
1138 i915_perf_sysctl_register();
1139 return 0;
1140 }
1141
i915_exit(void)1142 static void __exit i915_exit(void)
1143 {
1144 if (!i915_pci_driver.driver.owner)
1145 return;
1146
1147 i915_perf_sysctl_unregister();
1148 pci_unregister_driver(&i915_pci_driver);
1149 i915_globals_exit();
1150 }
1151
1152 module_init(i915_init);
1153 module_exit(i915_exit);
1154
1155 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1156 MODULE_AUTHOR("Intel Corporation");
1157
1158 MODULE_DESCRIPTION(DRIVER_DESC);
1159 MODULE_LICENSE("GPL and additional rights");
1160