1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/of_device.h>
7 #include <linux/qcom_scm.h>
8
9 #include "arm-smmu.h"
10
11 struct qcom_smmu {
12 struct arm_smmu_device smmu;
13 bool bypass_quirk;
14 u8 bypass_cbndx;
15 };
16
to_qcom_smmu(struct arm_smmu_device * smmu)17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
18 {
19 return container_of(smmu, struct qcom_smmu, smmu);
20 }
21
22 static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
23 { .compatible = "qcom,adreno" },
24 { .compatible = "qcom,mdp4" },
25 { .compatible = "qcom,mdss" },
26 { .compatible = "qcom,sc7180-mdss" },
27 { .compatible = "qcom,sc7180-mss-pil" },
28 { .compatible = "qcom,sdm845-mdss" },
29 { .compatible = "qcom,sdm845-mss-pil" },
30 { }
31 };
32
qcom_smmu_cfg_probe(struct arm_smmu_device * smmu)33 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
34 {
35 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
36 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
37 u32 reg;
38 u32 smr;
39 int i;
40
41 /*
42 * With some firmware versions writes to S2CR of type FAULT are
43 * ignored, and writing BYPASS will end up written as FAULT in the
44 * register. Perform a write to S2CR to detect if this is the case and
45 * if so reserve a context bank to emulate bypass streams.
46 */
47 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
48 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
49 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
50 arm_smmu_gr0_write(smmu, last_s2cr, reg);
51 reg = arm_smmu_gr0_read(smmu, last_s2cr);
52 if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
53 qsmmu->bypass_quirk = true;
54 qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
55
56 set_bit(qsmmu->bypass_cbndx, smmu->context_map);
57
58 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
59
60 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
61 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
62 }
63
64 for (i = 0; i < smmu->num_mapping_groups; i++) {
65 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
66
67 if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
68 /* Ignore valid bit for SMR mask extraction. */
69 smr &= ~ARM_SMMU_SMR_VALID;
70 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
71 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
72 smmu->smrs[i].valid = true;
73
74 smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
75 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
76 smmu->s2crs[i].cbndx = 0xff;
77 }
78 }
79
80 return 0;
81 }
82
qcom_smmu_write_s2cr(struct arm_smmu_device * smmu,int idx)83 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
84 {
85 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
86 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
87 u32 cbndx = s2cr->cbndx;
88 u32 type = s2cr->type;
89 u32 reg;
90
91 if (qsmmu->bypass_quirk) {
92 if (type == S2CR_TYPE_BYPASS) {
93 /*
94 * Firmware with quirky S2CR handling will substitute
95 * BYPASS writes with FAULT, so point the stream to the
96 * reserved context bank and ask for translation on the
97 * stream
98 */
99 type = S2CR_TYPE_TRANS;
100 cbndx = qsmmu->bypass_cbndx;
101 } else if (type == S2CR_TYPE_FAULT) {
102 /*
103 * Firmware with quirky S2CR handling will ignore FAULT
104 * writes, so trick it to write FAULT by asking for a
105 * BYPASS.
106 */
107 type = S2CR_TYPE_BYPASS;
108 cbndx = 0xff;
109 }
110 }
111
112 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
113 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
114 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
115 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
116 }
117
qcom_smmu_def_domain_type(struct device * dev)118 static int qcom_smmu_def_domain_type(struct device *dev)
119 {
120 const struct of_device_id *match =
121 of_match_device(qcom_smmu_client_of_match, dev);
122
123 return match ? IOMMU_DOMAIN_IDENTITY : 0;
124 }
125
qcom_sdm845_smmu500_reset(struct arm_smmu_device * smmu)126 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
127 {
128 int ret;
129
130 /*
131 * To address performance degradation in non-real time clients,
132 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
133 * such as MTP and db845, whose firmwares implement secure monitor
134 * call handlers to turn on/off the wait-for-safe logic.
135 */
136 ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
137 if (ret)
138 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
139
140 return ret;
141 }
142
qcom_smmu500_reset(struct arm_smmu_device * smmu)143 static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
144 {
145 const struct device_node *np = smmu->dev->of_node;
146
147 arm_mmu500_reset(smmu);
148
149 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
150 return qcom_sdm845_smmu500_reset(smmu);
151
152 return 0;
153 }
154
155 static const struct arm_smmu_impl qcom_smmu_impl = {
156 .cfg_probe = qcom_smmu_cfg_probe,
157 .def_domain_type = qcom_smmu_def_domain_type,
158 .reset = qcom_smmu500_reset,
159 .write_s2cr = qcom_smmu_write_s2cr,
160 };
161
qcom_smmu_impl_init(struct arm_smmu_device * smmu)162 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
163 {
164 struct qcom_smmu *qsmmu;
165
166 /* Check to make sure qcom_scm has finished probing */
167 if (!qcom_scm_is_available())
168 return ERR_PTR(-EPROBE_DEFER);
169
170 qsmmu = devm_kzalloc(smmu->dev, sizeof(*qsmmu), GFP_KERNEL);
171 if (!qsmmu)
172 return ERR_PTR(-ENOMEM);
173
174 qsmmu->smmu = *smmu;
175
176 qsmmu->smmu.impl = &qcom_smmu_impl;
177 devm_kfree(smmu->dev, smmu);
178
179 return &qsmmu->smmu;
180 }
181