1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 /*
15 * iProc SDHCI platform driver
16 */
17
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/module.h>
21 #include <linux/mmc/host.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include "sdhci-pltfm.h"
25
26 struct sdhci_iproc_data {
27 const struct sdhci_pltfm_data *pdata;
28 u32 caps;
29 u32 caps1;
30 u32 mmc_caps;
31 };
32
33 struct sdhci_iproc_host {
34 const struct sdhci_iproc_data *data;
35 u32 shadow_cmd;
36 u32 shadow_blk;
37 bool is_cmd_shadowed;
38 bool is_blk_shadowed;
39 };
40
41 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
42
sdhci_iproc_readl(struct sdhci_host * host,int reg)43 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
44 {
45 u32 val = readl(host->ioaddr + reg);
46
47 pr_debug("%s: readl [0x%02x] 0x%08x\n",
48 mmc_hostname(host->mmc), reg, val);
49 return val;
50 }
51
sdhci_iproc_readw(struct sdhci_host * host,int reg)52 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
53 {
54 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
55 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
56 u32 val;
57 u16 word;
58
59 if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
60 /* Get the saved transfer mode */
61 val = iproc_host->shadow_cmd;
62 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
63 iproc_host->is_blk_shadowed) {
64 /* Get the saved block info */
65 val = iproc_host->shadow_blk;
66 } else {
67 val = sdhci_iproc_readl(host, (reg & ~3));
68 }
69 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
70 return word;
71 }
72
sdhci_iproc_readb(struct sdhci_host * host,int reg)73 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
74 {
75 u32 val = sdhci_iproc_readl(host, (reg & ~3));
76 u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
77 return byte;
78 }
79
sdhci_iproc_writel(struct sdhci_host * host,u32 val,int reg)80 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
81 {
82 pr_debug("%s: writel [0x%02x] 0x%08x\n",
83 mmc_hostname(host->mmc), reg, val);
84
85 writel(val, host->ioaddr + reg);
86
87 if (host->clock <= 400000) {
88 /* Round up to micro-second four SD clock delay */
89 if (host->clock)
90 udelay((4 * 1000000 + host->clock - 1) / host->clock);
91 else
92 udelay(10);
93 }
94 }
95
96 /*
97 * The Arasan has a bugette whereby it may lose the content of successive
98 * writes to the same register that are within two SD-card clock cycles of
99 * each other (a clock domain crossing problem). The data
100 * register does not have this problem, which is just as well - otherwise we'd
101 * have to nobble the DMA engine too.
102 *
103 * This wouldn't be a problem with the code except that we can only write the
104 * controller with 32-bit writes. So two different 16-bit registers are
105 * written back to back creates the problem.
106 *
107 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
108 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
109 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
110 * the work around can be further optimized. We can keep shadow values of
111 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
112 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
113 * by the TRANSFER+COMMAND in another 32-bit write.
114 */
sdhci_iproc_writew(struct sdhci_host * host,u16 val,int reg)115 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
116 {
117 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
118 struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
119 u32 word_shift = REG_OFFSET_IN_BITS(reg);
120 u32 mask = 0xffff << word_shift;
121 u32 oldval, newval;
122
123 if (reg == SDHCI_COMMAND) {
124 /* Write the block now as we are issuing a command */
125 if (iproc_host->is_blk_shadowed) {
126 sdhci_iproc_writel(host, iproc_host->shadow_blk,
127 SDHCI_BLOCK_SIZE);
128 iproc_host->is_blk_shadowed = false;
129 }
130 oldval = iproc_host->shadow_cmd;
131 iproc_host->is_cmd_shadowed = false;
132 } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
133 iproc_host->is_blk_shadowed) {
134 /* Block size and count are stored in shadow reg */
135 oldval = iproc_host->shadow_blk;
136 } else {
137 /* Read reg, all other registers are not shadowed */
138 oldval = sdhci_iproc_readl(host, (reg & ~3));
139 }
140 newval = (oldval & ~mask) | (val << word_shift);
141
142 if (reg == SDHCI_TRANSFER_MODE) {
143 /* Save the transfer mode until the command is issued */
144 iproc_host->shadow_cmd = newval;
145 iproc_host->is_cmd_shadowed = true;
146 } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
147 /* Save the block info until the command is issued */
148 iproc_host->shadow_blk = newval;
149 iproc_host->is_blk_shadowed = true;
150 } else {
151 /* Command or other regular 32-bit write */
152 sdhci_iproc_writel(host, newval, reg & ~3);
153 }
154 }
155
sdhci_iproc_writeb(struct sdhci_host * host,u8 val,int reg)156 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
157 {
158 u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
159 u32 byte_shift = REG_OFFSET_IN_BITS(reg);
160 u32 mask = 0xff << byte_shift;
161 u32 newval = (oldval & ~mask) | (val << byte_shift);
162
163 sdhci_iproc_writel(host, newval, reg & ~3);
164 }
165
sdhci_iproc_get_max_clock(struct sdhci_host * host)166 static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
167 {
168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
169
170 if (pltfm_host->clk)
171 return sdhci_pltfm_clk_get_max_clock(host);
172 else
173 return pltfm_host->clock;
174 }
175
176 /*
177 * There is a known bug on BCM2711's SDHCI core integration where the
178 * controller will hang when the difference between the core clock and the bus
179 * clock is too great. Specifically this can be reproduced under the following
180 * conditions:
181 *
182 * - No SD card plugged in, polling thread is running, probing cards at
183 * 100 kHz.
184 * - BCM2711's core clock configured at 500MHz or more
185 *
186 * So we set 200kHz as the minimum clock frequency available for that SoC.
187 */
sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host * host)188 static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
189 {
190 return 200000;
191 }
192
193 static const struct sdhci_ops sdhci_iproc_ops = {
194 .set_clock = sdhci_set_clock,
195 .get_max_clock = sdhci_iproc_get_max_clock,
196 .set_bus_width = sdhci_set_bus_width,
197 .reset = sdhci_reset,
198 .set_uhs_signaling = sdhci_set_uhs_signaling,
199 };
200
201 static const struct sdhci_ops sdhci_iproc_32only_ops = {
202 .read_l = sdhci_iproc_readl,
203 .read_w = sdhci_iproc_readw,
204 .read_b = sdhci_iproc_readb,
205 .write_l = sdhci_iproc_writel,
206 .write_w = sdhci_iproc_writew,
207 .write_b = sdhci_iproc_writeb,
208 .set_clock = sdhci_set_clock,
209 .get_max_clock = sdhci_iproc_get_max_clock,
210 .set_bus_width = sdhci_set_bus_width,
211 .reset = sdhci_reset,
212 .set_uhs_signaling = sdhci_set_uhs_signaling,
213 };
214
215 static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
216 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
217 SDHCI_QUIRK_NO_HISPD_BIT,
218 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
219 .ops = &sdhci_iproc_32only_ops,
220 };
221
222 static const struct sdhci_iproc_data iproc_cygnus_data = {
223 .pdata = &sdhci_iproc_cygnus_pltfm_data,
224 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
225 & SDHCI_MAX_BLOCK_MASK) |
226 SDHCI_CAN_VDD_330 |
227 SDHCI_CAN_VDD_180 |
228 SDHCI_CAN_DO_SUSPEND |
229 SDHCI_CAN_DO_HISPD |
230 SDHCI_CAN_DO_ADMA2 |
231 SDHCI_CAN_DO_SDMA,
232 .caps1 = SDHCI_DRIVER_TYPE_C |
233 SDHCI_DRIVER_TYPE_D |
234 SDHCI_SUPPORT_DDR50,
235 .mmc_caps = MMC_CAP_1_8V_DDR,
236 };
237
238 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
239 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
240 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
241 SDHCI_QUIRK_NO_HISPD_BIT,
242 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
243 .ops = &sdhci_iproc_ops,
244 };
245
246 static const struct sdhci_iproc_data iproc_data = {
247 .pdata = &sdhci_iproc_pltfm_data,
248 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
249 & SDHCI_MAX_BLOCK_MASK) |
250 SDHCI_CAN_VDD_330 |
251 SDHCI_CAN_VDD_180 |
252 SDHCI_CAN_DO_SUSPEND |
253 SDHCI_CAN_DO_HISPD |
254 SDHCI_CAN_DO_ADMA2 |
255 SDHCI_CAN_DO_SDMA,
256 .caps1 = SDHCI_DRIVER_TYPE_C |
257 SDHCI_DRIVER_TYPE_D |
258 SDHCI_SUPPORT_DDR50,
259 };
260
261 static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
262 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
263 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
264 SDHCI_QUIRK_MISSING_CAPS |
265 SDHCI_QUIRK_NO_HISPD_BIT,
266 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
267 .ops = &sdhci_iproc_32only_ops,
268 };
269
270 static const struct sdhci_iproc_data bcm2835_data = {
271 .pdata = &sdhci_bcm2835_pltfm_data,
272 .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
273 & SDHCI_MAX_BLOCK_MASK) |
274 SDHCI_CAN_VDD_330 |
275 SDHCI_CAN_DO_HISPD,
276 .caps1 = SDHCI_DRIVER_TYPE_A |
277 SDHCI_DRIVER_TYPE_C,
278 .mmc_caps = 0x00000000,
279 };
280
281 static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
282 .read_l = sdhci_iproc_readl,
283 .read_w = sdhci_iproc_readw,
284 .read_b = sdhci_iproc_readb,
285 .write_l = sdhci_iproc_writel,
286 .write_w = sdhci_iproc_writew,
287 .write_b = sdhci_iproc_writeb,
288 .set_clock = sdhci_set_clock,
289 .set_power = sdhci_set_power_and_bus_voltage,
290 .get_max_clock = sdhci_iproc_get_max_clock,
291 .get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
292 .set_bus_width = sdhci_set_bus_width,
293 .reset = sdhci_reset,
294 .set_uhs_signaling = sdhci_set_uhs_signaling,
295 };
296
297 static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
298 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
299 .ops = &sdhci_iproc_bcm2711_ops,
300 };
301
302 static const struct sdhci_iproc_data bcm2711_data = {
303 .pdata = &sdhci_bcm2711_pltfm_data,
304 .mmc_caps = MMC_CAP_3_3V_DDR,
305 };
306
307 static const struct of_device_id sdhci_iproc_of_match[] = {
308 { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
309 { .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
310 { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
311 { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
312 { }
313 };
314 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
315
316 #ifdef CONFIG_ACPI
317 /*
318 * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
319 * which are provided by the ACPI table.
320 */
321 static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
322 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
323 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
324 SDHCI_QUIRK_NO_HISPD_BIT,
325 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
326 .ops = &sdhci_iproc_32only_ops,
327 };
328
329 static const struct sdhci_iproc_data bcm_arasan_data = {
330 .pdata = &sdhci_bcm_arasan_data,
331 };
332
333 static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
334 { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
335 { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
336 { .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
337 { .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
338 { /* sentinel */ }
339 };
340 MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
341 #endif
342
sdhci_iproc_probe(struct platform_device * pdev)343 static int sdhci_iproc_probe(struct platform_device *pdev)
344 {
345 struct device *dev = &pdev->dev;
346 const struct sdhci_iproc_data *iproc_data = NULL;
347 struct sdhci_host *host;
348 struct sdhci_iproc_host *iproc_host;
349 struct sdhci_pltfm_host *pltfm_host;
350 int ret;
351
352 iproc_data = device_get_match_data(dev);
353 if (!iproc_data)
354 return -ENODEV;
355
356 host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
357 if (IS_ERR(host))
358 return PTR_ERR(host);
359
360 pltfm_host = sdhci_priv(host);
361 iproc_host = sdhci_pltfm_priv(pltfm_host);
362
363 iproc_host->data = iproc_data;
364
365 ret = mmc_of_parse(host->mmc);
366 if (ret)
367 goto err;
368
369 sdhci_get_property(pdev);
370
371 host->mmc->caps |= iproc_host->data->mmc_caps;
372
373 if (dev->of_node) {
374 pltfm_host->clk = devm_clk_get(dev, NULL);
375 if (IS_ERR(pltfm_host->clk)) {
376 ret = PTR_ERR(pltfm_host->clk);
377 goto err;
378 }
379 ret = clk_prepare_enable(pltfm_host->clk);
380 if (ret) {
381 dev_err(dev, "failed to enable host clk\n");
382 goto err;
383 }
384 }
385
386 if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
387 host->caps = iproc_host->data->caps;
388 host->caps1 = iproc_host->data->caps1;
389 }
390
391 ret = sdhci_add_host(host);
392 if (ret)
393 goto err_clk;
394
395 return 0;
396
397 err_clk:
398 if (dev->of_node)
399 clk_disable_unprepare(pltfm_host->clk);
400 err:
401 sdhci_pltfm_free(pdev);
402 return ret;
403 }
404
405 static struct platform_driver sdhci_iproc_driver = {
406 .driver = {
407 .name = "sdhci-iproc",
408 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
409 .of_match_table = sdhci_iproc_of_match,
410 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
411 .pm = &sdhci_pltfm_pmops,
412 },
413 .probe = sdhci_iproc_probe,
414 .remove = sdhci_pltfm_unregister,
415 };
416 module_platform_driver(sdhci_iproc_driver);
417
418 MODULE_AUTHOR("Broadcom");
419 MODULE_DESCRIPTION("IPROC SDHCI driver");
420 MODULE_LICENSE("GPL v2");
421