1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <linux/bitfield.h>
13 #include <linux/can.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/error.h>
16 #include <linux/can/led.h>
17 #include <linux/can/rx-offload.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32
33 #define DRV_NAME "flexcan"
34
35 /* 8 for RX fifo and 2 error handling */
36 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
37
38 /* FLEXCAN module configuration register (CANMCR) bits */
39 #define FLEXCAN_MCR_MDIS BIT(31)
40 #define FLEXCAN_MCR_FRZ BIT(30)
41 #define FLEXCAN_MCR_FEN BIT(29)
42 #define FLEXCAN_MCR_HALT BIT(28)
43 #define FLEXCAN_MCR_NOT_RDY BIT(27)
44 #define FLEXCAN_MCR_WAK_MSK BIT(26)
45 #define FLEXCAN_MCR_SOFTRST BIT(25)
46 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
47 #define FLEXCAN_MCR_SUPV BIT(23)
48 #define FLEXCAN_MCR_SLF_WAK BIT(22)
49 #define FLEXCAN_MCR_WRN_EN BIT(21)
50 #define FLEXCAN_MCR_LPM_ACK BIT(20)
51 #define FLEXCAN_MCR_WAK_SRC BIT(19)
52 #define FLEXCAN_MCR_DOZE BIT(18)
53 #define FLEXCAN_MCR_SRX_DIS BIT(17)
54 #define FLEXCAN_MCR_IRMQ BIT(16)
55 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
56 #define FLEXCAN_MCR_AEN BIT(12)
57 #define FLEXCAN_MCR_FDEN BIT(11)
58 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
59 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
60 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
61 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
62 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
63 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
64
65 /* FLEXCAN control register (CANCTRL) bits */
66 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
67 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
68 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
69 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
70 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
71 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
72 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
73 #define FLEXCAN_CTRL_LPB BIT(12)
74 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
75 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
76 #define FLEXCAN_CTRL_SMP BIT(7)
77 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
78 #define FLEXCAN_CTRL_TSYN BIT(5)
79 #define FLEXCAN_CTRL_LBUF BIT(4)
80 #define FLEXCAN_CTRL_LOM BIT(3)
81 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
82 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
83 #define FLEXCAN_CTRL_ERR_STATE \
84 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
85 FLEXCAN_CTRL_BOFF_MSK)
86 #define FLEXCAN_CTRL_ERR_ALL \
87 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
88
89 /* FLEXCAN control register 2 (CTRL2) bits */
90 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
91 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
92 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
93 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
94 #define FLEXCAN_CTRL2_MRP BIT(18)
95 #define FLEXCAN_CTRL2_RRS BIT(17)
96 #define FLEXCAN_CTRL2_EACEN BIT(16)
97 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
98
99 /* FLEXCAN memory error control register (MECR) bits */
100 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
101 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
102 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
103 #define FLEXCAN_MECR_CEI_MSK BIT(16)
104 #define FLEXCAN_MECR_HAERRIE BIT(15)
105 #define FLEXCAN_MECR_FAERRIE BIT(14)
106 #define FLEXCAN_MECR_EXTERRIE BIT(13)
107 #define FLEXCAN_MECR_RERRDIS BIT(9)
108 #define FLEXCAN_MECR_ECCDIS BIT(8)
109 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
110
111 /* FLEXCAN error and status register (ESR) bits */
112 #define FLEXCAN_ESR_TWRN_INT BIT(17)
113 #define FLEXCAN_ESR_RWRN_INT BIT(16)
114 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
115 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
116 #define FLEXCAN_ESR_ACK_ERR BIT(13)
117 #define FLEXCAN_ESR_CRC_ERR BIT(12)
118 #define FLEXCAN_ESR_FRM_ERR BIT(11)
119 #define FLEXCAN_ESR_STF_ERR BIT(10)
120 #define FLEXCAN_ESR_TX_WRN BIT(9)
121 #define FLEXCAN_ESR_RX_WRN BIT(8)
122 #define FLEXCAN_ESR_IDLE BIT(7)
123 #define FLEXCAN_ESR_TXRX BIT(6)
124 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
125 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
126 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
127 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
128 #define FLEXCAN_ESR_BOFF_INT BIT(2)
129 #define FLEXCAN_ESR_ERR_INT BIT(1)
130 #define FLEXCAN_ESR_WAK_INT BIT(0)
131 #define FLEXCAN_ESR_ERR_BUS \
132 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
133 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
134 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
135 #define FLEXCAN_ESR_ERR_STATE \
136 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
137 #define FLEXCAN_ESR_ERR_ALL \
138 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
139 #define FLEXCAN_ESR_ALL_INT \
140 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
141 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
142
143 /* FLEXCAN Bit Timing register (CBT) bits */
144 #define FLEXCAN_CBT_BTF BIT(31)
145 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
146 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
147 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
148 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
149 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
150
151 /* FLEXCAN FD control register (FDCTRL) bits */
152 #define FLEXCAN_FDCTRL_FDRATE BIT(31)
153 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
154 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
155 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
156 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
157 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
158 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
159 #define FLEXCAN_FDCTRL_TDCEN BIT(15)
160 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
161 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
162 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
163
164 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
165 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
166 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
167 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
168 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
169 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
170
171 /* FLEXCAN interrupt flag register (IFLAG) bits */
172 /* Errata ERR005829 step7: Reserve first valid MB */
173 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
174 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
175 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
176 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
177 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
178 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
179 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
180
181 /* FLEXCAN message buffers */
182 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
183 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
184 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
185 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
186 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
187 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
188 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
189
190 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
191 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
192 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
193 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
194
195 #define FLEXCAN_MB_CNT_EDL BIT(31)
196 #define FLEXCAN_MB_CNT_BRS BIT(30)
197 #define FLEXCAN_MB_CNT_ESI BIT(29)
198 #define FLEXCAN_MB_CNT_SRR BIT(22)
199 #define FLEXCAN_MB_CNT_IDE BIT(21)
200 #define FLEXCAN_MB_CNT_RTR BIT(20)
201 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
202 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
203
204 #define FLEXCAN_TIMEOUT_US (250)
205
206 /* FLEXCAN hardware feature flags
207 *
208 * Below is some version info we got:
209 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
210 * Filter? connected? Passive detection ption in MB Supported?
211 * MX25 FlexCAN2 03.00.00.00 no no no no no no
212 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no
213 * MX35 FlexCAN2 03.00.00.00 no no no no no no
214 * MX53 FlexCAN2 03.00.00.00 yes no no no no no
215 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no
216 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes
217 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes
218 * VF610 FlexCAN3 ? no yes no yes yes? no
219 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no
220 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes
221 *
222 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
223 */
224
225 /* [TR]WRN_INT not connected */
226 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
227 /* Disable RX FIFO Global mask */
228 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
229 /* Enable EACEN and RRS bit in ctrl2 */
230 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
231 /* Disable non-correctable errors interrupt and freeze mode */
232 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
233 /* Use timestamp based offloading */
234 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
235 /* No interrupt for error passive */
236 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
237 /* default to BE register access */
238 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
239 /* Setup stop mode to support wakeup */
240 #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)
241 /* Support CAN-FD mode */
242 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
243 /* support memory detection and correction */
244 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
245
246 /* Structure of the message buffer */
247 struct flexcan_mb {
248 u32 can_ctrl;
249 u32 can_id;
250 u32 data[];
251 };
252
253 /* Structure of the hardware registers */
254 struct flexcan_regs {
255 u32 mcr; /* 0x00 */
256 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
257 u32 timer; /* 0x08 */
258 u32 tcr; /* 0x0c */
259 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
260 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
261 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
262 u32 ecr; /* 0x1c */
263 u32 esr; /* 0x20 */
264 u32 imask2; /* 0x24 */
265 u32 imask1; /* 0x28 */
266 u32 iflag2; /* 0x2c */
267 u32 iflag1; /* 0x30 */
268 union { /* 0x34 */
269 u32 gfwr_mx28; /* MX28, MX53 */
270 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
271 };
272 u32 esr2; /* 0x38 */
273 u32 imeur; /* 0x3c */
274 u32 lrfr; /* 0x40 */
275 u32 crcr; /* 0x44 */
276 u32 rxfgmask; /* 0x48 */
277 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
278 u32 cbt; /* 0x50 - Not affected by Soft Reset */
279 u32 _reserved2; /* 0x54 */
280 u32 dbg1; /* 0x58 */
281 u32 dbg2; /* 0x5c */
282 u32 _reserved3[8]; /* 0x60 */
283 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
284 /* FIFO-mode:
285 * MB
286 * 0x080...0x08f 0 RX message buffer
287 * 0x090...0x0df 1-5 reserved
288 * 0x0e0...0x0ff 6-7 8 entry ID table
289 * (mx25, mx28, mx35, mx53)
290 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
291 * size conf'ed via ctrl2::RFFN
292 * (mx6, vf610)
293 */
294 u32 _reserved4[256]; /* 0x480 */
295 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
296 u32 _reserved5[24]; /* 0x980 */
297 u32 gfwr_mx6; /* 0x9e0 - MX6 */
298 u32 _reserved6[39]; /* 0x9e4 */
299 u32 _rxfir[6]; /* 0xa80 */
300 u32 _reserved8[2]; /* 0xa98 */
301 u32 _rxmgmask; /* 0xaa0 */
302 u32 _rxfgmask; /* 0xaa4 */
303 u32 _rx14mask; /* 0xaa8 */
304 u32 _rx15mask; /* 0xaac */
305 u32 tx_smb[4]; /* 0xab0 */
306 u32 rx_smb0[4]; /* 0xac0 */
307 u32 rx_smb1[4]; /* 0xad0 */
308 u32 mecr; /* 0xae0 */
309 u32 erriar; /* 0xae4 */
310 u32 erridpr; /* 0xae8 */
311 u32 errippr; /* 0xaec */
312 u32 rerrar; /* 0xaf0 */
313 u32 rerrdr; /* 0xaf4 */
314 u32 rerrsynr; /* 0xaf8 */
315 u32 errsr; /* 0xafc */
316 u32 _reserved7[64]; /* 0xb00 */
317 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
318 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
319 u32 fdcrc; /* 0xc08 */
320 u32 _reserved9[199]; /* 0xc0c */
321 u32 tx_smb_fd[18]; /* 0xf28 */
322 u32 rx_smb0_fd[18]; /* 0xf70 */
323 u32 rx_smb1_fd[18]; /* 0xfb8 */
324 };
325
326 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
327
328 struct flexcan_devtype_data {
329 u32 quirks; /* quirks needed for different IP cores */
330 };
331
332 struct flexcan_stop_mode {
333 struct regmap *gpr;
334 u8 req_gpr;
335 u8 req_bit;
336 };
337
338 struct flexcan_priv {
339 struct can_priv can;
340 struct can_rx_offload offload;
341 struct device *dev;
342
343 struct flexcan_regs __iomem *regs;
344 struct flexcan_mb __iomem *tx_mb;
345 struct flexcan_mb __iomem *tx_mb_reserved;
346 u8 tx_mb_idx;
347 u8 mb_count;
348 u8 mb_size;
349 u8 clk_src; /* clock source of CAN Protocol Engine */
350
351 u64 rx_mask;
352 u64 tx_mask;
353 u32 reg_ctrl_default;
354
355 struct clk *clk_ipg;
356 struct clk *clk_per;
357 const struct flexcan_devtype_data *devtype_data;
358 struct regulator *reg_xceiver;
359 struct flexcan_stop_mode stm;
360
361 /* Read and Write APIs */
362 u32 (*read)(void __iomem *addr);
363 void (*write)(u32 val, void __iomem *addr);
364 };
365
366 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
367 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
368 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
369 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
370 };
371
372 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
373 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
374 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
375 };
376
377 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
378 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
379 };
380
381 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
382 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
383 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
384 FLEXCAN_QUIRK_SETUP_STOP_MODE,
385 };
386
387 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
388 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
389 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
390 FLEXCAN_QUIRK_SUPPORT_FD,
391 };
392
393 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
394 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
395 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
396 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE |
397 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
398 };
399
400 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
401 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
402 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
403 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
404 };
405
406 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
407 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
408 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
409 };
410
411 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
412 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
413 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
414 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
415 FLEXCAN_QUIRK_SUPPORT_ECC,
416 };
417
418 static const struct can_bittiming_const flexcan_bittiming_const = {
419 .name = DRV_NAME,
420 .tseg1_min = 4,
421 .tseg1_max = 16,
422 .tseg2_min = 2,
423 .tseg2_max = 8,
424 .sjw_max = 4,
425 .brp_min = 1,
426 .brp_max = 256,
427 .brp_inc = 1,
428 };
429
430 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
431 .name = DRV_NAME,
432 .tseg1_min = 2,
433 .tseg1_max = 96,
434 .tseg2_min = 2,
435 .tseg2_max = 32,
436 .sjw_max = 16,
437 .brp_min = 1,
438 .brp_max = 1024,
439 .brp_inc = 1,
440 };
441
442 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
443 .name = DRV_NAME,
444 .tseg1_min = 2,
445 .tseg1_max = 39,
446 .tseg2_min = 2,
447 .tseg2_max = 8,
448 .sjw_max = 4,
449 .brp_min = 1,
450 .brp_max = 1024,
451 .brp_inc = 1,
452 };
453
454 /* FlexCAN module is essentially modelled as a little-endian IP in most
455 * SoCs, i.e the registers as well as the message buffer areas are
456 * implemented in a little-endian fashion.
457 *
458 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
459 * module in a big-endian fashion (i.e the registers as well as the
460 * message buffer areas are implemented in a big-endian way).
461 *
462 * In addition, the FlexCAN module can be found on SoCs having ARM or
463 * PPC cores. So, we need to abstract off the register read/write
464 * functions, ensuring that these cater to all the combinations of module
465 * endianness and underlying CPU endianness.
466 */
flexcan_read_be(void __iomem * addr)467 static inline u32 flexcan_read_be(void __iomem *addr)
468 {
469 return ioread32be(addr);
470 }
471
flexcan_write_be(u32 val,void __iomem * addr)472 static inline void flexcan_write_be(u32 val, void __iomem *addr)
473 {
474 iowrite32be(val, addr);
475 }
476
flexcan_read_le(void __iomem * addr)477 static inline u32 flexcan_read_le(void __iomem *addr)
478 {
479 return ioread32(addr);
480 }
481
flexcan_write_le(u32 val,void __iomem * addr)482 static inline void flexcan_write_le(u32 val, void __iomem *addr)
483 {
484 iowrite32(val, addr);
485 }
486
flexcan_get_mb(const struct flexcan_priv * priv,u8 mb_index)487 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
488 u8 mb_index)
489 {
490 u8 bank_size;
491 bool bank;
492
493 if (WARN_ON(mb_index >= priv->mb_count))
494 return NULL;
495
496 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
497
498 bank = mb_index >= bank_size;
499 if (bank)
500 mb_index -= bank_size;
501
502 return (struct flexcan_mb __iomem *)
503 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
504 }
505
flexcan_low_power_enter_ack(struct flexcan_priv * priv)506 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
507 {
508 struct flexcan_regs __iomem *regs = priv->regs;
509 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
510
511 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
512 udelay(10);
513
514 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
515 return -ETIMEDOUT;
516
517 return 0;
518 }
519
flexcan_low_power_exit_ack(struct flexcan_priv * priv)520 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
521 {
522 struct flexcan_regs __iomem *regs = priv->regs;
523 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
524
525 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
526 udelay(10);
527
528 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
529 return -ETIMEDOUT;
530
531 return 0;
532 }
533
flexcan_enable_wakeup_irq(struct flexcan_priv * priv,bool enable)534 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
535 {
536 struct flexcan_regs __iomem *regs = priv->regs;
537 u32 reg_mcr;
538
539 reg_mcr = priv->read(®s->mcr);
540
541 if (enable)
542 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
543 else
544 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
545
546 priv->write(reg_mcr, ®s->mcr);
547 }
548
flexcan_enter_stop_mode(struct flexcan_priv * priv)549 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
550 {
551 struct flexcan_regs __iomem *regs = priv->regs;
552 u32 reg_mcr;
553
554 reg_mcr = priv->read(®s->mcr);
555 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
556 priv->write(reg_mcr, ®s->mcr);
557
558 /* enable stop request */
559 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
560 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
561
562 return flexcan_low_power_enter_ack(priv);
563 }
564
flexcan_exit_stop_mode(struct flexcan_priv * priv)565 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
566 {
567 struct flexcan_regs __iomem *regs = priv->regs;
568 u32 reg_mcr;
569
570 /* remove stop request */
571 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
572 1 << priv->stm.req_bit, 0);
573
574 reg_mcr = priv->read(®s->mcr);
575 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
576 priv->write(reg_mcr, ®s->mcr);
577
578 return flexcan_low_power_exit_ack(priv);
579 }
580
flexcan_error_irq_enable(const struct flexcan_priv * priv)581 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
582 {
583 struct flexcan_regs __iomem *regs = priv->regs;
584 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
585
586 priv->write(reg_ctrl, ®s->ctrl);
587 }
588
flexcan_error_irq_disable(const struct flexcan_priv * priv)589 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
590 {
591 struct flexcan_regs __iomem *regs = priv->regs;
592 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
593
594 priv->write(reg_ctrl, ®s->ctrl);
595 }
596
flexcan_clks_enable(const struct flexcan_priv * priv)597 static int flexcan_clks_enable(const struct flexcan_priv *priv)
598 {
599 int err;
600
601 err = clk_prepare_enable(priv->clk_ipg);
602 if (err)
603 return err;
604
605 err = clk_prepare_enable(priv->clk_per);
606 if (err)
607 clk_disable_unprepare(priv->clk_ipg);
608
609 return err;
610 }
611
flexcan_clks_disable(const struct flexcan_priv * priv)612 static void flexcan_clks_disable(const struct flexcan_priv *priv)
613 {
614 clk_disable_unprepare(priv->clk_per);
615 clk_disable_unprepare(priv->clk_ipg);
616 }
617
flexcan_transceiver_enable(const struct flexcan_priv * priv)618 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
619 {
620 if (!priv->reg_xceiver)
621 return 0;
622
623 return regulator_enable(priv->reg_xceiver);
624 }
625
flexcan_transceiver_disable(const struct flexcan_priv * priv)626 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
627 {
628 if (!priv->reg_xceiver)
629 return 0;
630
631 return regulator_disable(priv->reg_xceiver);
632 }
633
flexcan_chip_enable(struct flexcan_priv * priv)634 static int flexcan_chip_enable(struct flexcan_priv *priv)
635 {
636 struct flexcan_regs __iomem *regs = priv->regs;
637 u32 reg;
638
639 reg = priv->read(®s->mcr);
640 reg &= ~FLEXCAN_MCR_MDIS;
641 priv->write(reg, ®s->mcr);
642
643 return flexcan_low_power_exit_ack(priv);
644 }
645
flexcan_chip_disable(struct flexcan_priv * priv)646 static int flexcan_chip_disable(struct flexcan_priv *priv)
647 {
648 struct flexcan_regs __iomem *regs = priv->regs;
649 u32 reg;
650
651 reg = priv->read(®s->mcr);
652 reg |= FLEXCAN_MCR_MDIS;
653 priv->write(reg, ®s->mcr);
654
655 return flexcan_low_power_enter_ack(priv);
656 }
657
flexcan_chip_freeze(struct flexcan_priv * priv)658 static int flexcan_chip_freeze(struct flexcan_priv *priv)
659 {
660 struct flexcan_regs __iomem *regs = priv->regs;
661 unsigned int timeout;
662 u32 bitrate = priv->can.bittiming.bitrate;
663 u32 reg;
664
665 if (bitrate)
666 timeout = 1000 * 1000 * 10 / bitrate;
667 else
668 timeout = FLEXCAN_TIMEOUT_US / 10;
669
670 reg = priv->read(®s->mcr);
671 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
672 priv->write(reg, ®s->mcr);
673
674 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
675 udelay(100);
676
677 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
678 return -ETIMEDOUT;
679
680 return 0;
681 }
682
flexcan_chip_unfreeze(struct flexcan_priv * priv)683 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
684 {
685 struct flexcan_regs __iomem *regs = priv->regs;
686 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
687 u32 reg;
688
689 reg = priv->read(®s->mcr);
690 reg &= ~FLEXCAN_MCR_HALT;
691 priv->write(reg, ®s->mcr);
692
693 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
694 udelay(10);
695
696 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
697 return -ETIMEDOUT;
698
699 return 0;
700 }
701
flexcan_chip_softreset(struct flexcan_priv * priv)702 static int flexcan_chip_softreset(struct flexcan_priv *priv)
703 {
704 struct flexcan_regs __iomem *regs = priv->regs;
705 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
706
707 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
708 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
709 udelay(10);
710
711 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
712 return -ETIMEDOUT;
713
714 return 0;
715 }
716
__flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)717 static int __flexcan_get_berr_counter(const struct net_device *dev,
718 struct can_berr_counter *bec)
719 {
720 const struct flexcan_priv *priv = netdev_priv(dev);
721 struct flexcan_regs __iomem *regs = priv->regs;
722 u32 reg = priv->read(®s->ecr);
723
724 bec->txerr = (reg >> 0) & 0xff;
725 bec->rxerr = (reg >> 8) & 0xff;
726
727 return 0;
728 }
729
flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)730 static int flexcan_get_berr_counter(const struct net_device *dev,
731 struct can_berr_counter *bec)
732 {
733 const struct flexcan_priv *priv = netdev_priv(dev);
734 int err;
735
736 err = pm_runtime_get_sync(priv->dev);
737 if (err < 0) {
738 pm_runtime_put_noidle(priv->dev);
739 return err;
740 }
741
742 err = __flexcan_get_berr_counter(dev, bec);
743
744 pm_runtime_put(priv->dev);
745
746 return err;
747 }
748
flexcan_start_xmit(struct sk_buff * skb,struct net_device * dev)749 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
750 {
751 const struct flexcan_priv *priv = netdev_priv(dev);
752 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
753 u32 can_id;
754 u32 data;
755 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16);
756 int i;
757
758 if (can_dropped_invalid_skb(dev, skb))
759 return NETDEV_TX_OK;
760
761 netif_stop_queue(dev);
762
763 if (cfd->can_id & CAN_EFF_FLAG) {
764 can_id = cfd->can_id & CAN_EFF_MASK;
765 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
766 } else {
767 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
768 }
769
770 if (cfd->can_id & CAN_RTR_FLAG)
771 ctrl |= FLEXCAN_MB_CNT_RTR;
772
773 if (can_is_canfd_skb(skb)) {
774 ctrl |= FLEXCAN_MB_CNT_EDL;
775
776 if (cfd->flags & CANFD_BRS)
777 ctrl |= FLEXCAN_MB_CNT_BRS;
778 }
779
780 for (i = 0; i < cfd->len; i += sizeof(u32)) {
781 data = be32_to_cpup((__be32 *)&cfd->data[i]);
782 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
783 }
784
785 can_put_echo_skb(skb, dev, 0);
786
787 priv->write(can_id, &priv->tx_mb->can_id);
788 priv->write(ctrl, &priv->tx_mb->can_ctrl);
789
790 /* Errata ERR005829 step8:
791 * Write twice INACTIVE(0x8) code to first MB.
792 */
793 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
794 &priv->tx_mb_reserved->can_ctrl);
795 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
796 &priv->tx_mb_reserved->can_ctrl);
797
798 return NETDEV_TX_OK;
799 }
800
flexcan_irq_bus_err(struct net_device * dev,u32 reg_esr)801 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
802 {
803 struct flexcan_priv *priv = netdev_priv(dev);
804 struct flexcan_regs __iomem *regs = priv->regs;
805 struct sk_buff *skb;
806 struct can_frame *cf;
807 bool rx_errors = false, tx_errors = false;
808 u32 timestamp;
809 int err;
810
811 timestamp = priv->read(®s->timer) << 16;
812
813 skb = alloc_can_err_skb(dev, &cf);
814 if (unlikely(!skb))
815 return;
816
817 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
818
819 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
820 netdev_dbg(dev, "BIT1_ERR irq\n");
821 cf->data[2] |= CAN_ERR_PROT_BIT1;
822 tx_errors = true;
823 }
824 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
825 netdev_dbg(dev, "BIT0_ERR irq\n");
826 cf->data[2] |= CAN_ERR_PROT_BIT0;
827 tx_errors = true;
828 }
829 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
830 netdev_dbg(dev, "ACK_ERR irq\n");
831 cf->can_id |= CAN_ERR_ACK;
832 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
833 tx_errors = true;
834 }
835 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
836 netdev_dbg(dev, "CRC_ERR irq\n");
837 cf->data[2] |= CAN_ERR_PROT_BIT;
838 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
839 rx_errors = true;
840 }
841 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
842 netdev_dbg(dev, "FRM_ERR irq\n");
843 cf->data[2] |= CAN_ERR_PROT_FORM;
844 rx_errors = true;
845 }
846 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
847 netdev_dbg(dev, "STF_ERR irq\n");
848 cf->data[2] |= CAN_ERR_PROT_STUFF;
849 rx_errors = true;
850 }
851
852 priv->can.can_stats.bus_error++;
853 if (rx_errors)
854 dev->stats.rx_errors++;
855 if (tx_errors)
856 dev->stats.tx_errors++;
857
858 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
859 if (err)
860 dev->stats.rx_fifo_errors++;
861 }
862
flexcan_irq_state(struct net_device * dev,u32 reg_esr)863 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
864 {
865 struct flexcan_priv *priv = netdev_priv(dev);
866 struct flexcan_regs __iomem *regs = priv->regs;
867 struct sk_buff *skb;
868 struct can_frame *cf;
869 enum can_state new_state, rx_state, tx_state;
870 int flt;
871 struct can_berr_counter bec;
872 u32 timestamp;
873 int err;
874
875 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
876 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
877 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
878 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
879 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
880 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
881 new_state = max(tx_state, rx_state);
882 } else {
883 __flexcan_get_berr_counter(dev, &bec);
884 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
885 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
886 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
887 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
888 }
889
890 /* state hasn't changed */
891 if (likely(new_state == priv->can.state))
892 return;
893
894 timestamp = priv->read(®s->timer) << 16;
895
896 skb = alloc_can_err_skb(dev, &cf);
897 if (unlikely(!skb))
898 return;
899
900 can_change_state(dev, cf, tx_state, rx_state);
901
902 if (unlikely(new_state == CAN_STATE_BUS_OFF))
903 can_bus_off(dev);
904
905 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
906 if (err)
907 dev->stats.rx_fifo_errors++;
908 }
909
flexcan_read64_mask(struct flexcan_priv * priv,void __iomem * addr,u64 mask)910 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
911 {
912 u64 reg = 0;
913
914 if (upper_32_bits(mask))
915 reg = (u64)priv->read(addr - 4) << 32;
916 if (lower_32_bits(mask))
917 reg |= priv->read(addr);
918
919 return reg & mask;
920 }
921
flexcan_write64(struct flexcan_priv * priv,u64 val,void __iomem * addr)922 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
923 {
924 if (upper_32_bits(val))
925 priv->write(upper_32_bits(val), addr - 4);
926 if (lower_32_bits(val))
927 priv->write(lower_32_bits(val), addr);
928 }
929
flexcan_read_reg_iflag_rx(struct flexcan_priv * priv)930 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
931 {
932 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
933 }
934
flexcan_read_reg_iflag_tx(struct flexcan_priv * priv)935 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
936 {
937 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
938 }
939
rx_offload_to_priv(struct can_rx_offload * offload)940 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
941 {
942 return container_of(offload, struct flexcan_priv, offload);
943 }
944
flexcan_mailbox_read(struct can_rx_offload * offload,unsigned int n,u32 * timestamp,bool drop)945 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
946 unsigned int n, u32 *timestamp,
947 bool drop)
948 {
949 struct flexcan_priv *priv = rx_offload_to_priv(offload);
950 struct flexcan_regs __iomem *regs = priv->regs;
951 struct flexcan_mb __iomem *mb;
952 struct sk_buff *skb;
953 struct canfd_frame *cfd;
954 u32 reg_ctrl, reg_id, reg_iflag1;
955 int i;
956
957 mb = flexcan_get_mb(priv, n);
958
959 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
960 u32 code;
961
962 do {
963 reg_ctrl = priv->read(&mb->can_ctrl);
964 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
965
966 /* is this MB empty? */
967 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
968 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
969 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
970 return NULL;
971
972 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
973 /* This MB was overrun, we lost data */
974 offload->dev->stats.rx_over_errors++;
975 offload->dev->stats.rx_errors++;
976 }
977 } else {
978 reg_iflag1 = priv->read(®s->iflag1);
979 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
980 return NULL;
981
982 reg_ctrl = priv->read(&mb->can_ctrl);
983 }
984
985 if (unlikely(drop)) {
986 skb = ERR_PTR(-ENOBUFS);
987 goto mark_as_read;
988 }
989
990 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
991 skb = alloc_canfd_skb(offload->dev, &cfd);
992 else
993 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
994 if (unlikely(!skb)) {
995 skb = ERR_PTR(-ENOMEM);
996 goto mark_as_read;
997 }
998
999 /* increase timstamp to full 32 bit */
1000 *timestamp = reg_ctrl << 16;
1001
1002 reg_id = priv->read(&mb->can_id);
1003 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1004 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1005 else
1006 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1007
1008 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1009 cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf));
1010
1011 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1012 cfd->flags |= CANFD_BRS;
1013 } else {
1014 cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf);
1015
1016 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1017 cfd->can_id |= CAN_RTR_FLAG;
1018 }
1019
1020 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1021 cfd->flags |= CANFD_ESI;
1022
1023 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1024 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1025 *(__be32 *)(cfd->data + i) = data;
1026 }
1027
1028 mark_as_read:
1029 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1030 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1031 else
1032 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1033
1034 /* Read the Free Running Timer. It is optional but recommended
1035 * to unlock Mailbox as soon as possible and make it available
1036 * for reception.
1037 */
1038 priv->read(®s->timer);
1039
1040 return skb;
1041 }
1042
flexcan_irq(int irq,void * dev_id)1043 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1044 {
1045 struct net_device *dev = dev_id;
1046 struct net_device_stats *stats = &dev->stats;
1047 struct flexcan_priv *priv = netdev_priv(dev);
1048 struct flexcan_regs __iomem *regs = priv->regs;
1049 irqreturn_t handled = IRQ_NONE;
1050 u64 reg_iflag_tx;
1051 u32 reg_esr;
1052 enum can_state last_state = priv->can.state;
1053
1054 /* reception interrupt */
1055 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1056 u64 reg_iflag_rx;
1057 int ret;
1058
1059 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1060 handled = IRQ_HANDLED;
1061 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1062 reg_iflag_rx);
1063 if (!ret)
1064 break;
1065 }
1066 } else {
1067 u32 reg_iflag1;
1068
1069 reg_iflag1 = priv->read(®s->iflag1);
1070 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1071 handled = IRQ_HANDLED;
1072 can_rx_offload_irq_offload_fifo(&priv->offload);
1073 }
1074
1075 /* FIFO overflow interrupt */
1076 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1077 handled = IRQ_HANDLED;
1078 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1079 ®s->iflag1);
1080 dev->stats.rx_over_errors++;
1081 dev->stats.rx_errors++;
1082 }
1083 }
1084
1085 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1086
1087 /* transmission complete interrupt */
1088 if (reg_iflag_tx & priv->tx_mask) {
1089 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1090
1091 handled = IRQ_HANDLED;
1092 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
1093 0, reg_ctrl << 16);
1094 stats->tx_packets++;
1095 can_led_event(dev, CAN_LED_EVENT_TX);
1096
1097 /* after sending a RTR frame MB is in RX mode */
1098 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1099 &priv->tx_mb->can_ctrl);
1100 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1101 netif_wake_queue(dev);
1102 }
1103
1104 reg_esr = priv->read(®s->esr);
1105
1106 /* ACK all bus error, state change and wake IRQ sources */
1107 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1108 handled = IRQ_HANDLED;
1109 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1110 }
1111
1112 /* state change interrupt or broken error state quirk fix is enabled */
1113 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1114 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1115 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1116 flexcan_irq_state(dev, reg_esr);
1117
1118 /* bus error IRQ - handle if bus error reporting is activated */
1119 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1120 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1121 flexcan_irq_bus_err(dev, reg_esr);
1122
1123 /* availability of error interrupt among state transitions in case
1124 * bus error reporting is de-activated and
1125 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1126 * +--------------------------------------------------------------+
1127 * | +----------------------------------------------+ [stopped / |
1128 * | | | sleeping] -+
1129 * +-+-> active <-> warning <-> passive -> bus off -+
1130 * ___________^^^^^^^^^^^^_______________________________
1131 * disabled(1) enabled disabled
1132 *
1133 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1134 */
1135 if ((last_state != priv->can.state) &&
1136 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1137 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1138 switch (priv->can.state) {
1139 case CAN_STATE_ERROR_ACTIVE:
1140 if (priv->devtype_data->quirks &
1141 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1142 flexcan_error_irq_enable(priv);
1143 else
1144 flexcan_error_irq_disable(priv);
1145 break;
1146
1147 case CAN_STATE_ERROR_WARNING:
1148 flexcan_error_irq_enable(priv);
1149 break;
1150
1151 case CAN_STATE_ERROR_PASSIVE:
1152 case CAN_STATE_BUS_OFF:
1153 flexcan_error_irq_disable(priv);
1154 break;
1155
1156 default:
1157 break;
1158 }
1159 }
1160
1161 return handled;
1162 }
1163
flexcan_set_bittiming_ctrl(const struct net_device * dev)1164 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1165 {
1166 const struct flexcan_priv *priv = netdev_priv(dev);
1167 const struct can_bittiming *bt = &priv->can.bittiming;
1168 struct flexcan_regs __iomem *regs = priv->regs;
1169 u32 reg;
1170
1171 reg = priv->read(®s->ctrl);
1172 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1173 FLEXCAN_CTRL_RJW(0x3) |
1174 FLEXCAN_CTRL_PSEG1(0x7) |
1175 FLEXCAN_CTRL_PSEG2(0x7) |
1176 FLEXCAN_CTRL_PROPSEG(0x7));
1177
1178 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1179 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1180 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1181 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1182 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1183
1184 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1185 priv->write(reg, ®s->ctrl);
1186
1187 /* print chip status */
1188 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1189 priv->read(®s->mcr), priv->read(®s->ctrl));
1190 }
1191
flexcan_set_bittiming_cbt(const struct net_device * dev)1192 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1193 {
1194 struct flexcan_priv *priv = netdev_priv(dev);
1195 struct can_bittiming *bt = &priv->can.bittiming;
1196 struct can_bittiming *dbt = &priv->can.data_bittiming;
1197 struct flexcan_regs __iomem *regs = priv->regs;
1198 u32 reg_cbt, reg_fdctrl;
1199
1200 /* CBT */
1201 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1202 * long. The can_calc_bittiming() tries to divide the tseg1
1203 * equally between phase_seg1 and prop_seg, which may not fit
1204 * in CBT register. Therefore, if phase_seg1 is more than
1205 * possible value, increase prop_seg and decrease phase_seg1.
1206 */
1207 if (bt->phase_seg1 > 0x20) {
1208 bt->prop_seg += (bt->phase_seg1 - 0x20);
1209 bt->phase_seg1 = 0x20;
1210 }
1211
1212 reg_cbt = FLEXCAN_CBT_BTF |
1213 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1214 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1215 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1216 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1217 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1218
1219 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1220 priv->write(reg_cbt, ®s->cbt);
1221
1222 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1223 u32 reg_fdcbt, reg_ctrl2;
1224
1225 if (bt->brp != dbt->brp)
1226 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1227 dbt->brp, bt->brp);
1228
1229 /* FDCBT */
1230 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1231 * 5 bit long. The can_calc_bittiming tries to divide
1232 * the tseg1 equally between phase_seg1 and prop_seg,
1233 * which may not fit in FDCBT register. Therefore, if
1234 * phase_seg1 is more than possible value, increase
1235 * prop_seg and decrease phase_seg1
1236 */
1237 if (dbt->phase_seg1 > 0x8) {
1238 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1239 dbt->phase_seg1 = 0x8;
1240 }
1241
1242 reg_fdcbt = priv->read(®s->fdcbt);
1243 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1244 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1245 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1246 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1247 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1248
1249 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1250 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1251 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1252 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1253 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1254
1255 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1256 priv->write(reg_fdcbt, ®s->fdcbt);
1257
1258 /* CTRL2 */
1259 reg_ctrl2 = priv->read(®s->ctrl2);
1260 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1261 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1262 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1263
1264 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1265 priv->write(reg_ctrl2, ®s->ctrl2);
1266 }
1267
1268 /* FDCTRL */
1269 reg_fdctrl = priv->read(®s->fdctrl);
1270 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1271 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1272
1273 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1274 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1275
1276 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1277 /* TDC must be disabled for Loop Back mode */
1278 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1279 } else {
1280 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1281 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1282 ((dbt->phase_seg1 - 1) +
1283 dbt->prop_seg + 2) *
1284 ((dbt->brp - 1 ) + 1));
1285 }
1286 }
1287
1288 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1289 priv->write(reg_fdctrl, ®s->fdctrl);
1290
1291 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1292 __func__,
1293 priv->read(®s->mcr), priv->read(®s->ctrl),
1294 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1295 priv->read(®s->cbt), priv->read(®s->fdcbt));
1296 }
1297
flexcan_set_bittiming(struct net_device * dev)1298 static void flexcan_set_bittiming(struct net_device *dev)
1299 {
1300 const struct flexcan_priv *priv = netdev_priv(dev);
1301 struct flexcan_regs __iomem *regs = priv->regs;
1302 u32 reg;
1303
1304 reg = priv->read(®s->ctrl);
1305 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1306 FLEXCAN_CTRL_LOM);
1307
1308 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1309 reg |= FLEXCAN_CTRL_LPB;
1310 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1311 reg |= FLEXCAN_CTRL_LOM;
1312 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1313 reg |= FLEXCAN_CTRL_SMP;
1314
1315 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1316 priv->write(reg, ®s->ctrl);
1317
1318 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1319 return flexcan_set_bittiming_cbt(dev);
1320 else
1321 return flexcan_set_bittiming_ctrl(dev);
1322 }
1323
flexcan_ram_init(struct net_device * dev)1324 static void flexcan_ram_init(struct net_device *dev)
1325 {
1326 struct flexcan_priv *priv = netdev_priv(dev);
1327 struct flexcan_regs __iomem *regs = priv->regs;
1328 u32 reg_ctrl2;
1329
1330 /* 11.8.3.13 Detection and correction of memory errors:
1331 * CTRL2[WRMFRZ] grants write access to all memory positions
1332 * that require initialization, ranging from 0x080 to 0xADF
1333 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1334 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1335 * need to be initialized as well. MCR[RFEN] must not be set
1336 * during memory initialization.
1337 */
1338 reg_ctrl2 = priv->read(®s->ctrl2);
1339 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1340 priv->write(reg_ctrl2, ®s->ctrl2);
1341
1342 memset_io(®s->mb[0][0], 0,
1343 offsetof(struct flexcan_regs, rx_smb1[3]) -
1344 offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1345
1346 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1347 memset_io(®s->tx_smb_fd[0], 0,
1348 offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1349 offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1350
1351 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1352 priv->write(reg_ctrl2, ®s->ctrl2);
1353 }
1354
1355 /* flexcan_chip_start
1356 *
1357 * this functions is entered with clocks enabled
1358 *
1359 */
flexcan_chip_start(struct net_device * dev)1360 static int flexcan_chip_start(struct net_device *dev)
1361 {
1362 struct flexcan_priv *priv = netdev_priv(dev);
1363 struct flexcan_regs __iomem *regs = priv->regs;
1364 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1365 u64 reg_imask;
1366 int err, i;
1367 struct flexcan_mb __iomem *mb;
1368
1369 /* enable module */
1370 err = flexcan_chip_enable(priv);
1371 if (err)
1372 return err;
1373
1374 /* soft reset */
1375 err = flexcan_chip_softreset(priv);
1376 if (err)
1377 goto out_chip_disable;
1378
1379 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1380 flexcan_ram_init(dev);
1381
1382 flexcan_set_bittiming(dev);
1383
1384 /* set freeze, halt */
1385 err = flexcan_chip_freeze(priv);
1386 if (err)
1387 goto out_chip_disable;
1388
1389 /* MCR
1390 *
1391 * only supervisor access
1392 * enable warning int
1393 * enable individual RX masking
1394 * choose format C
1395 * set max mailbox number
1396 */
1397 reg_mcr = priv->read(®s->mcr);
1398 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1399 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1400 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1401
1402 /* MCR
1403 *
1404 * FIFO:
1405 * - disable for timestamp mode
1406 * - enable for FIFO mode
1407 */
1408 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1409 reg_mcr &= ~FLEXCAN_MCR_FEN;
1410 else
1411 reg_mcr |= FLEXCAN_MCR_FEN;
1412
1413 /* MCR
1414 *
1415 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1416 * asserted because this will impede the self reception
1417 * of a transmitted message. This is not documented in
1418 * earlier versions of flexcan block guide.
1419 *
1420 * Self Reception:
1421 * - enable Self Reception for loopback mode
1422 * (by clearing "Self Reception Disable" bit)
1423 * - disable for normal operation
1424 */
1425 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1426 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1427 else
1428 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1429
1430 /* MCR - CAN-FD */
1431 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1432 reg_mcr |= FLEXCAN_MCR_FDEN;
1433 else
1434 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1435
1436 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1437 priv->write(reg_mcr, ®s->mcr);
1438
1439 /* CTRL
1440 *
1441 * disable timer sync feature
1442 *
1443 * disable auto busoff recovery
1444 * transmit lowest buffer first
1445 *
1446 * enable tx and rx warning interrupt
1447 * enable bus off interrupt
1448 * (== FLEXCAN_CTRL_ERR_STATE)
1449 */
1450 reg_ctrl = priv->read(®s->ctrl);
1451 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1452 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1453 FLEXCAN_CTRL_ERR_STATE;
1454
1455 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1456 * on most Flexcan cores, too. Otherwise we don't get
1457 * any error warning or passive interrupts.
1458 */
1459 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1460 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1461 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1462 else
1463 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1464
1465 /* save for later use */
1466 priv->reg_ctrl_default = reg_ctrl;
1467 /* leave interrupts disabled for now */
1468 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1469 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1470 priv->write(reg_ctrl, ®s->ctrl);
1471
1472 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1473 reg_ctrl2 = priv->read(®s->ctrl2);
1474 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1475 priv->write(reg_ctrl2, ®s->ctrl2);
1476 }
1477
1478 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1479 u32 reg_fdctrl;
1480
1481 reg_fdctrl = priv->read(®s->fdctrl);
1482 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1483 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1484
1485 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1486 reg_fdctrl |=
1487 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1488 FLEXCAN_FDCTRL_MBDSR_64) |
1489 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1490 FLEXCAN_FDCTRL_MBDSR_64);
1491 } else {
1492 reg_fdctrl |=
1493 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1494 FLEXCAN_FDCTRL_MBDSR_8) |
1495 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1496 FLEXCAN_FDCTRL_MBDSR_8);
1497 }
1498
1499 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1500 __func__, reg_fdctrl);
1501 priv->write(reg_fdctrl, ®s->fdctrl);
1502 }
1503
1504 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1505 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1506 mb = flexcan_get_mb(priv, i);
1507 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1508 &mb->can_ctrl);
1509 }
1510 } else {
1511 /* clear and invalidate unused mailboxes first */
1512 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1513 mb = flexcan_get_mb(priv, i);
1514 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1515 &mb->can_ctrl);
1516 }
1517 }
1518
1519 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1520 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1521 &priv->tx_mb_reserved->can_ctrl);
1522
1523 /* mark TX mailbox as INACTIVE */
1524 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1525 &priv->tx_mb->can_ctrl);
1526
1527 /* acceptance mask/acceptance code (accept everything) */
1528 priv->write(0x0, ®s->rxgmask);
1529 priv->write(0x0, ®s->rx14mask);
1530 priv->write(0x0, ®s->rx15mask);
1531
1532 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1533 priv->write(0x0, ®s->rxfgmask);
1534
1535 /* clear acceptance filters */
1536 for (i = 0; i < priv->mb_count; i++)
1537 priv->write(0, ®s->rximr[i]);
1538
1539 /* On Vybrid, disable non-correctable errors interrupt and
1540 * freeze mode. It still can correct the correctable errors
1541 * when HW supports ECC.
1542 *
1543 * This also works around errata e5295 which generates false
1544 * positive memory errors and put the device in freeze mode.
1545 */
1546 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1547 /* Follow the protocol as described in "Detection
1548 * and Correction of Memory Errors" to write to
1549 * MECR register (step 1 - 5)
1550 *
1551 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1552 * 2. set CTRL2[ECRWRE]
1553 */
1554 reg_ctrl2 = priv->read(®s->ctrl2);
1555 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1556 priv->write(reg_ctrl2, ®s->ctrl2);
1557
1558 /* 3. clear MECR[ECRWRDIS] */
1559 reg_mecr = priv->read(®s->mecr);
1560 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1561 priv->write(reg_mecr, ®s->mecr);
1562
1563 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1564 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1565 FLEXCAN_MECR_FANCEI_MSK);
1566 priv->write(reg_mecr, ®s->mecr);
1567
1568 /* 5. after configuration done, lock MECR by either
1569 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1570 */
1571 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1572 priv->write(reg_mecr, ®s->mecr);
1573
1574 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1575 priv->write(reg_ctrl2, ®s->ctrl2);
1576 }
1577
1578 /* synchronize with the can bus */
1579 err = flexcan_chip_unfreeze(priv);
1580 if (err)
1581 goto out_chip_disable;
1582
1583 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1584
1585 /* enable interrupts atomically */
1586 disable_irq(dev->irq);
1587 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1588 reg_imask = priv->rx_mask | priv->tx_mask;
1589 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1590 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1591 enable_irq(dev->irq);
1592
1593 /* print chip status */
1594 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1595 priv->read(®s->mcr), priv->read(®s->ctrl));
1596
1597 return 0;
1598
1599 out_chip_disable:
1600 flexcan_chip_disable(priv);
1601 return err;
1602 }
1603
1604 /* __flexcan_chip_stop
1605 *
1606 * this function is entered with clocks enabled
1607 */
__flexcan_chip_stop(struct net_device * dev,bool disable_on_error)1608 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1609 {
1610 struct flexcan_priv *priv = netdev_priv(dev);
1611 struct flexcan_regs __iomem *regs = priv->regs;
1612 int err;
1613
1614 /* freeze + disable module */
1615 err = flexcan_chip_freeze(priv);
1616 if (err && !disable_on_error)
1617 return err;
1618 err = flexcan_chip_disable(priv);
1619 if (err && !disable_on_error)
1620 goto out_chip_unfreeze;
1621
1622 /* Disable all interrupts */
1623 priv->write(0, ®s->imask2);
1624 priv->write(0, ®s->imask1);
1625 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1626 ®s->ctrl);
1627
1628 priv->can.state = CAN_STATE_STOPPED;
1629
1630 return 0;
1631
1632 out_chip_unfreeze:
1633 flexcan_chip_unfreeze(priv);
1634
1635 return err;
1636 }
1637
flexcan_chip_stop_disable_on_error(struct net_device * dev)1638 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1639 {
1640 return __flexcan_chip_stop(dev, true);
1641 }
1642
flexcan_chip_stop(struct net_device * dev)1643 static inline int flexcan_chip_stop(struct net_device *dev)
1644 {
1645 return __flexcan_chip_stop(dev, false);
1646 }
1647
flexcan_open(struct net_device * dev)1648 static int flexcan_open(struct net_device *dev)
1649 {
1650 struct flexcan_priv *priv = netdev_priv(dev);
1651 int err;
1652
1653 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1654 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1655 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1656 return -EINVAL;
1657 }
1658
1659 err = pm_runtime_get_sync(priv->dev);
1660 if (err < 0) {
1661 pm_runtime_put_noidle(priv->dev);
1662 return err;
1663 }
1664
1665 err = open_candev(dev);
1666 if (err)
1667 goto out_runtime_put;
1668
1669 err = flexcan_transceiver_enable(priv);
1670 if (err)
1671 goto out_close;
1672
1673 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1674 if (err)
1675 goto out_transceiver_disable;
1676
1677 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1678 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1679 else
1680 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1681 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1682 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1683
1684 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1685 priv->tx_mb_reserved =
1686 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1687 else
1688 priv->tx_mb_reserved =
1689 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1690 priv->tx_mb_idx = priv->mb_count - 1;
1691 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1692 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1693
1694 priv->offload.mailbox_read = flexcan_mailbox_read;
1695
1696 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1697 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1698 priv->offload.mb_last = priv->mb_count - 2;
1699
1700 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1701 priv->offload.mb_first);
1702 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1703 } else {
1704 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1705 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1706 err = can_rx_offload_add_fifo(dev, &priv->offload,
1707 FLEXCAN_NAPI_WEIGHT);
1708 }
1709 if (err)
1710 goto out_free_irq;
1711
1712 /* start chip and queuing */
1713 err = flexcan_chip_start(dev);
1714 if (err)
1715 goto out_offload_del;
1716
1717 can_led_event(dev, CAN_LED_EVENT_OPEN);
1718
1719 can_rx_offload_enable(&priv->offload);
1720 netif_start_queue(dev);
1721
1722 return 0;
1723
1724 out_offload_del:
1725 can_rx_offload_del(&priv->offload);
1726 out_free_irq:
1727 free_irq(dev->irq, dev);
1728 out_transceiver_disable:
1729 flexcan_transceiver_disable(priv);
1730 out_close:
1731 close_candev(dev);
1732 out_runtime_put:
1733 pm_runtime_put(priv->dev);
1734
1735 return err;
1736 }
1737
flexcan_close(struct net_device * dev)1738 static int flexcan_close(struct net_device *dev)
1739 {
1740 struct flexcan_priv *priv = netdev_priv(dev);
1741
1742 netif_stop_queue(dev);
1743 can_rx_offload_disable(&priv->offload);
1744 flexcan_chip_stop_disable_on_error(dev);
1745
1746 can_rx_offload_del(&priv->offload);
1747 free_irq(dev->irq, dev);
1748 flexcan_transceiver_disable(priv);
1749
1750 close_candev(dev);
1751 pm_runtime_put(priv->dev);
1752
1753 can_led_event(dev, CAN_LED_EVENT_STOP);
1754
1755 return 0;
1756 }
1757
flexcan_set_mode(struct net_device * dev,enum can_mode mode)1758 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1759 {
1760 int err;
1761
1762 switch (mode) {
1763 case CAN_MODE_START:
1764 err = flexcan_chip_start(dev);
1765 if (err)
1766 return err;
1767
1768 netif_wake_queue(dev);
1769 break;
1770
1771 default:
1772 return -EOPNOTSUPP;
1773 }
1774
1775 return 0;
1776 }
1777
1778 static const struct net_device_ops flexcan_netdev_ops = {
1779 .ndo_open = flexcan_open,
1780 .ndo_stop = flexcan_close,
1781 .ndo_start_xmit = flexcan_start_xmit,
1782 .ndo_change_mtu = can_change_mtu,
1783 };
1784
register_flexcandev(struct net_device * dev)1785 static int register_flexcandev(struct net_device *dev)
1786 {
1787 struct flexcan_priv *priv = netdev_priv(dev);
1788 struct flexcan_regs __iomem *regs = priv->regs;
1789 u32 reg, err;
1790
1791 err = flexcan_clks_enable(priv);
1792 if (err)
1793 return err;
1794
1795 /* select "bus clock", chip must be disabled */
1796 err = flexcan_chip_disable(priv);
1797 if (err)
1798 goto out_clks_disable;
1799
1800 reg = priv->read(®s->ctrl);
1801 if (priv->clk_src)
1802 reg |= FLEXCAN_CTRL_CLK_SRC;
1803 else
1804 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1805 priv->write(reg, ®s->ctrl);
1806
1807 err = flexcan_chip_enable(priv);
1808 if (err)
1809 goto out_chip_disable;
1810
1811 /* set freeze, halt */
1812 err = flexcan_chip_freeze(priv);
1813 if (err)
1814 goto out_chip_disable;
1815
1816 /* activate FIFO, restrict register access */
1817 reg = priv->read(®s->mcr);
1818 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1819 priv->write(reg, ®s->mcr);
1820
1821 /* Currently we only support newer versions of this core
1822 * featuring a RX hardware FIFO (although this driver doesn't
1823 * make use of it on some cores). Older cores, found on some
1824 * Coldfire derivates are not tested.
1825 */
1826 reg = priv->read(®s->mcr);
1827 if (!(reg & FLEXCAN_MCR_FEN)) {
1828 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1829 err = -ENODEV;
1830 goto out_chip_disable;
1831 }
1832
1833 err = register_candev(dev);
1834 if (err)
1835 goto out_chip_disable;
1836
1837 /* Disable core and let pm_runtime_put() disable the clocks.
1838 * If CONFIG_PM is not enabled, the clocks will stay powered.
1839 */
1840 flexcan_chip_disable(priv);
1841 pm_runtime_put(priv->dev);
1842
1843 return 0;
1844
1845 out_chip_disable:
1846 flexcan_chip_disable(priv);
1847 out_clks_disable:
1848 flexcan_clks_disable(priv);
1849 return err;
1850 }
1851
unregister_flexcandev(struct net_device * dev)1852 static void unregister_flexcandev(struct net_device *dev)
1853 {
1854 unregister_candev(dev);
1855 }
1856
flexcan_setup_stop_mode(struct platform_device * pdev)1857 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1858 {
1859 struct net_device *dev = platform_get_drvdata(pdev);
1860 struct device_node *np = pdev->dev.of_node;
1861 struct device_node *gpr_np;
1862 struct flexcan_priv *priv;
1863 phandle phandle;
1864 u32 out_val[3];
1865 int ret;
1866
1867 if (!np)
1868 return -EINVAL;
1869
1870 /* stop mode property format is:
1871 * <&gpr req_gpr req_bit>.
1872 */
1873 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1874 ARRAY_SIZE(out_val));
1875 if (ret) {
1876 dev_dbg(&pdev->dev, "no stop-mode property\n");
1877 return ret;
1878 }
1879 phandle = *out_val;
1880
1881 gpr_np = of_find_node_by_phandle(phandle);
1882 if (!gpr_np) {
1883 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1884 return -ENODEV;
1885 }
1886
1887 priv = netdev_priv(dev);
1888 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1889 if (IS_ERR(priv->stm.gpr)) {
1890 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1891 ret = PTR_ERR(priv->stm.gpr);
1892 goto out_put_node;
1893 }
1894
1895 priv->stm.req_gpr = out_val[1];
1896 priv->stm.req_bit = out_val[2];
1897
1898 dev_dbg(&pdev->dev,
1899 "gpr %s req_gpr=0x02%x req_bit=%u\n",
1900 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
1901
1902 device_set_wakeup_capable(&pdev->dev, true);
1903
1904 if (of_property_read_bool(np, "wakeup-source"))
1905 device_set_wakeup_enable(&pdev->dev, true);
1906
1907 return 0;
1908
1909 out_put_node:
1910 of_node_put(gpr_np);
1911 return ret;
1912 }
1913
1914 static const struct of_device_id flexcan_of_match[] = {
1915 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
1916 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
1917 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1918 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1919 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1920 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1921 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1922 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1923 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1924 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1925 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
1926 { /* sentinel */ },
1927 };
1928 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1929
1930 static const struct platform_device_id flexcan_id_table[] = {
1931 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1932 { /* sentinel */ },
1933 };
1934 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1935
flexcan_probe(struct platform_device * pdev)1936 static int flexcan_probe(struct platform_device *pdev)
1937 {
1938 const struct of_device_id *of_id;
1939 const struct flexcan_devtype_data *devtype_data;
1940 struct net_device *dev;
1941 struct flexcan_priv *priv;
1942 struct regulator *reg_xceiver;
1943 struct clk *clk_ipg = NULL, *clk_per = NULL;
1944 struct flexcan_regs __iomem *regs;
1945 int err, irq;
1946 u8 clk_src = 1;
1947 u32 clock_freq = 0;
1948
1949 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
1950 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1951 return -EPROBE_DEFER;
1952 else if (PTR_ERR(reg_xceiver) == -ENODEV)
1953 reg_xceiver = NULL;
1954 else if (IS_ERR(reg_xceiver))
1955 return PTR_ERR(reg_xceiver);
1956
1957 if (pdev->dev.of_node) {
1958 of_property_read_u32(pdev->dev.of_node,
1959 "clock-frequency", &clock_freq);
1960 of_property_read_u8(pdev->dev.of_node,
1961 "fsl,clk-source", &clk_src);
1962 }
1963
1964 if (!clock_freq) {
1965 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1966 if (IS_ERR(clk_ipg)) {
1967 dev_err(&pdev->dev, "no ipg clock defined\n");
1968 return PTR_ERR(clk_ipg);
1969 }
1970
1971 clk_per = devm_clk_get(&pdev->dev, "per");
1972 if (IS_ERR(clk_per)) {
1973 dev_err(&pdev->dev, "no per clock defined\n");
1974 return PTR_ERR(clk_per);
1975 }
1976 clock_freq = clk_get_rate(clk_per);
1977 }
1978
1979 irq = platform_get_irq(pdev, 0);
1980 if (irq <= 0)
1981 return -ENODEV;
1982
1983 regs = devm_platform_ioremap_resource(pdev, 0);
1984 if (IS_ERR(regs))
1985 return PTR_ERR(regs);
1986
1987 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1988 if (of_id) {
1989 devtype_data = of_id->data;
1990 } else if (platform_get_device_id(pdev)->driver_data) {
1991 devtype_data = (struct flexcan_devtype_data *)
1992 platform_get_device_id(pdev)->driver_data;
1993 } else {
1994 return -ENODEV;
1995 }
1996
1997 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
1998 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
1999 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
2000 return -EINVAL;
2001 }
2002
2003 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2004 if (!dev)
2005 return -ENOMEM;
2006
2007 platform_set_drvdata(pdev, dev);
2008 SET_NETDEV_DEV(dev, &pdev->dev);
2009
2010 dev->netdev_ops = &flexcan_netdev_ops;
2011 dev->irq = irq;
2012 dev->flags |= IFF_ECHO;
2013
2014 priv = netdev_priv(dev);
2015
2016 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2017 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2018 priv->read = flexcan_read_be;
2019 priv->write = flexcan_write_be;
2020 } else {
2021 priv->read = flexcan_read_le;
2022 priv->write = flexcan_write_le;
2023 }
2024
2025 priv->dev = &pdev->dev;
2026 priv->can.clock.freq = clock_freq;
2027 priv->can.do_set_mode = flexcan_set_mode;
2028 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2029 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2030 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2031 CAN_CTRLMODE_BERR_REPORTING;
2032 priv->regs = regs;
2033 priv->clk_ipg = clk_ipg;
2034 priv->clk_per = clk_per;
2035 priv->clk_src = clk_src;
2036 priv->devtype_data = devtype_data;
2037 priv->reg_xceiver = reg_xceiver;
2038
2039 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2040 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2041 CAN_CTRLMODE_FD_NON_ISO;
2042 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2043 priv->can.data_bittiming_const =
2044 &flexcan_fd_data_bittiming_const;
2045 } else {
2046 priv->can.bittiming_const = &flexcan_bittiming_const;
2047 }
2048
2049 pm_runtime_get_noresume(&pdev->dev);
2050 pm_runtime_set_active(&pdev->dev);
2051 pm_runtime_enable(&pdev->dev);
2052
2053 err = register_flexcandev(dev);
2054 if (err) {
2055 dev_err(&pdev->dev, "registering netdev failed\n");
2056 goto failed_register;
2057 }
2058
2059 of_can_transceiver(dev);
2060 devm_can_led_init(dev);
2061
2062 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
2063 err = flexcan_setup_stop_mode(pdev);
2064 if (err)
2065 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
2066 }
2067
2068 return 0;
2069
2070 failed_register:
2071 pm_runtime_put_noidle(&pdev->dev);
2072 pm_runtime_disable(&pdev->dev);
2073 free_candev(dev);
2074 return err;
2075 }
2076
flexcan_remove(struct platform_device * pdev)2077 static int flexcan_remove(struct platform_device *pdev)
2078 {
2079 struct net_device *dev = platform_get_drvdata(pdev);
2080
2081 device_set_wakeup_enable(&pdev->dev, false);
2082 device_set_wakeup_capable(&pdev->dev, false);
2083 unregister_flexcandev(dev);
2084 pm_runtime_disable(&pdev->dev);
2085 free_candev(dev);
2086
2087 return 0;
2088 }
2089
flexcan_suspend(struct device * device)2090 static int __maybe_unused flexcan_suspend(struct device *device)
2091 {
2092 struct net_device *dev = dev_get_drvdata(device);
2093 struct flexcan_priv *priv = netdev_priv(dev);
2094 int err;
2095
2096 if (netif_running(dev)) {
2097 /* if wakeup is enabled, enter stop mode
2098 * else enter disabled mode.
2099 */
2100 if (device_may_wakeup(device)) {
2101 enable_irq_wake(dev->irq);
2102 err = flexcan_enter_stop_mode(priv);
2103 if (err)
2104 return err;
2105 } else {
2106 err = flexcan_chip_stop(dev);
2107 if (err)
2108 return err;
2109
2110 err = pinctrl_pm_select_sleep_state(device);
2111 if (err)
2112 return err;
2113 }
2114 netif_stop_queue(dev);
2115 netif_device_detach(dev);
2116 }
2117 priv->can.state = CAN_STATE_SLEEPING;
2118
2119 return 0;
2120 }
2121
flexcan_resume(struct device * device)2122 static int __maybe_unused flexcan_resume(struct device *device)
2123 {
2124 struct net_device *dev = dev_get_drvdata(device);
2125 struct flexcan_priv *priv = netdev_priv(dev);
2126 int err;
2127
2128 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2129 if (netif_running(dev)) {
2130 netif_device_attach(dev);
2131 netif_start_queue(dev);
2132 if (device_may_wakeup(device)) {
2133 disable_irq_wake(dev->irq);
2134 err = flexcan_exit_stop_mode(priv);
2135 if (err)
2136 return err;
2137 } else {
2138 err = pinctrl_pm_select_default_state(device);
2139 if (err)
2140 return err;
2141
2142 err = flexcan_chip_start(dev);
2143 if (err)
2144 return err;
2145 }
2146 }
2147
2148 return 0;
2149 }
2150
flexcan_runtime_suspend(struct device * device)2151 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2152 {
2153 struct net_device *dev = dev_get_drvdata(device);
2154 struct flexcan_priv *priv = netdev_priv(dev);
2155
2156 flexcan_clks_disable(priv);
2157
2158 return 0;
2159 }
2160
flexcan_runtime_resume(struct device * device)2161 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2162 {
2163 struct net_device *dev = dev_get_drvdata(device);
2164 struct flexcan_priv *priv = netdev_priv(dev);
2165
2166 return flexcan_clks_enable(priv);
2167 }
2168
flexcan_noirq_suspend(struct device * device)2169 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2170 {
2171 struct net_device *dev = dev_get_drvdata(device);
2172 struct flexcan_priv *priv = netdev_priv(dev);
2173
2174 if (netif_running(dev)) {
2175 int err;
2176
2177 if (device_may_wakeup(device))
2178 flexcan_enable_wakeup_irq(priv, true);
2179
2180 err = pm_runtime_force_suspend(device);
2181 if (err)
2182 return err;
2183 }
2184
2185 return 0;
2186 }
2187
flexcan_noirq_resume(struct device * device)2188 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2189 {
2190 struct net_device *dev = dev_get_drvdata(device);
2191 struct flexcan_priv *priv = netdev_priv(dev);
2192
2193 if (netif_running(dev)) {
2194 int err;
2195
2196 err = pm_runtime_force_resume(device);
2197 if (err)
2198 return err;
2199
2200 if (device_may_wakeup(device))
2201 flexcan_enable_wakeup_irq(priv, false);
2202 }
2203
2204 return 0;
2205 }
2206
2207 static const struct dev_pm_ops flexcan_pm_ops = {
2208 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2209 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2210 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2211 };
2212
2213 static struct platform_driver flexcan_driver = {
2214 .driver = {
2215 .name = DRV_NAME,
2216 .pm = &flexcan_pm_ops,
2217 .of_match_table = flexcan_of_match,
2218 },
2219 .probe = flexcan_probe,
2220 .remove = flexcan_remove,
2221 .id_table = flexcan_id_table,
2222 };
2223
2224 module_platform_driver(flexcan_driver);
2225
2226 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2227 "Marc Kleine-Budde <kernel@pengutronix.de>");
2228 MODULE_LICENSE("GPL v2");
2229 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2230