1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7 #include <linux/types.h>
8 #include <asm/byteorder.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/if_vlan.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/stddef.h>
15 #include <linux/workqueue.h>
16 #include <net/ipv6.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/errno.h>
20 #include <linux/etherdevice.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/mutex.h>
24 #include <linux/spinlock.h>
25 #include <linux/string.h>
26 #include <linux/qed/qed_ll2_if.h>
27 #include "qed.h"
28 #include "qed_cxt.h"
29 #include "qed_dev_api.h"
30 #include "qed_hsi.h"
31 #include "qed_hw.h"
32 #include "qed_int.h"
33 #include "qed_ll2.h"
34 #include "qed_mcp.h"
35 #include "qed_ooo.h"
36 #include "qed_reg_addr.h"
37 #include "qed_sp.h"
38 #include "qed_rdma.h"
39
40 #define QED_LL2_RX_REGISTERED(ll2) ((ll2)->rx_queue.b_cb_registered)
41 #define QED_LL2_TX_REGISTERED(ll2) ((ll2)->tx_queue.b_cb_registered)
42
43 #define QED_LL2_TX_SIZE (256)
44 #define QED_LL2_RX_SIZE (4096)
45
46 struct qed_cb_ll2_info {
47 int rx_cnt;
48 u32 rx_size;
49 u8 handle;
50
51 /* Lock protecting LL2 buffer lists in sleepless context */
52 spinlock_t lock;
53 struct list_head list;
54
55 const struct qed_ll2_cb_ops *cbs;
56 void *cb_cookie;
57 };
58
59 struct qed_ll2_buffer {
60 struct list_head list;
61 void *data;
62 dma_addr_t phys_addr;
63 };
64
qed_ll2b_complete_tx_packet(void * cxt,u8 connection_handle,void * cookie,dma_addr_t first_frag_addr,bool b_last_fragment,bool b_last_packet)65 static void qed_ll2b_complete_tx_packet(void *cxt,
66 u8 connection_handle,
67 void *cookie,
68 dma_addr_t first_frag_addr,
69 bool b_last_fragment,
70 bool b_last_packet)
71 {
72 struct qed_hwfn *p_hwfn = cxt;
73 struct qed_dev *cdev = p_hwfn->cdev;
74 struct sk_buff *skb = cookie;
75
76 /* All we need to do is release the mapping */
77 dma_unmap_single(&p_hwfn->cdev->pdev->dev, first_frag_addr,
78 skb_headlen(skb), DMA_TO_DEVICE);
79
80 if (cdev->ll2->cbs && cdev->ll2->cbs->tx_cb)
81 cdev->ll2->cbs->tx_cb(cdev->ll2->cb_cookie, skb,
82 b_last_fragment);
83
84 dev_kfree_skb_any(skb);
85 }
86
qed_ll2_alloc_buffer(struct qed_dev * cdev,u8 ** data,dma_addr_t * phys_addr)87 static int qed_ll2_alloc_buffer(struct qed_dev *cdev,
88 u8 **data, dma_addr_t *phys_addr)
89 {
90 *data = kmalloc(cdev->ll2->rx_size, GFP_ATOMIC);
91 if (!(*data)) {
92 DP_INFO(cdev, "Failed to allocate LL2 buffer data\n");
93 return -ENOMEM;
94 }
95
96 *phys_addr = dma_map_single(&cdev->pdev->dev,
97 ((*data) + NET_SKB_PAD),
98 cdev->ll2->rx_size, DMA_FROM_DEVICE);
99 if (dma_mapping_error(&cdev->pdev->dev, *phys_addr)) {
100 DP_INFO(cdev, "Failed to map LL2 buffer data\n");
101 kfree((*data));
102 return -ENOMEM;
103 }
104
105 return 0;
106 }
107
qed_ll2_dealloc_buffer(struct qed_dev * cdev,struct qed_ll2_buffer * buffer)108 static int qed_ll2_dealloc_buffer(struct qed_dev *cdev,
109 struct qed_ll2_buffer *buffer)
110 {
111 spin_lock_bh(&cdev->ll2->lock);
112
113 dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
114 cdev->ll2->rx_size, DMA_FROM_DEVICE);
115 kfree(buffer->data);
116 list_del(&buffer->list);
117
118 cdev->ll2->rx_cnt--;
119 if (!cdev->ll2->rx_cnt)
120 DP_INFO(cdev, "All LL2 entries were removed\n");
121
122 spin_unlock_bh(&cdev->ll2->lock);
123
124 return 0;
125 }
126
qed_ll2_kill_buffers(struct qed_dev * cdev)127 static void qed_ll2_kill_buffers(struct qed_dev *cdev)
128 {
129 struct qed_ll2_buffer *buffer, *tmp_buffer;
130
131 list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list)
132 qed_ll2_dealloc_buffer(cdev, buffer);
133 }
134
qed_ll2b_complete_rx_packet(void * cxt,struct qed_ll2_comp_rx_data * data)135 static void qed_ll2b_complete_rx_packet(void *cxt,
136 struct qed_ll2_comp_rx_data *data)
137 {
138 struct qed_hwfn *p_hwfn = cxt;
139 struct qed_ll2_buffer *buffer = data->cookie;
140 struct qed_dev *cdev = p_hwfn->cdev;
141 dma_addr_t new_phys_addr;
142 struct sk_buff *skb;
143 bool reuse = false;
144 int rc = -EINVAL;
145 u8 *new_data;
146
147 DP_VERBOSE(p_hwfn,
148 (NETIF_MSG_RX_STATUS | QED_MSG_STORAGE | NETIF_MSG_PKTDATA),
149 "Got an LL2 Rx completion: [Buffer at phys 0x%llx, offset 0x%02x] Length 0x%04x Parse_flags 0x%04x vlan 0x%04x Opaque data [0x%08x:0x%08x]\n",
150 (u64)data->rx_buf_addr,
151 data->u.placement_offset,
152 data->length.packet_length,
153 data->parse_flags,
154 data->vlan, data->opaque_data_0, data->opaque_data_1);
155
156 if ((cdev->dp_module & NETIF_MSG_PKTDATA) && buffer->data) {
157 print_hex_dump(KERN_INFO, "",
158 DUMP_PREFIX_OFFSET, 16, 1,
159 buffer->data, data->length.packet_length, false);
160 }
161
162 /* Determine if data is valid */
163 if (data->length.packet_length < ETH_HLEN)
164 reuse = true;
165
166 /* Allocate a replacement for buffer; Reuse upon failure */
167 if (!reuse)
168 rc = qed_ll2_alloc_buffer(p_hwfn->cdev, &new_data,
169 &new_phys_addr);
170
171 /* If need to reuse or there's no replacement buffer, repost this */
172 if (rc)
173 goto out_post;
174 dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
175 cdev->ll2->rx_size, DMA_FROM_DEVICE);
176
177 skb = build_skb(buffer->data, 0);
178 if (!skb) {
179 DP_INFO(cdev, "Failed to build SKB\n");
180 kfree(buffer->data);
181 goto out_post1;
182 }
183
184 data->u.placement_offset += NET_SKB_PAD;
185 skb_reserve(skb, data->u.placement_offset);
186 skb_put(skb, data->length.packet_length);
187 skb_checksum_none_assert(skb);
188
189 /* Get parital ethernet information instead of eth_type_trans(),
190 * Since we don't have an associated net_device.
191 */
192 skb_reset_mac_header(skb);
193 skb->protocol = eth_hdr(skb)->h_proto;
194
195 /* Pass SKB onward */
196 if (cdev->ll2->cbs && cdev->ll2->cbs->rx_cb) {
197 if (data->vlan)
198 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
199 data->vlan);
200 cdev->ll2->cbs->rx_cb(cdev->ll2->cb_cookie, skb,
201 data->opaque_data_0,
202 data->opaque_data_1);
203 } else {
204 DP_VERBOSE(p_hwfn, (NETIF_MSG_RX_STATUS | NETIF_MSG_PKTDATA |
205 QED_MSG_LL2 | QED_MSG_STORAGE),
206 "Dropping the packet\n");
207 kfree(buffer->data);
208 }
209
210 out_post1:
211 /* Update Buffer information and update FW producer */
212 buffer->data = new_data;
213 buffer->phys_addr = new_phys_addr;
214
215 out_post:
216 rc = qed_ll2_post_rx_buffer(p_hwfn, cdev->ll2->handle,
217 buffer->phys_addr, 0, buffer, 1);
218 if (rc)
219 qed_ll2_dealloc_buffer(cdev, buffer);
220 }
221
__qed_ll2_handle_sanity(struct qed_hwfn * p_hwfn,u8 connection_handle,bool b_lock,bool b_only_active)222 static struct qed_ll2_info *__qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
223 u8 connection_handle,
224 bool b_lock,
225 bool b_only_active)
226 {
227 struct qed_ll2_info *p_ll2_conn, *p_ret = NULL;
228
229 if (connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS)
230 return NULL;
231
232 if (!p_hwfn->p_ll2_info)
233 return NULL;
234
235 p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
236
237 if (b_only_active) {
238 if (b_lock)
239 mutex_lock(&p_ll2_conn->mutex);
240 if (p_ll2_conn->b_active)
241 p_ret = p_ll2_conn;
242 if (b_lock)
243 mutex_unlock(&p_ll2_conn->mutex);
244 } else {
245 p_ret = p_ll2_conn;
246 }
247
248 return p_ret;
249 }
250
qed_ll2_handle_sanity(struct qed_hwfn * p_hwfn,u8 connection_handle)251 static struct qed_ll2_info *qed_ll2_handle_sanity(struct qed_hwfn *p_hwfn,
252 u8 connection_handle)
253 {
254 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, true);
255 }
256
qed_ll2_handle_sanity_lock(struct qed_hwfn * p_hwfn,u8 connection_handle)257 static struct qed_ll2_info *qed_ll2_handle_sanity_lock(struct qed_hwfn *p_hwfn,
258 u8 connection_handle)
259 {
260 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, true, true);
261 }
262
qed_ll2_handle_sanity_inactive(struct qed_hwfn * p_hwfn,u8 connection_handle)263 static struct qed_ll2_info *qed_ll2_handle_sanity_inactive(struct qed_hwfn
264 *p_hwfn,
265 u8 connection_handle)
266 {
267 return __qed_ll2_handle_sanity(p_hwfn, connection_handle, false, false);
268 }
269
qed_ll2_txq_flush(struct qed_hwfn * p_hwfn,u8 connection_handle)270 static void qed_ll2_txq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
271 {
272 bool b_last_packet = false, b_last_frag = false;
273 struct qed_ll2_tx_packet *p_pkt = NULL;
274 struct qed_ll2_info *p_ll2_conn;
275 struct qed_ll2_tx_queue *p_tx;
276 unsigned long flags = 0;
277 dma_addr_t tx_frag;
278
279 p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
280 if (!p_ll2_conn)
281 return;
282
283 p_tx = &p_ll2_conn->tx_queue;
284
285 spin_lock_irqsave(&p_tx->lock, flags);
286 while (!list_empty(&p_tx->active_descq)) {
287 p_pkt = list_first_entry(&p_tx->active_descq,
288 struct qed_ll2_tx_packet, list_entry);
289 if (!p_pkt)
290 break;
291
292 list_del(&p_pkt->list_entry);
293 b_last_packet = list_empty(&p_tx->active_descq);
294 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
295 spin_unlock_irqrestore(&p_tx->lock, flags);
296 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO) {
297 struct qed_ooo_buffer *p_buffer;
298
299 p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
300 qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
301 p_buffer);
302 } else {
303 p_tx->cur_completing_packet = *p_pkt;
304 p_tx->cur_completing_bd_idx = 1;
305 b_last_frag =
306 p_tx->cur_completing_bd_idx == p_pkt->bd_used;
307 tx_frag = p_pkt->bds_set[0].tx_frag;
308 p_ll2_conn->cbs.tx_release_cb(p_ll2_conn->cbs.cookie,
309 p_ll2_conn->my_id,
310 p_pkt->cookie,
311 tx_frag,
312 b_last_frag,
313 b_last_packet);
314 }
315 spin_lock_irqsave(&p_tx->lock, flags);
316 }
317 spin_unlock_irqrestore(&p_tx->lock, flags);
318 }
319
qed_ll2_txq_completion(struct qed_hwfn * p_hwfn,void * p_cookie)320 static int qed_ll2_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
321 {
322 struct qed_ll2_info *p_ll2_conn = p_cookie;
323 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
324 u16 new_idx = 0, num_bds = 0, num_bds_in_packet = 0;
325 struct qed_ll2_tx_packet *p_pkt;
326 bool b_last_frag = false;
327 unsigned long flags;
328 int rc = -EINVAL;
329
330 if (!p_ll2_conn)
331 return rc;
332
333 spin_lock_irqsave(&p_tx->lock, flags);
334 if (p_tx->b_completing_packet) {
335 rc = -EBUSY;
336 goto out;
337 }
338
339 new_idx = le16_to_cpu(*p_tx->p_fw_cons);
340 num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
341 while (num_bds) {
342 if (list_empty(&p_tx->active_descq))
343 goto out;
344
345 p_pkt = list_first_entry(&p_tx->active_descq,
346 struct qed_ll2_tx_packet, list_entry);
347 if (!p_pkt)
348 goto out;
349
350 p_tx->b_completing_packet = true;
351 p_tx->cur_completing_packet = *p_pkt;
352 num_bds_in_packet = p_pkt->bd_used;
353 list_del(&p_pkt->list_entry);
354
355 if (num_bds < num_bds_in_packet) {
356 DP_NOTICE(p_hwfn,
357 "Rest of BDs does not cover whole packet\n");
358 goto out;
359 }
360
361 num_bds -= num_bds_in_packet;
362 p_tx->bds_idx += num_bds_in_packet;
363 while (num_bds_in_packet--)
364 qed_chain_consume(&p_tx->txq_chain);
365
366 p_tx->cur_completing_bd_idx = 1;
367 b_last_frag = p_tx->cur_completing_bd_idx == p_pkt->bd_used;
368 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
369
370 spin_unlock_irqrestore(&p_tx->lock, flags);
371
372 p_ll2_conn->cbs.tx_comp_cb(p_ll2_conn->cbs.cookie,
373 p_ll2_conn->my_id,
374 p_pkt->cookie,
375 p_pkt->bds_set[0].tx_frag,
376 b_last_frag, !num_bds);
377
378 spin_lock_irqsave(&p_tx->lock, flags);
379 }
380
381 p_tx->b_completing_packet = false;
382 rc = 0;
383 out:
384 spin_unlock_irqrestore(&p_tx->lock, flags);
385 return rc;
386 }
387
qed_ll2_rxq_parse_gsi(struct qed_hwfn * p_hwfn,union core_rx_cqe_union * p_cqe,struct qed_ll2_comp_rx_data * data)388 static void qed_ll2_rxq_parse_gsi(struct qed_hwfn *p_hwfn,
389 union core_rx_cqe_union *p_cqe,
390 struct qed_ll2_comp_rx_data *data)
391 {
392 data->parse_flags = le16_to_cpu(p_cqe->rx_cqe_gsi.parse_flags.flags);
393 data->length.data_length = le16_to_cpu(p_cqe->rx_cqe_gsi.data_length);
394 data->vlan = le16_to_cpu(p_cqe->rx_cqe_gsi.vlan);
395 data->opaque_data_0 = le32_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrhi);
396 data->opaque_data_1 = le16_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrlo);
397 data->u.data_length_error = p_cqe->rx_cqe_gsi.data_length_error;
398 data->qp_id = le16_to_cpu(p_cqe->rx_cqe_gsi.qp_id);
399
400 data->src_qp = le32_to_cpu(p_cqe->rx_cqe_gsi.src_qp);
401 }
402
qed_ll2_rxq_parse_reg(struct qed_hwfn * p_hwfn,union core_rx_cqe_union * p_cqe,struct qed_ll2_comp_rx_data * data)403 static void qed_ll2_rxq_parse_reg(struct qed_hwfn *p_hwfn,
404 union core_rx_cqe_union *p_cqe,
405 struct qed_ll2_comp_rx_data *data)
406 {
407 data->parse_flags = le16_to_cpu(p_cqe->rx_cqe_fp.parse_flags.flags);
408 data->err_flags = le16_to_cpu(p_cqe->rx_cqe_fp.err_flags.flags);
409 data->length.packet_length =
410 le16_to_cpu(p_cqe->rx_cqe_fp.packet_length);
411 data->vlan = le16_to_cpu(p_cqe->rx_cqe_fp.vlan);
412 data->opaque_data_0 = le32_to_cpu(p_cqe->rx_cqe_fp.opaque_data.data[0]);
413 data->opaque_data_1 = le32_to_cpu(p_cqe->rx_cqe_fp.opaque_data.data[1]);
414 data->u.placement_offset = p_cqe->rx_cqe_fp.placement_offset;
415 }
416
417 static int
qed_ll2_handle_slowpath(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn,union core_rx_cqe_union * p_cqe,unsigned long * p_lock_flags)418 qed_ll2_handle_slowpath(struct qed_hwfn *p_hwfn,
419 struct qed_ll2_info *p_ll2_conn,
420 union core_rx_cqe_union *p_cqe,
421 unsigned long *p_lock_flags)
422 {
423 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
424 struct core_rx_slow_path_cqe *sp_cqe;
425
426 sp_cqe = &p_cqe->rx_cqe_sp;
427 if (sp_cqe->ramrod_cmd_id != CORE_RAMROD_RX_QUEUE_FLUSH) {
428 DP_NOTICE(p_hwfn,
429 "LL2 - unexpected Rx CQE slowpath ramrod_cmd_id:%d\n",
430 sp_cqe->ramrod_cmd_id);
431 return -EINVAL;
432 }
433
434 if (!p_ll2_conn->cbs.slowpath_cb) {
435 DP_NOTICE(p_hwfn,
436 "LL2 - received RX_QUEUE_FLUSH but no callback was provided\n");
437 return -EINVAL;
438 }
439
440 spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
441
442 p_ll2_conn->cbs.slowpath_cb(p_ll2_conn->cbs.cookie,
443 p_ll2_conn->my_id,
444 le32_to_cpu(sp_cqe->opaque_data.data[0]),
445 le32_to_cpu(sp_cqe->opaque_data.data[1]));
446
447 spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
448
449 return 0;
450 }
451
452 static int
qed_ll2_rxq_handle_completion(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn,union core_rx_cqe_union * p_cqe,unsigned long * p_lock_flags,bool b_last_cqe)453 qed_ll2_rxq_handle_completion(struct qed_hwfn *p_hwfn,
454 struct qed_ll2_info *p_ll2_conn,
455 union core_rx_cqe_union *p_cqe,
456 unsigned long *p_lock_flags, bool b_last_cqe)
457 {
458 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
459 struct qed_ll2_rx_packet *p_pkt = NULL;
460 struct qed_ll2_comp_rx_data data;
461
462 if (!list_empty(&p_rx->active_descq))
463 p_pkt = list_first_entry(&p_rx->active_descq,
464 struct qed_ll2_rx_packet, list_entry);
465 if (!p_pkt) {
466 DP_NOTICE(p_hwfn,
467 "[%d] LL2 Rx completion but active_descq is empty\n",
468 p_ll2_conn->input.conn_type);
469
470 return -EIO;
471 }
472 list_del(&p_pkt->list_entry);
473
474 if (p_cqe->rx_cqe_sp.type == CORE_RX_CQE_TYPE_REGULAR)
475 qed_ll2_rxq_parse_reg(p_hwfn, p_cqe, &data);
476 else
477 qed_ll2_rxq_parse_gsi(p_hwfn, p_cqe, &data);
478 if (qed_chain_consume(&p_rx->rxq_chain) != p_pkt->rxq_bd)
479 DP_NOTICE(p_hwfn,
480 "Mismatch between active_descq and the LL2 Rx chain\n");
481
482 list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
483
484 data.connection_handle = p_ll2_conn->my_id;
485 data.cookie = p_pkt->cookie;
486 data.rx_buf_addr = p_pkt->rx_buf_addr;
487 data.b_last_packet = b_last_cqe;
488
489 spin_unlock_irqrestore(&p_rx->lock, *p_lock_flags);
490 p_ll2_conn->cbs.rx_comp_cb(p_ll2_conn->cbs.cookie, &data);
491
492 spin_lock_irqsave(&p_rx->lock, *p_lock_flags);
493
494 return 0;
495 }
496
qed_ll2_rxq_completion(struct qed_hwfn * p_hwfn,void * cookie)497 static int qed_ll2_rxq_completion(struct qed_hwfn *p_hwfn, void *cookie)
498 {
499 struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)cookie;
500 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
501 union core_rx_cqe_union *cqe = NULL;
502 u16 cq_new_idx = 0, cq_old_idx = 0;
503 unsigned long flags = 0;
504 int rc = 0;
505
506 if (!p_ll2_conn)
507 return rc;
508
509 spin_lock_irqsave(&p_rx->lock, flags);
510
511 if (!QED_LL2_RX_REGISTERED(p_ll2_conn)) {
512 spin_unlock_irqrestore(&p_rx->lock, flags);
513 return 0;
514 }
515
516 cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
517 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
518
519 while (cq_new_idx != cq_old_idx) {
520 bool b_last_cqe = (cq_new_idx == cq_old_idx);
521
522 cqe =
523 (union core_rx_cqe_union *)
524 qed_chain_consume(&p_rx->rcq_chain);
525 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
526
527 DP_VERBOSE(p_hwfn,
528 QED_MSG_LL2,
529 "LL2 [sw. cons %04x, fw. at %04x] - Got Packet of type %02x\n",
530 cq_old_idx, cq_new_idx, cqe->rx_cqe_sp.type);
531
532 switch (cqe->rx_cqe_sp.type) {
533 case CORE_RX_CQE_TYPE_SLOW_PATH:
534 rc = qed_ll2_handle_slowpath(p_hwfn, p_ll2_conn,
535 cqe, &flags);
536 break;
537 case CORE_RX_CQE_TYPE_GSI_OFFLOAD:
538 case CORE_RX_CQE_TYPE_REGULAR:
539 rc = qed_ll2_rxq_handle_completion(p_hwfn, p_ll2_conn,
540 cqe, &flags,
541 b_last_cqe);
542 break;
543 default:
544 rc = -EIO;
545 }
546 }
547
548 spin_unlock_irqrestore(&p_rx->lock, flags);
549 return rc;
550 }
551
qed_ll2_rxq_flush(struct qed_hwfn * p_hwfn,u8 connection_handle)552 static void qed_ll2_rxq_flush(struct qed_hwfn *p_hwfn, u8 connection_handle)
553 {
554 struct qed_ll2_info *p_ll2_conn = NULL;
555 struct qed_ll2_rx_packet *p_pkt = NULL;
556 struct qed_ll2_rx_queue *p_rx;
557 unsigned long flags = 0;
558
559 p_ll2_conn = qed_ll2_handle_sanity_inactive(p_hwfn, connection_handle);
560 if (!p_ll2_conn)
561 return;
562
563 p_rx = &p_ll2_conn->rx_queue;
564
565 spin_lock_irqsave(&p_rx->lock, flags);
566 while (!list_empty(&p_rx->active_descq)) {
567 p_pkt = list_first_entry(&p_rx->active_descq,
568 struct qed_ll2_rx_packet, list_entry);
569 if (!p_pkt)
570 break;
571 list_move_tail(&p_pkt->list_entry, &p_rx->free_descq);
572 spin_unlock_irqrestore(&p_rx->lock, flags);
573
574 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO) {
575 struct qed_ooo_buffer *p_buffer;
576
577 p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
578 qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
579 p_buffer);
580 } else {
581 dma_addr_t rx_buf_addr = p_pkt->rx_buf_addr;
582 void *cookie = p_pkt->cookie;
583 bool b_last;
584
585 b_last = list_empty(&p_rx->active_descq);
586 p_ll2_conn->cbs.rx_release_cb(p_ll2_conn->cbs.cookie,
587 p_ll2_conn->my_id,
588 cookie,
589 rx_buf_addr, b_last);
590 }
591 spin_lock_irqsave(&p_rx->lock, flags);
592 }
593 spin_unlock_irqrestore(&p_rx->lock, flags);
594 }
595
596 static bool
qed_ll2_lb_rxq_handler_slowpath(struct qed_hwfn * p_hwfn,struct core_rx_slow_path_cqe * p_cqe)597 qed_ll2_lb_rxq_handler_slowpath(struct qed_hwfn *p_hwfn,
598 struct core_rx_slow_path_cqe *p_cqe)
599 {
600 struct ooo_opaque *iscsi_ooo;
601 u32 cid;
602
603 if (p_cqe->ramrod_cmd_id != CORE_RAMROD_RX_QUEUE_FLUSH)
604 return false;
605
606 iscsi_ooo = (struct ooo_opaque *)&p_cqe->opaque_data;
607 if (iscsi_ooo->ooo_opcode != TCP_EVENT_DELETE_ISLES)
608 return false;
609
610 /* Need to make a flush */
611 cid = le32_to_cpu(iscsi_ooo->cid);
612 qed_ooo_release_connection_isles(p_hwfn, p_hwfn->p_ooo_info, cid);
613
614 return true;
615 }
616
qed_ll2_lb_rxq_handler(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)617 static int qed_ll2_lb_rxq_handler(struct qed_hwfn *p_hwfn,
618 struct qed_ll2_info *p_ll2_conn)
619 {
620 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
621 u16 packet_length = 0, parse_flags = 0, vlan = 0;
622 struct qed_ll2_rx_packet *p_pkt = NULL;
623 u32 num_ooo_add_to_peninsula = 0, cid;
624 union core_rx_cqe_union *cqe = NULL;
625 u16 cq_new_idx = 0, cq_old_idx = 0;
626 struct qed_ooo_buffer *p_buffer;
627 struct ooo_opaque *iscsi_ooo;
628 u8 placement_offset = 0;
629 u8 cqe_type;
630
631 cq_new_idx = le16_to_cpu(*p_rx->p_fw_cons);
632 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
633 if (cq_new_idx == cq_old_idx)
634 return 0;
635
636 while (cq_new_idx != cq_old_idx) {
637 struct core_rx_fast_path_cqe *p_cqe_fp;
638
639 cqe = qed_chain_consume(&p_rx->rcq_chain);
640 cq_old_idx = qed_chain_get_cons_idx(&p_rx->rcq_chain);
641 cqe_type = cqe->rx_cqe_sp.type;
642
643 if (cqe_type == CORE_RX_CQE_TYPE_SLOW_PATH)
644 if (qed_ll2_lb_rxq_handler_slowpath(p_hwfn,
645 &cqe->rx_cqe_sp))
646 continue;
647
648 if (cqe_type != CORE_RX_CQE_TYPE_REGULAR) {
649 DP_NOTICE(p_hwfn,
650 "Got a non-regular LB LL2 completion [type 0x%02x]\n",
651 cqe_type);
652 return -EINVAL;
653 }
654 p_cqe_fp = &cqe->rx_cqe_fp;
655
656 placement_offset = p_cqe_fp->placement_offset;
657 parse_flags = le16_to_cpu(p_cqe_fp->parse_flags.flags);
658 packet_length = le16_to_cpu(p_cqe_fp->packet_length);
659 vlan = le16_to_cpu(p_cqe_fp->vlan);
660 iscsi_ooo = (struct ooo_opaque *)&p_cqe_fp->opaque_data;
661 qed_ooo_save_history_entry(p_hwfn, p_hwfn->p_ooo_info,
662 iscsi_ooo);
663 cid = le32_to_cpu(iscsi_ooo->cid);
664
665 /* Process delete isle first */
666 if (iscsi_ooo->drop_size)
667 qed_ooo_delete_isles(p_hwfn, p_hwfn->p_ooo_info, cid,
668 iscsi_ooo->drop_isle,
669 iscsi_ooo->drop_size);
670
671 if (iscsi_ooo->ooo_opcode == TCP_EVENT_NOP)
672 continue;
673
674 /* Now process create/add/join isles */
675 if (list_empty(&p_rx->active_descq)) {
676 DP_NOTICE(p_hwfn,
677 "LL2 OOO RX chain has no submitted buffers\n"
678 );
679 return -EIO;
680 }
681
682 p_pkt = list_first_entry(&p_rx->active_descq,
683 struct qed_ll2_rx_packet, list_entry);
684
685 if ((iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_NEW_ISLE) ||
686 (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_RIGHT) ||
687 (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_ISLE_LEFT) ||
688 (iscsi_ooo->ooo_opcode == TCP_EVENT_ADD_PEN) ||
689 (iscsi_ooo->ooo_opcode == TCP_EVENT_JOIN)) {
690 if (!p_pkt) {
691 DP_NOTICE(p_hwfn,
692 "LL2 OOO RX packet is not valid\n");
693 return -EIO;
694 }
695 list_del(&p_pkt->list_entry);
696 p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
697 p_buffer->packet_length = packet_length;
698 p_buffer->parse_flags = parse_flags;
699 p_buffer->vlan = vlan;
700 p_buffer->placement_offset = placement_offset;
701 qed_chain_consume(&p_rx->rxq_chain);
702 list_add_tail(&p_pkt->list_entry, &p_rx->free_descq);
703
704 switch (iscsi_ooo->ooo_opcode) {
705 case TCP_EVENT_ADD_NEW_ISLE:
706 qed_ooo_add_new_isle(p_hwfn,
707 p_hwfn->p_ooo_info,
708 cid,
709 iscsi_ooo->ooo_isle,
710 p_buffer);
711 break;
712 case TCP_EVENT_ADD_ISLE_RIGHT:
713 qed_ooo_add_new_buffer(p_hwfn,
714 p_hwfn->p_ooo_info,
715 cid,
716 iscsi_ooo->ooo_isle,
717 p_buffer,
718 QED_OOO_RIGHT_BUF);
719 break;
720 case TCP_EVENT_ADD_ISLE_LEFT:
721 qed_ooo_add_new_buffer(p_hwfn,
722 p_hwfn->p_ooo_info,
723 cid,
724 iscsi_ooo->ooo_isle,
725 p_buffer,
726 QED_OOO_LEFT_BUF);
727 break;
728 case TCP_EVENT_JOIN:
729 qed_ooo_add_new_buffer(p_hwfn,
730 p_hwfn->p_ooo_info,
731 cid,
732 iscsi_ooo->ooo_isle +
733 1,
734 p_buffer,
735 QED_OOO_LEFT_BUF);
736 qed_ooo_join_isles(p_hwfn,
737 p_hwfn->p_ooo_info,
738 cid, iscsi_ooo->ooo_isle);
739 break;
740 case TCP_EVENT_ADD_PEN:
741 num_ooo_add_to_peninsula++;
742 qed_ooo_put_ready_buffer(p_hwfn,
743 p_hwfn->p_ooo_info,
744 p_buffer, true);
745 break;
746 }
747 } else {
748 DP_NOTICE(p_hwfn,
749 "Unexpected event (%d) TX OOO completion\n",
750 iscsi_ooo->ooo_opcode);
751 }
752 }
753
754 return 0;
755 }
756
757 static void
qed_ooo_submit_tx_buffers(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)758 qed_ooo_submit_tx_buffers(struct qed_hwfn *p_hwfn,
759 struct qed_ll2_info *p_ll2_conn)
760 {
761 struct qed_ll2_tx_pkt_info tx_pkt;
762 struct qed_ooo_buffer *p_buffer;
763 u16 l4_hdr_offset_w;
764 dma_addr_t first_frag;
765 u8 bd_flags;
766 int rc;
767
768 /* Submit Tx buffers here */
769 while ((p_buffer = qed_ooo_get_ready_buffer(p_hwfn,
770 p_hwfn->p_ooo_info))) {
771 l4_hdr_offset_w = 0;
772 bd_flags = 0;
773
774 first_frag = p_buffer->rx_buffer_phys_addr +
775 p_buffer->placement_offset;
776 SET_FIELD(bd_flags, CORE_TX_BD_DATA_FORCE_VLAN_MODE, 1);
777 SET_FIELD(bd_flags, CORE_TX_BD_DATA_L4_PROTOCOL, 1);
778
779 memset(&tx_pkt, 0, sizeof(tx_pkt));
780 tx_pkt.num_of_bds = 1;
781 tx_pkt.vlan = p_buffer->vlan;
782 tx_pkt.bd_flags = bd_flags;
783 tx_pkt.l4_hdr_offset_w = l4_hdr_offset_w;
784 switch (p_ll2_conn->tx_dest) {
785 case CORE_TX_DEST_NW:
786 tx_pkt.tx_dest = QED_LL2_TX_DEST_NW;
787 break;
788 case CORE_TX_DEST_LB:
789 tx_pkt.tx_dest = QED_LL2_TX_DEST_LB;
790 break;
791 case CORE_TX_DEST_DROP:
792 default:
793 tx_pkt.tx_dest = QED_LL2_TX_DEST_DROP;
794 break;
795 }
796 tx_pkt.first_frag = first_frag;
797 tx_pkt.first_frag_len = p_buffer->packet_length;
798 tx_pkt.cookie = p_buffer;
799
800 rc = qed_ll2_prepare_tx_packet(p_hwfn, p_ll2_conn->my_id,
801 &tx_pkt, true);
802 if (rc) {
803 qed_ooo_put_ready_buffer(p_hwfn, p_hwfn->p_ooo_info,
804 p_buffer, false);
805 break;
806 }
807 }
808 }
809
810 static void
qed_ooo_submit_rx_buffers(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)811 qed_ooo_submit_rx_buffers(struct qed_hwfn *p_hwfn,
812 struct qed_ll2_info *p_ll2_conn)
813 {
814 struct qed_ooo_buffer *p_buffer;
815 int rc;
816
817 while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
818 p_hwfn->p_ooo_info))) {
819 rc = qed_ll2_post_rx_buffer(p_hwfn,
820 p_ll2_conn->my_id,
821 p_buffer->rx_buffer_phys_addr,
822 0, p_buffer, true);
823 if (rc) {
824 qed_ooo_put_free_buffer(p_hwfn,
825 p_hwfn->p_ooo_info, p_buffer);
826 break;
827 }
828 }
829 }
830
qed_ll2_lb_rxq_completion(struct qed_hwfn * p_hwfn,void * p_cookie)831 static int qed_ll2_lb_rxq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
832 {
833 struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
834 int rc;
835
836 if (!p_ll2_conn)
837 return 0;
838
839 if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
840 return 0;
841
842 rc = qed_ll2_lb_rxq_handler(p_hwfn, p_ll2_conn);
843 if (rc)
844 return rc;
845
846 qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
847 qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
848
849 return 0;
850 }
851
qed_ll2_lb_txq_completion(struct qed_hwfn * p_hwfn,void * p_cookie)852 static int qed_ll2_lb_txq_completion(struct qed_hwfn *p_hwfn, void *p_cookie)
853 {
854 struct qed_ll2_info *p_ll2_conn = (struct qed_ll2_info *)p_cookie;
855 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
856 struct qed_ll2_tx_packet *p_pkt = NULL;
857 struct qed_ooo_buffer *p_buffer;
858 bool b_dont_submit_rx = false;
859 u16 new_idx = 0, num_bds = 0;
860 int rc;
861
862 if (!p_ll2_conn)
863 return 0;
864
865 if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
866 return 0;
867
868 new_idx = le16_to_cpu(*p_tx->p_fw_cons);
869 num_bds = ((s16)new_idx - (s16)p_tx->bds_idx);
870
871 if (!num_bds)
872 return 0;
873
874 while (num_bds) {
875 if (list_empty(&p_tx->active_descq))
876 return -EINVAL;
877
878 p_pkt = list_first_entry(&p_tx->active_descq,
879 struct qed_ll2_tx_packet, list_entry);
880 if (!p_pkt)
881 return -EINVAL;
882
883 if (p_pkt->bd_used != 1) {
884 DP_NOTICE(p_hwfn,
885 "Unexpectedly many BDs(%d) in TX OOO completion\n",
886 p_pkt->bd_used);
887 return -EINVAL;
888 }
889
890 list_del(&p_pkt->list_entry);
891
892 num_bds--;
893 p_tx->bds_idx++;
894 qed_chain_consume(&p_tx->txq_chain);
895
896 p_buffer = (struct qed_ooo_buffer *)p_pkt->cookie;
897 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
898
899 if (b_dont_submit_rx) {
900 qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info,
901 p_buffer);
902 continue;
903 }
904
905 rc = qed_ll2_post_rx_buffer(p_hwfn, p_ll2_conn->my_id,
906 p_buffer->rx_buffer_phys_addr, 0,
907 p_buffer, true);
908 if (rc != 0) {
909 qed_ooo_put_free_buffer(p_hwfn,
910 p_hwfn->p_ooo_info, p_buffer);
911 b_dont_submit_rx = true;
912 }
913 }
914
915 qed_ooo_submit_tx_buffers(p_hwfn, p_ll2_conn);
916
917 return 0;
918 }
919
qed_ll2_stop_ooo(struct qed_hwfn * p_hwfn)920 static void qed_ll2_stop_ooo(struct qed_hwfn *p_hwfn)
921 {
922 u8 *handle = &p_hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
923
924 DP_VERBOSE(p_hwfn, (QED_MSG_STORAGE | QED_MSG_LL2),
925 "Stopping LL2 OOO queue [%02x]\n", *handle);
926
927 qed_ll2_terminate_connection(p_hwfn, *handle);
928 qed_ll2_release_connection(p_hwfn, *handle);
929 *handle = QED_LL2_UNUSED_HANDLE;
930 }
931
qed_sp_ll2_rx_queue_start(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn,u8 action_on_error)932 static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
933 struct qed_ll2_info *p_ll2_conn,
934 u8 action_on_error)
935 {
936 enum qed_ll2_conn_type conn_type = p_ll2_conn->input.conn_type;
937 struct qed_ll2_rx_queue *p_rx = &p_ll2_conn->rx_queue;
938 struct core_rx_start_ramrod_data *p_ramrod = NULL;
939 struct qed_spq_entry *p_ent = NULL;
940 struct qed_sp_init_data init_data;
941 u16 cqe_pbl_size;
942 int rc = 0;
943
944 /* Get SPQ entry */
945 memset(&init_data, 0, sizeof(init_data));
946 init_data.cid = p_ll2_conn->cid;
947 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
948 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
949
950 rc = qed_sp_init_request(p_hwfn, &p_ent,
951 CORE_RAMROD_RX_QUEUE_START,
952 PROTOCOLID_CORE, &init_data);
953 if (rc)
954 return rc;
955
956 p_ramrod = &p_ent->ramrod.core_rx_queue_start;
957 memset(p_ramrod, 0, sizeof(*p_ramrod));
958 p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
959 p_ramrod->sb_index = p_rx->rx_sb_index;
960 p_ramrod->complete_event_flg = 1;
961
962 p_ramrod->mtu = cpu_to_le16(p_ll2_conn->input.mtu);
963 DMA_REGPAIR_LE(p_ramrod->bd_base, p_rx->rxq_chain.p_phys_addr);
964 cqe_pbl_size = (u16)qed_chain_get_page_cnt(&p_rx->rcq_chain);
965 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
966 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr,
967 qed_chain_get_pbl_phys(&p_rx->rcq_chain));
968
969 p_ramrod->drop_ttl0_flg = p_ll2_conn->input.rx_drop_ttl0_flg;
970 p_ramrod->inner_vlan_stripping_en =
971 p_ll2_conn->input.rx_vlan_removal_en;
972
973 if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) &&
974 p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE)
975 p_ramrod->report_outer_vlan = 1;
976 p_ramrod->queue_id = p_ll2_conn->queue_id;
977 p_ramrod->main_func_queue = p_ll2_conn->main_func_queue ? 1 : 0;
978
979 if (test_bit(QED_MF_LL2_NON_UNICAST, &p_hwfn->cdev->mf_bits) &&
980 p_ramrod->main_func_queue && conn_type != QED_LL2_TYPE_ROCE &&
981 conn_type != QED_LL2_TYPE_IWARP) {
982 p_ramrod->mf_si_bcast_accept_all = 1;
983 p_ramrod->mf_si_mcast_accept_all = 1;
984 } else {
985 p_ramrod->mf_si_bcast_accept_all = 0;
986 p_ramrod->mf_si_mcast_accept_all = 0;
987 }
988
989 p_ramrod->action_on_error.error_type = action_on_error;
990 p_ramrod->gsi_offload_flag = p_ll2_conn->input.gsi_enable;
991 p_ramrod->zero_prod_flg = 1;
992
993 return qed_spq_post(p_hwfn, p_ent, NULL);
994 }
995
qed_sp_ll2_tx_queue_start(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)996 static int qed_sp_ll2_tx_queue_start(struct qed_hwfn *p_hwfn,
997 struct qed_ll2_info *p_ll2_conn)
998 {
999 enum qed_ll2_conn_type conn_type = p_ll2_conn->input.conn_type;
1000 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
1001 struct core_tx_start_ramrod_data *p_ramrod = NULL;
1002 struct qed_spq_entry *p_ent = NULL;
1003 struct qed_sp_init_data init_data;
1004 u16 pq_id = 0, pbl_size;
1005 int rc = -EINVAL;
1006
1007 if (!QED_LL2_TX_REGISTERED(p_ll2_conn))
1008 return 0;
1009
1010 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO)
1011 p_ll2_conn->tx_stats_en = 0;
1012 else
1013 p_ll2_conn->tx_stats_en = 1;
1014
1015 /* Get SPQ entry */
1016 memset(&init_data, 0, sizeof(init_data));
1017 init_data.cid = p_ll2_conn->cid;
1018 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1019 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1020
1021 rc = qed_sp_init_request(p_hwfn, &p_ent,
1022 CORE_RAMROD_TX_QUEUE_START,
1023 PROTOCOLID_CORE, &init_data);
1024 if (rc)
1025 return rc;
1026
1027 p_ramrod = &p_ent->ramrod.core_tx_queue_start;
1028
1029 p_ramrod->sb_id = cpu_to_le16(qed_int_get_sp_sb_id(p_hwfn));
1030 p_ramrod->sb_index = p_tx->tx_sb_index;
1031 p_ramrod->mtu = cpu_to_le16(p_ll2_conn->input.mtu);
1032 p_ramrod->stats_en = p_ll2_conn->tx_stats_en;
1033 p_ramrod->stats_id = p_ll2_conn->tx_stats_id;
1034
1035 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr,
1036 qed_chain_get_pbl_phys(&p_tx->txq_chain));
1037 pbl_size = qed_chain_get_page_cnt(&p_tx->txq_chain);
1038 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
1039
1040 switch (p_ll2_conn->input.tx_tc) {
1041 case PURE_LB_TC:
1042 pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
1043 break;
1044 case PKT_LB_TC:
1045 pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OOO);
1046 break;
1047 default:
1048 pq_id = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1049 break;
1050 }
1051
1052 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
1053
1054 switch (conn_type) {
1055 case QED_LL2_TYPE_FCOE:
1056 p_ramrod->conn_type = PROTOCOLID_FCOE;
1057 break;
1058 case QED_LL2_TYPE_ISCSI:
1059 p_ramrod->conn_type = PROTOCOLID_ISCSI;
1060 break;
1061 case QED_LL2_TYPE_ROCE:
1062 p_ramrod->conn_type = PROTOCOLID_ROCE;
1063 break;
1064 case QED_LL2_TYPE_IWARP:
1065 p_ramrod->conn_type = PROTOCOLID_IWARP;
1066 break;
1067 case QED_LL2_TYPE_OOO:
1068 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
1069 p_ramrod->conn_type = PROTOCOLID_ISCSI;
1070 else
1071 p_ramrod->conn_type = PROTOCOLID_IWARP;
1072 break;
1073 default:
1074 p_ramrod->conn_type = PROTOCOLID_ETH;
1075 DP_NOTICE(p_hwfn, "Unknown connection type: %d\n", conn_type);
1076 }
1077
1078 p_ramrod->gsi_offload_flag = p_ll2_conn->input.gsi_enable;
1079
1080 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1081 if (rc)
1082 return rc;
1083
1084 rc = qed_db_recovery_add(p_hwfn->cdev, p_tx->doorbell_addr,
1085 &p_tx->db_msg, DB_REC_WIDTH_32B,
1086 DB_REC_KERNEL);
1087 return rc;
1088 }
1089
qed_sp_ll2_rx_queue_stop(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)1090 static int qed_sp_ll2_rx_queue_stop(struct qed_hwfn *p_hwfn,
1091 struct qed_ll2_info *p_ll2_conn)
1092 {
1093 struct core_rx_stop_ramrod_data *p_ramrod = NULL;
1094 struct qed_spq_entry *p_ent = NULL;
1095 struct qed_sp_init_data init_data;
1096 int rc = -EINVAL;
1097
1098 /* Get SPQ entry */
1099 memset(&init_data, 0, sizeof(init_data));
1100 init_data.cid = p_ll2_conn->cid;
1101 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1102 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1103
1104 rc = qed_sp_init_request(p_hwfn, &p_ent,
1105 CORE_RAMROD_RX_QUEUE_STOP,
1106 PROTOCOLID_CORE, &init_data);
1107 if (rc)
1108 return rc;
1109
1110 p_ramrod = &p_ent->ramrod.core_rx_queue_stop;
1111
1112 p_ramrod->complete_event_flg = 1;
1113 p_ramrod->queue_id = p_ll2_conn->queue_id;
1114
1115 return qed_spq_post(p_hwfn, p_ent, NULL);
1116 }
1117
qed_sp_ll2_tx_queue_stop(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)1118 static int qed_sp_ll2_tx_queue_stop(struct qed_hwfn *p_hwfn,
1119 struct qed_ll2_info *p_ll2_conn)
1120 {
1121 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
1122 struct qed_spq_entry *p_ent = NULL;
1123 struct qed_sp_init_data init_data;
1124 int rc = -EINVAL;
1125 qed_db_recovery_del(p_hwfn->cdev, p_tx->doorbell_addr, &p_tx->db_msg);
1126
1127 /* Get SPQ entry */
1128 memset(&init_data, 0, sizeof(init_data));
1129 init_data.cid = p_ll2_conn->cid;
1130 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1131 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1132
1133 rc = qed_sp_init_request(p_hwfn, &p_ent,
1134 CORE_RAMROD_TX_QUEUE_STOP,
1135 PROTOCOLID_CORE, &init_data);
1136 if (rc)
1137 return rc;
1138
1139 return qed_spq_post(p_hwfn, p_ent, NULL);
1140 }
1141
1142 static int
qed_ll2_acquire_connection_rx(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_info)1143 qed_ll2_acquire_connection_rx(struct qed_hwfn *p_hwfn,
1144 struct qed_ll2_info *p_ll2_info)
1145 {
1146 struct qed_chain_init_params params = {
1147 .intended_use = QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1148 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
1149 .num_elems = p_ll2_info->input.rx_num_desc,
1150 };
1151 struct qed_dev *cdev = p_hwfn->cdev;
1152 struct qed_ll2_rx_packet *p_descq;
1153 u32 capacity;
1154 int rc = 0;
1155
1156 if (!p_ll2_info->input.rx_num_desc)
1157 goto out;
1158
1159 params.mode = QED_CHAIN_MODE_NEXT_PTR;
1160 params.elem_size = sizeof(struct core_rx_bd);
1161
1162 rc = qed_chain_alloc(cdev, &p_ll2_info->rx_queue.rxq_chain, ¶ms);
1163 if (rc) {
1164 DP_NOTICE(p_hwfn, "Failed to allocate ll2 rxq chain\n");
1165 goto out;
1166 }
1167
1168 capacity = qed_chain_get_capacity(&p_ll2_info->rx_queue.rxq_chain);
1169 p_descq = kcalloc(capacity, sizeof(struct qed_ll2_rx_packet),
1170 GFP_KERNEL);
1171 if (!p_descq) {
1172 rc = -ENOMEM;
1173 DP_NOTICE(p_hwfn, "Failed to allocate ll2 Rx desc\n");
1174 goto out;
1175 }
1176 p_ll2_info->rx_queue.descq_array = p_descq;
1177
1178 params.mode = QED_CHAIN_MODE_PBL;
1179 params.elem_size = sizeof(struct core_rx_fast_path_cqe);
1180
1181 rc = qed_chain_alloc(cdev, &p_ll2_info->rx_queue.rcq_chain, ¶ms);
1182 if (rc) {
1183 DP_NOTICE(p_hwfn, "Failed to allocate ll2 rcq chain\n");
1184 goto out;
1185 }
1186
1187 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
1188 "Allocated LL2 Rxq [Type %08x] with 0x%08x buffers\n",
1189 p_ll2_info->input.conn_type, p_ll2_info->input.rx_num_desc);
1190
1191 out:
1192 return rc;
1193 }
1194
qed_ll2_acquire_connection_tx(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_info)1195 static int qed_ll2_acquire_connection_tx(struct qed_hwfn *p_hwfn,
1196 struct qed_ll2_info *p_ll2_info)
1197 {
1198 struct qed_chain_init_params params = {
1199 .mode = QED_CHAIN_MODE_PBL,
1200 .intended_use = QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1201 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
1202 .num_elems = p_ll2_info->input.tx_num_desc,
1203 .elem_size = sizeof(struct core_tx_bd),
1204 };
1205 struct qed_ll2_tx_packet *p_descq;
1206 size_t desc_size;
1207 u32 capacity;
1208 int rc = 0;
1209
1210 if (!p_ll2_info->input.tx_num_desc)
1211 goto out;
1212
1213 rc = qed_chain_alloc(p_hwfn->cdev, &p_ll2_info->tx_queue.txq_chain,
1214 ¶ms);
1215 if (rc)
1216 goto out;
1217
1218 capacity = qed_chain_get_capacity(&p_ll2_info->tx_queue.txq_chain);
1219 /* All bds_set elements are flexibily added. */
1220 desc_size = struct_size(p_descq, bds_set,
1221 p_ll2_info->input.tx_max_bds_per_packet);
1222
1223 p_descq = kcalloc(capacity, desc_size, GFP_KERNEL);
1224 if (!p_descq) {
1225 rc = -ENOMEM;
1226 goto out;
1227 }
1228 p_ll2_info->tx_queue.descq_mem = p_descq;
1229
1230 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
1231 "Allocated LL2 Txq [Type %08x] with 0x%08x buffers\n",
1232 p_ll2_info->input.conn_type, p_ll2_info->input.tx_num_desc);
1233
1234 out:
1235 if (rc)
1236 DP_NOTICE(p_hwfn,
1237 "Can't allocate memory for Tx LL2 with 0x%08x buffers\n",
1238 p_ll2_info->input.tx_num_desc);
1239 return rc;
1240 }
1241
1242 static int
qed_ll2_acquire_connection_ooo(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_info,u16 mtu)1243 qed_ll2_acquire_connection_ooo(struct qed_hwfn *p_hwfn,
1244 struct qed_ll2_info *p_ll2_info, u16 mtu)
1245 {
1246 struct qed_ooo_buffer *p_buf = NULL;
1247 void *p_virt;
1248 u16 buf_idx;
1249 int rc = 0;
1250
1251 if (p_ll2_info->input.conn_type != QED_LL2_TYPE_OOO)
1252 return rc;
1253
1254 /* Correct number of requested OOO buffers if needed */
1255 if (!p_ll2_info->input.rx_num_ooo_buffers) {
1256 u16 num_desc = p_ll2_info->input.rx_num_desc;
1257
1258 if (!num_desc)
1259 return -EINVAL;
1260 p_ll2_info->input.rx_num_ooo_buffers = num_desc * 2;
1261 }
1262
1263 for (buf_idx = 0; buf_idx < p_ll2_info->input.rx_num_ooo_buffers;
1264 buf_idx++) {
1265 p_buf = kzalloc(sizeof(*p_buf), GFP_KERNEL);
1266 if (!p_buf) {
1267 rc = -ENOMEM;
1268 goto out;
1269 }
1270
1271 p_buf->rx_buffer_size = mtu + 26 + ETH_CACHE_LINE_SIZE;
1272 p_buf->rx_buffer_size = (p_buf->rx_buffer_size +
1273 ETH_CACHE_LINE_SIZE - 1) &
1274 ~(ETH_CACHE_LINE_SIZE - 1);
1275 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1276 p_buf->rx_buffer_size,
1277 &p_buf->rx_buffer_phys_addr,
1278 GFP_KERNEL);
1279 if (!p_virt) {
1280 kfree(p_buf);
1281 rc = -ENOMEM;
1282 goto out;
1283 }
1284
1285 p_buf->rx_buffer_virt_addr = p_virt;
1286 qed_ooo_put_free_buffer(p_hwfn, p_hwfn->p_ooo_info, p_buf);
1287 }
1288
1289 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
1290 "Allocated [%04x] LL2 OOO buffers [each of size 0x%08x]\n",
1291 p_ll2_info->input.rx_num_ooo_buffers, p_buf->rx_buffer_size);
1292
1293 out:
1294 return rc;
1295 }
1296
1297 static int
qed_ll2_set_cbs(struct qed_ll2_info * p_ll2_info,const struct qed_ll2_cbs * cbs)1298 qed_ll2_set_cbs(struct qed_ll2_info *p_ll2_info, const struct qed_ll2_cbs *cbs)
1299 {
1300 if (!cbs || (!cbs->rx_comp_cb ||
1301 !cbs->rx_release_cb ||
1302 !cbs->tx_comp_cb || !cbs->tx_release_cb || !cbs->cookie))
1303 return -EINVAL;
1304
1305 p_ll2_info->cbs.rx_comp_cb = cbs->rx_comp_cb;
1306 p_ll2_info->cbs.rx_release_cb = cbs->rx_release_cb;
1307 p_ll2_info->cbs.tx_comp_cb = cbs->tx_comp_cb;
1308 p_ll2_info->cbs.tx_release_cb = cbs->tx_release_cb;
1309 p_ll2_info->cbs.slowpath_cb = cbs->slowpath_cb;
1310 p_ll2_info->cbs.cookie = cbs->cookie;
1311
1312 return 0;
1313 }
1314
_qed_ll2_calc_allowed_conns(struct qed_hwfn * p_hwfn,struct qed_ll2_acquire_data * data,u8 * start_idx,u8 * last_idx)1315 static void _qed_ll2_calc_allowed_conns(struct qed_hwfn *p_hwfn,
1316 struct qed_ll2_acquire_data *data,
1317 u8 *start_idx, u8 *last_idx)
1318 {
1319 /* LL2 queues handles will be split as follows:
1320 * First will be the legacy queues, and then the ctx based.
1321 */
1322 if (data->input.rx_conn_type == QED_LL2_RX_TYPE_LEGACY) {
1323 *start_idx = QED_LL2_LEGACY_CONN_BASE_PF;
1324 *last_idx = *start_idx +
1325 QED_MAX_NUM_OF_LEGACY_LL2_CONNS_PF;
1326 } else {
1327 /* QED_LL2_RX_TYPE_CTX */
1328 *start_idx = QED_LL2_CTX_CONN_BASE_PF;
1329 *last_idx = *start_idx +
1330 QED_MAX_NUM_OF_CTX_LL2_CONNS_PF;
1331 }
1332 }
1333
1334 static enum core_error_handle
qed_ll2_get_error_choice(enum qed_ll2_error_handle err)1335 qed_ll2_get_error_choice(enum qed_ll2_error_handle err)
1336 {
1337 switch (err) {
1338 case QED_LL2_DROP_PACKET:
1339 return LL2_DROP_PACKET;
1340 case QED_LL2_DO_NOTHING:
1341 return LL2_DO_NOTHING;
1342 case QED_LL2_ASSERT:
1343 return LL2_ASSERT;
1344 default:
1345 return LL2_DO_NOTHING;
1346 }
1347 }
1348
qed_ll2_acquire_connection(void * cxt,struct qed_ll2_acquire_data * data)1349 int qed_ll2_acquire_connection(void *cxt, struct qed_ll2_acquire_data *data)
1350 {
1351 struct qed_hwfn *p_hwfn = cxt;
1352 qed_int_comp_cb_t comp_rx_cb, comp_tx_cb;
1353 struct qed_ll2_info *p_ll2_info = NULL;
1354 u8 i, first_idx, last_idx, *p_tx_max;
1355 int rc;
1356
1357 if (!data->p_connection_handle || !p_hwfn->p_ll2_info)
1358 return -EINVAL;
1359
1360 _qed_ll2_calc_allowed_conns(p_hwfn, data, &first_idx, &last_idx);
1361
1362 /* Find a free connection to be used */
1363 for (i = first_idx; i < last_idx; i++) {
1364 mutex_lock(&p_hwfn->p_ll2_info[i].mutex);
1365 if (p_hwfn->p_ll2_info[i].b_active) {
1366 mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
1367 continue;
1368 }
1369
1370 p_hwfn->p_ll2_info[i].b_active = true;
1371 p_ll2_info = &p_hwfn->p_ll2_info[i];
1372 mutex_unlock(&p_hwfn->p_ll2_info[i].mutex);
1373 break;
1374 }
1375 if (!p_ll2_info)
1376 return -EBUSY;
1377
1378 memcpy(&p_ll2_info->input, &data->input, sizeof(p_ll2_info->input));
1379
1380 switch (data->input.tx_dest) {
1381 case QED_LL2_TX_DEST_NW:
1382 p_ll2_info->tx_dest = CORE_TX_DEST_NW;
1383 break;
1384 case QED_LL2_TX_DEST_LB:
1385 p_ll2_info->tx_dest = CORE_TX_DEST_LB;
1386 break;
1387 case QED_LL2_TX_DEST_DROP:
1388 p_ll2_info->tx_dest = CORE_TX_DEST_DROP;
1389 break;
1390 default:
1391 return -EINVAL;
1392 }
1393
1394 if (data->input.conn_type == QED_LL2_TYPE_OOO ||
1395 data->input.secondary_queue)
1396 p_ll2_info->main_func_queue = false;
1397 else
1398 p_ll2_info->main_func_queue = true;
1399
1400 /* Correct maximum number of Tx BDs */
1401 p_tx_max = &p_ll2_info->input.tx_max_bds_per_packet;
1402 if (*p_tx_max == 0)
1403 *p_tx_max = CORE_LL2_TX_MAX_BDS_PER_PACKET;
1404 else
1405 *p_tx_max = min_t(u8, *p_tx_max,
1406 CORE_LL2_TX_MAX_BDS_PER_PACKET);
1407
1408 rc = qed_ll2_set_cbs(p_ll2_info, data->cbs);
1409 if (rc) {
1410 DP_NOTICE(p_hwfn, "Invalid callback functions\n");
1411 goto q_allocate_fail;
1412 }
1413
1414 rc = qed_ll2_acquire_connection_rx(p_hwfn, p_ll2_info);
1415 if (rc)
1416 goto q_allocate_fail;
1417
1418 rc = qed_ll2_acquire_connection_tx(p_hwfn, p_ll2_info);
1419 if (rc)
1420 goto q_allocate_fail;
1421
1422 rc = qed_ll2_acquire_connection_ooo(p_hwfn, p_ll2_info,
1423 data->input.mtu);
1424 if (rc)
1425 goto q_allocate_fail;
1426
1427 /* Register callbacks for the Rx/Tx queues */
1428 if (data->input.conn_type == QED_LL2_TYPE_OOO) {
1429 comp_rx_cb = qed_ll2_lb_rxq_completion;
1430 comp_tx_cb = qed_ll2_lb_txq_completion;
1431 } else {
1432 comp_rx_cb = qed_ll2_rxq_completion;
1433 comp_tx_cb = qed_ll2_txq_completion;
1434 }
1435
1436 if (data->input.rx_num_desc) {
1437 qed_int_register_cb(p_hwfn, comp_rx_cb,
1438 &p_hwfn->p_ll2_info[i],
1439 &p_ll2_info->rx_queue.rx_sb_index,
1440 &p_ll2_info->rx_queue.p_fw_cons);
1441 p_ll2_info->rx_queue.b_cb_registered = true;
1442 }
1443
1444 if (data->input.tx_num_desc) {
1445 qed_int_register_cb(p_hwfn,
1446 comp_tx_cb,
1447 &p_hwfn->p_ll2_info[i],
1448 &p_ll2_info->tx_queue.tx_sb_index,
1449 &p_ll2_info->tx_queue.p_fw_cons);
1450 p_ll2_info->tx_queue.b_cb_registered = true;
1451 }
1452
1453 *data->p_connection_handle = i;
1454 return rc;
1455
1456 q_allocate_fail:
1457 qed_ll2_release_connection(p_hwfn, i);
1458 return -ENOMEM;
1459 }
1460
qed_ll2_establish_connection_rx(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)1461 static int qed_ll2_establish_connection_rx(struct qed_hwfn *p_hwfn,
1462 struct qed_ll2_info *p_ll2_conn)
1463 {
1464 enum qed_ll2_error_handle error_input;
1465 enum core_error_handle error_mode;
1466 u8 action_on_error = 0;
1467 int rc;
1468
1469 if (!QED_LL2_RX_REGISTERED(p_ll2_conn))
1470 return 0;
1471
1472 DIRECT_REG_WR(p_ll2_conn->rx_queue.set_prod_addr, 0x0);
1473 error_input = p_ll2_conn->input.ai_err_packet_too_big;
1474 error_mode = qed_ll2_get_error_choice(error_input);
1475 SET_FIELD(action_on_error,
1476 CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG, error_mode);
1477 error_input = p_ll2_conn->input.ai_err_no_buf;
1478 error_mode = qed_ll2_get_error_choice(error_input);
1479 SET_FIELD(action_on_error, CORE_RX_ACTION_ON_ERROR_NO_BUFF, error_mode);
1480
1481 rc = qed_sp_ll2_rx_queue_start(p_hwfn, p_ll2_conn, action_on_error);
1482 if (rc)
1483 return rc;
1484
1485 if (p_ll2_conn->rx_queue.ctx_based) {
1486 rc = qed_db_recovery_add(p_hwfn->cdev,
1487 p_ll2_conn->rx_queue.set_prod_addr,
1488 &p_ll2_conn->rx_queue.db_data,
1489 DB_REC_WIDTH_64B, DB_REC_KERNEL);
1490 }
1491
1492 return rc;
1493 }
1494
1495 static void
qed_ll2_establish_connection_ooo(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)1496 qed_ll2_establish_connection_ooo(struct qed_hwfn *p_hwfn,
1497 struct qed_ll2_info *p_ll2_conn)
1498 {
1499 if (p_ll2_conn->input.conn_type != QED_LL2_TYPE_OOO)
1500 return;
1501
1502 qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
1503 qed_ooo_submit_rx_buffers(p_hwfn, p_ll2_conn);
1504 }
1505
qed_ll2_handle_to_queue_id(struct qed_hwfn * p_hwfn,u8 handle,u8 ll2_queue_type)1506 static inline u8 qed_ll2_handle_to_queue_id(struct qed_hwfn *p_hwfn,
1507 u8 handle,
1508 u8 ll2_queue_type)
1509 {
1510 u8 qid;
1511
1512 if (ll2_queue_type == QED_LL2_RX_TYPE_LEGACY)
1513 return p_hwfn->hw_info.resc_start[QED_LL2_RAM_QUEUE] + handle;
1514
1515 /* QED_LL2_RX_TYPE_CTX
1516 * FW distinguishes between the legacy queues (ram based) and the
1517 * ctx based queues by the queue_id.
1518 * The first MAX_NUM_LL2_RX_RAM_QUEUES queues are legacy
1519 * and the queue ids above that are ctx base.
1520 */
1521 qid = p_hwfn->hw_info.resc_start[QED_LL2_CTX_QUEUE] +
1522 MAX_NUM_LL2_RX_RAM_QUEUES;
1523
1524 /* See comment on the acquire connection for how the ll2
1525 * queues handles are divided.
1526 */
1527 qid += (handle - QED_MAX_NUM_OF_LEGACY_LL2_CONNS_PF);
1528
1529 return qid;
1530 }
1531
qed_ll2_establish_connection(void * cxt,u8 connection_handle)1532 int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
1533 {
1534 struct e4_core_conn_context *p_cxt;
1535 struct qed_ll2_tx_packet *p_pkt;
1536 struct qed_ll2_info *p_ll2_conn;
1537 struct qed_hwfn *p_hwfn = cxt;
1538 struct qed_ll2_rx_queue *p_rx;
1539 struct qed_ll2_tx_queue *p_tx;
1540 struct qed_cxt_info cxt_info;
1541 struct qed_ptt *p_ptt;
1542 int rc = -EINVAL;
1543 u32 i, capacity;
1544 size_t desc_size;
1545 u8 qid;
1546
1547 p_ptt = qed_ptt_acquire(p_hwfn);
1548 if (!p_ptt)
1549 return -EAGAIN;
1550
1551 p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
1552 if (!p_ll2_conn) {
1553 rc = -EINVAL;
1554 goto out;
1555 }
1556
1557 p_rx = &p_ll2_conn->rx_queue;
1558 p_tx = &p_ll2_conn->tx_queue;
1559
1560 qed_chain_reset(&p_rx->rxq_chain);
1561 qed_chain_reset(&p_rx->rcq_chain);
1562 INIT_LIST_HEAD(&p_rx->active_descq);
1563 INIT_LIST_HEAD(&p_rx->free_descq);
1564 INIT_LIST_HEAD(&p_rx->posting_descq);
1565 spin_lock_init(&p_rx->lock);
1566 capacity = qed_chain_get_capacity(&p_rx->rxq_chain);
1567 for (i = 0; i < capacity; i++)
1568 list_add_tail(&p_rx->descq_array[i].list_entry,
1569 &p_rx->free_descq);
1570 *p_rx->p_fw_cons = 0;
1571
1572 qed_chain_reset(&p_tx->txq_chain);
1573 INIT_LIST_HEAD(&p_tx->active_descq);
1574 INIT_LIST_HEAD(&p_tx->free_descq);
1575 INIT_LIST_HEAD(&p_tx->sending_descq);
1576 spin_lock_init(&p_tx->lock);
1577 capacity = qed_chain_get_capacity(&p_tx->txq_chain);
1578 /* All bds_set elements are flexibily added. */
1579 desc_size = struct_size(p_pkt, bds_set,
1580 p_ll2_conn->input.tx_max_bds_per_packet);
1581
1582 for (i = 0; i < capacity; i++) {
1583 p_pkt = p_tx->descq_mem + desc_size * i;
1584 list_add_tail(&p_pkt->list_entry, &p_tx->free_descq);
1585 }
1586 p_tx->cur_completing_bd_idx = 0;
1587 p_tx->bds_idx = 0;
1588 p_tx->b_completing_packet = false;
1589 p_tx->cur_send_packet = NULL;
1590 p_tx->cur_send_frag_num = 0;
1591 p_tx->cur_completing_frag_num = 0;
1592 *p_tx->p_fw_cons = 0;
1593
1594 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_CORE, &p_ll2_conn->cid);
1595 if (rc)
1596 goto out;
1597 cxt_info.iid = p_ll2_conn->cid;
1598 rc = qed_cxt_get_cid_info(p_hwfn, &cxt_info);
1599 if (rc) {
1600 DP_NOTICE(p_hwfn, "Cannot find context info for cid=%d\n",
1601 p_ll2_conn->cid);
1602 goto out;
1603 }
1604
1605 p_cxt = cxt_info.p_cxt;
1606
1607 memset(p_cxt, 0, sizeof(*p_cxt));
1608
1609 qid = qed_ll2_handle_to_queue_id(p_hwfn, connection_handle,
1610 p_ll2_conn->input.rx_conn_type);
1611 p_ll2_conn->queue_id = qid;
1612 p_ll2_conn->tx_stats_id = qid;
1613
1614 DP_VERBOSE(p_hwfn, QED_MSG_LL2,
1615 "Establishing ll2 queue. PF %d ctx_based=%d abs qid=%d\n",
1616 p_hwfn->rel_pf_id, p_ll2_conn->input.rx_conn_type, qid);
1617
1618 if (p_ll2_conn->input.rx_conn_type == QED_LL2_RX_TYPE_LEGACY) {
1619 p_rx->set_prod_addr = p_hwfn->regview +
1620 GTT_BAR0_MAP_REG_TSDM_RAM + TSTORM_LL2_RX_PRODS_OFFSET(qid);
1621 } else {
1622 /* QED_LL2_RX_TYPE_CTX - using doorbell */
1623 p_rx->ctx_based = 1;
1624
1625 p_rx->set_prod_addr = p_hwfn->doorbells +
1626 p_hwfn->dpi_start_offset +
1627 DB_ADDR_SHIFT(DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE);
1628
1629 /* prepare db data */
1630 p_rx->db_data.icid = cpu_to_le16((u16)p_ll2_conn->cid);
1631 SET_FIELD(p_rx->db_data.params,
1632 CORE_PWM_PROD_UPDATE_DATA_AGG_CMD, DB_AGG_CMD_SET);
1633 SET_FIELD(p_rx->db_data.params,
1634 CORE_PWM_PROD_UPDATE_DATA_RESERVED1, 0);
1635 }
1636
1637 p_tx->doorbell_addr = (u8 __iomem *)p_hwfn->doorbells +
1638 qed_db_addr(p_ll2_conn->cid,
1639 DQ_DEMS_LEGACY);
1640 /* prepare db data */
1641 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_DEST, DB_DEST_XCM);
1642 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
1643 SET_FIELD(p_tx->db_msg.params, CORE_DB_DATA_AGG_VAL_SEL,
1644 DQ_XCM_CORE_TX_BD_PROD_CMD);
1645 p_tx->db_msg.agg_flags = DQ_XCM_CORE_DQ_CF_CMD;
1646
1647 rc = qed_ll2_establish_connection_rx(p_hwfn, p_ll2_conn);
1648 if (rc)
1649 goto out;
1650
1651 rc = qed_sp_ll2_tx_queue_start(p_hwfn, p_ll2_conn);
1652 if (rc)
1653 goto out;
1654
1655 if (!QED_IS_RDMA_PERSONALITY(p_hwfn))
1656 qed_wr(p_hwfn, p_ptt, PRS_REG_USE_LIGHT_L2, 1);
1657
1658 qed_ll2_establish_connection_ooo(p_hwfn, p_ll2_conn);
1659
1660 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE) {
1661 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1662 qed_llh_add_protocol_filter(p_hwfn->cdev, 0,
1663 QED_LLH_FILTER_ETHERTYPE,
1664 ETH_P_FCOE, 0);
1665 qed_llh_add_protocol_filter(p_hwfn->cdev, 0,
1666 QED_LLH_FILTER_ETHERTYPE,
1667 ETH_P_FIP, 0);
1668 }
1669
1670 out:
1671 qed_ptt_release(p_hwfn, p_ptt);
1672 return rc;
1673 }
1674
qed_ll2_post_rx_buffer_notify_fw(struct qed_hwfn * p_hwfn,struct qed_ll2_rx_queue * p_rx,struct qed_ll2_rx_packet * p_curp)1675 static void qed_ll2_post_rx_buffer_notify_fw(struct qed_hwfn *p_hwfn,
1676 struct qed_ll2_rx_queue *p_rx,
1677 struct qed_ll2_rx_packet *p_curp)
1678 {
1679 struct qed_ll2_rx_packet *p_posting_packet = NULL;
1680 struct core_ll2_rx_prod rx_prod = { 0, 0 };
1681 bool b_notify_fw = false;
1682 u16 bd_prod, cq_prod;
1683
1684 /* This handles the flushing of already posted buffers */
1685 while (!list_empty(&p_rx->posting_descq)) {
1686 p_posting_packet = list_first_entry(&p_rx->posting_descq,
1687 struct qed_ll2_rx_packet,
1688 list_entry);
1689 list_move_tail(&p_posting_packet->list_entry,
1690 &p_rx->active_descq);
1691 b_notify_fw = true;
1692 }
1693
1694 /* This handles the supplied packet [if there is one] */
1695 if (p_curp) {
1696 list_add_tail(&p_curp->list_entry, &p_rx->active_descq);
1697 b_notify_fw = true;
1698 }
1699
1700 if (!b_notify_fw)
1701 return;
1702
1703 bd_prod = qed_chain_get_prod_idx(&p_rx->rxq_chain);
1704 cq_prod = qed_chain_get_prod_idx(&p_rx->rcq_chain);
1705 if (p_rx->ctx_based) {
1706 /* update producer by giving a doorbell */
1707 p_rx->db_data.prod.bd_prod = cpu_to_le16(bd_prod);
1708 p_rx->db_data.prod.cqe_prod = cpu_to_le16(cq_prod);
1709 /* Make sure chain element is updated before ringing the
1710 * doorbell
1711 */
1712 dma_wmb();
1713 DIRECT_REG_WR64(p_rx->set_prod_addr,
1714 *((u64 *)&p_rx->db_data));
1715 } else {
1716 rx_prod.bd_prod = cpu_to_le16(bd_prod);
1717 rx_prod.cqe_prod = cpu_to_le16(cq_prod);
1718
1719 /* Make sure chain element is updated before ringing the
1720 * doorbell
1721 */
1722 dma_wmb();
1723
1724 DIRECT_REG_WR(p_rx->set_prod_addr, *((u32 *)&rx_prod));
1725 }
1726 }
1727
qed_ll2_post_rx_buffer(void * cxt,u8 connection_handle,dma_addr_t addr,u16 buf_len,void * cookie,u8 notify_fw)1728 int qed_ll2_post_rx_buffer(void *cxt,
1729 u8 connection_handle,
1730 dma_addr_t addr,
1731 u16 buf_len, void *cookie, u8 notify_fw)
1732 {
1733 struct qed_hwfn *p_hwfn = cxt;
1734 struct core_rx_bd_with_buff_len *p_curb = NULL;
1735 struct qed_ll2_rx_packet *p_curp = NULL;
1736 struct qed_ll2_info *p_ll2_conn;
1737 struct qed_ll2_rx_queue *p_rx;
1738 unsigned long flags;
1739 void *p_data;
1740 int rc = 0;
1741
1742 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1743 if (!p_ll2_conn)
1744 return -EINVAL;
1745 p_rx = &p_ll2_conn->rx_queue;
1746 if (!p_rx->set_prod_addr)
1747 return -EIO;
1748
1749 spin_lock_irqsave(&p_rx->lock, flags);
1750 if (!list_empty(&p_rx->free_descq))
1751 p_curp = list_first_entry(&p_rx->free_descq,
1752 struct qed_ll2_rx_packet, list_entry);
1753 if (p_curp) {
1754 if (qed_chain_get_elem_left(&p_rx->rxq_chain) &&
1755 qed_chain_get_elem_left(&p_rx->rcq_chain)) {
1756 p_data = qed_chain_produce(&p_rx->rxq_chain);
1757 p_curb = (struct core_rx_bd_with_buff_len *)p_data;
1758 qed_chain_produce(&p_rx->rcq_chain);
1759 }
1760 }
1761
1762 /* If we're lacking entires, let's try to flush buffers to FW */
1763 if (!p_curp || !p_curb) {
1764 rc = -EBUSY;
1765 p_curp = NULL;
1766 goto out_notify;
1767 }
1768
1769 /* We have an Rx packet we can fill */
1770 DMA_REGPAIR_LE(p_curb->addr, addr);
1771 p_curb->buff_length = cpu_to_le16(buf_len);
1772 p_curp->rx_buf_addr = addr;
1773 p_curp->cookie = cookie;
1774 p_curp->rxq_bd = p_curb;
1775 p_curp->buf_length = buf_len;
1776 list_del(&p_curp->list_entry);
1777
1778 /* Check if we only want to enqueue this packet without informing FW */
1779 if (!notify_fw) {
1780 list_add_tail(&p_curp->list_entry, &p_rx->posting_descq);
1781 goto out;
1782 }
1783
1784 out_notify:
1785 qed_ll2_post_rx_buffer_notify_fw(p_hwfn, p_rx, p_curp);
1786 out:
1787 spin_unlock_irqrestore(&p_rx->lock, flags);
1788 return rc;
1789 }
1790
qed_ll2_prepare_tx_packet_set(struct qed_hwfn * p_hwfn,struct qed_ll2_tx_queue * p_tx,struct qed_ll2_tx_packet * p_curp,struct qed_ll2_tx_pkt_info * pkt,u8 notify_fw)1791 static void qed_ll2_prepare_tx_packet_set(struct qed_hwfn *p_hwfn,
1792 struct qed_ll2_tx_queue *p_tx,
1793 struct qed_ll2_tx_packet *p_curp,
1794 struct qed_ll2_tx_pkt_info *pkt,
1795 u8 notify_fw)
1796 {
1797 list_del(&p_curp->list_entry);
1798 p_curp->cookie = pkt->cookie;
1799 p_curp->bd_used = pkt->num_of_bds;
1800 p_curp->notify_fw = notify_fw;
1801 p_tx->cur_send_packet = p_curp;
1802 p_tx->cur_send_frag_num = 0;
1803
1804 p_curp->bds_set[p_tx->cur_send_frag_num].tx_frag = pkt->first_frag;
1805 p_curp->bds_set[p_tx->cur_send_frag_num].frag_len = pkt->first_frag_len;
1806 p_tx->cur_send_frag_num++;
1807 }
1808
1809 static void
qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2,struct qed_ll2_tx_packet * p_curp,struct qed_ll2_tx_pkt_info * pkt)1810 qed_ll2_prepare_tx_packet_set_bd(struct qed_hwfn *p_hwfn,
1811 struct qed_ll2_info *p_ll2,
1812 struct qed_ll2_tx_packet *p_curp,
1813 struct qed_ll2_tx_pkt_info *pkt)
1814 {
1815 struct qed_chain *p_tx_chain = &p_ll2->tx_queue.txq_chain;
1816 u16 prod_idx = qed_chain_get_prod_idx(p_tx_chain);
1817 struct core_tx_bd *start_bd = NULL;
1818 enum core_roce_flavor_type roce_flavor;
1819 enum core_tx_dest tx_dest;
1820 u16 bd_data = 0, frag_idx;
1821 u16 bitfield1;
1822
1823 roce_flavor = (pkt->qed_roce_flavor == QED_LL2_ROCE) ? CORE_ROCE
1824 : CORE_RROCE;
1825
1826 switch (pkt->tx_dest) {
1827 case QED_LL2_TX_DEST_NW:
1828 tx_dest = CORE_TX_DEST_NW;
1829 break;
1830 case QED_LL2_TX_DEST_LB:
1831 tx_dest = CORE_TX_DEST_LB;
1832 break;
1833 case QED_LL2_TX_DEST_DROP:
1834 tx_dest = CORE_TX_DEST_DROP;
1835 break;
1836 default:
1837 tx_dest = CORE_TX_DEST_LB;
1838 break;
1839 }
1840
1841 start_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
1842 if (QED_IS_IWARP_PERSONALITY(p_hwfn) &&
1843 p_ll2->input.conn_type == QED_LL2_TYPE_OOO) {
1844 start_bd->nw_vlan_or_lb_echo =
1845 cpu_to_le16(IWARP_LL2_IN_ORDER_TX_QUEUE);
1846 } else {
1847 start_bd->nw_vlan_or_lb_echo = cpu_to_le16(pkt->vlan);
1848 if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) &&
1849 p_ll2->input.conn_type == QED_LL2_TYPE_FCOE)
1850 pkt->remove_stag = true;
1851 }
1852
1853 bitfield1 = le16_to_cpu(start_bd->bitfield1);
1854 SET_FIELD(bitfield1, CORE_TX_BD_L4_HDR_OFFSET_W, pkt->l4_hdr_offset_w);
1855 SET_FIELD(bitfield1, CORE_TX_BD_TX_DST, tx_dest);
1856 start_bd->bitfield1 = cpu_to_le16(bitfield1);
1857
1858 bd_data |= pkt->bd_flags;
1859 SET_FIELD(bd_data, CORE_TX_BD_DATA_START_BD, 0x1);
1860 SET_FIELD(bd_data, CORE_TX_BD_DATA_NBDS, pkt->num_of_bds);
1861 SET_FIELD(bd_data, CORE_TX_BD_DATA_ROCE_FLAV, roce_flavor);
1862 SET_FIELD(bd_data, CORE_TX_BD_DATA_IP_CSUM, !!(pkt->enable_ip_cksum));
1863 SET_FIELD(bd_data, CORE_TX_BD_DATA_L4_CSUM, !!(pkt->enable_l4_cksum));
1864 SET_FIELD(bd_data, CORE_TX_BD_DATA_IP_LEN, !!(pkt->calc_ip_len));
1865 SET_FIELD(bd_data, CORE_TX_BD_DATA_DISABLE_STAG_INSERTION,
1866 !!(pkt->remove_stag));
1867
1868 start_bd->bd_data.as_bitfield = cpu_to_le16(bd_data);
1869 DMA_REGPAIR_LE(start_bd->addr, pkt->first_frag);
1870 start_bd->nbytes = cpu_to_le16(pkt->first_frag_len);
1871
1872 DP_VERBOSE(p_hwfn,
1873 (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
1874 "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Tx Producer at [0x%04x] - set with a %04x bytes %02x BDs buffer at %08x:%08x\n",
1875 p_ll2->queue_id,
1876 p_ll2->cid,
1877 p_ll2->input.conn_type,
1878 prod_idx,
1879 pkt->first_frag_len,
1880 pkt->num_of_bds,
1881 le32_to_cpu(start_bd->addr.hi),
1882 le32_to_cpu(start_bd->addr.lo));
1883
1884 if (p_ll2->tx_queue.cur_send_frag_num == pkt->num_of_bds)
1885 return;
1886
1887 /* Need to provide the packet with additional BDs for frags */
1888 for (frag_idx = p_ll2->tx_queue.cur_send_frag_num;
1889 frag_idx < pkt->num_of_bds; frag_idx++) {
1890 struct core_tx_bd **p_bd = &p_curp->bds_set[frag_idx].txq_bd;
1891
1892 *p_bd = (struct core_tx_bd *)qed_chain_produce(p_tx_chain);
1893 (*p_bd)->bd_data.as_bitfield = 0;
1894 (*p_bd)->bitfield1 = 0;
1895 p_curp->bds_set[frag_idx].tx_frag = 0;
1896 p_curp->bds_set[frag_idx].frag_len = 0;
1897 }
1898 }
1899
1900 /* This should be called while the Txq spinlock is being held */
qed_ll2_tx_packet_notify(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)1901 static void qed_ll2_tx_packet_notify(struct qed_hwfn *p_hwfn,
1902 struct qed_ll2_info *p_ll2_conn)
1903 {
1904 bool b_notify = p_ll2_conn->tx_queue.cur_send_packet->notify_fw;
1905 struct qed_ll2_tx_queue *p_tx = &p_ll2_conn->tx_queue;
1906 struct qed_ll2_tx_packet *p_pkt = NULL;
1907 u16 bd_prod;
1908
1909 /* If there are missing BDs, don't do anything now */
1910 if (p_ll2_conn->tx_queue.cur_send_frag_num !=
1911 p_ll2_conn->tx_queue.cur_send_packet->bd_used)
1912 return;
1913
1914 /* Push the current packet to the list and clean after it */
1915 list_add_tail(&p_ll2_conn->tx_queue.cur_send_packet->list_entry,
1916 &p_ll2_conn->tx_queue.sending_descq);
1917 p_ll2_conn->tx_queue.cur_send_packet = NULL;
1918 p_ll2_conn->tx_queue.cur_send_frag_num = 0;
1919
1920 /* Notify FW of packet only if requested to */
1921 if (!b_notify)
1922 return;
1923
1924 bd_prod = qed_chain_get_prod_idx(&p_ll2_conn->tx_queue.txq_chain);
1925
1926 while (!list_empty(&p_tx->sending_descq)) {
1927 p_pkt = list_first_entry(&p_tx->sending_descq,
1928 struct qed_ll2_tx_packet, list_entry);
1929 if (!p_pkt)
1930 break;
1931
1932 list_move_tail(&p_pkt->list_entry, &p_tx->active_descq);
1933 }
1934
1935 p_tx->db_msg.spq_prod = cpu_to_le16(bd_prod);
1936
1937 /* Make sure the BDs data is updated before ringing the doorbell */
1938 wmb();
1939
1940 DIRECT_REG_WR(p_tx->doorbell_addr, *((u32 *)&p_tx->db_msg));
1941
1942 DP_VERBOSE(p_hwfn,
1943 (NETIF_MSG_TX_QUEUED | QED_MSG_LL2),
1944 "LL2 [q 0x%02x cid 0x%08x type 0x%08x] Doorbelled [producer 0x%04x]\n",
1945 p_ll2_conn->queue_id,
1946 p_ll2_conn->cid,
1947 p_ll2_conn->input.conn_type, p_tx->db_msg.spq_prod);
1948 }
1949
qed_ll2_prepare_tx_packet(void * cxt,u8 connection_handle,struct qed_ll2_tx_pkt_info * pkt,bool notify_fw)1950 int qed_ll2_prepare_tx_packet(void *cxt,
1951 u8 connection_handle,
1952 struct qed_ll2_tx_pkt_info *pkt,
1953 bool notify_fw)
1954 {
1955 struct qed_hwfn *p_hwfn = cxt;
1956 struct qed_ll2_tx_packet *p_curp = NULL;
1957 struct qed_ll2_info *p_ll2_conn = NULL;
1958 struct qed_ll2_tx_queue *p_tx;
1959 struct qed_chain *p_tx_chain;
1960 unsigned long flags;
1961 int rc = 0;
1962
1963 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
1964 if (!p_ll2_conn)
1965 return -EINVAL;
1966 p_tx = &p_ll2_conn->tx_queue;
1967 p_tx_chain = &p_tx->txq_chain;
1968
1969 if (pkt->num_of_bds > p_ll2_conn->input.tx_max_bds_per_packet)
1970 return -EIO;
1971
1972 spin_lock_irqsave(&p_tx->lock, flags);
1973 if (p_tx->cur_send_packet) {
1974 rc = -EEXIST;
1975 goto out;
1976 }
1977
1978 /* Get entry, but only if we have tx elements for it */
1979 if (!list_empty(&p_tx->free_descq))
1980 p_curp = list_first_entry(&p_tx->free_descq,
1981 struct qed_ll2_tx_packet, list_entry);
1982 if (p_curp && qed_chain_get_elem_left(p_tx_chain) < pkt->num_of_bds)
1983 p_curp = NULL;
1984
1985 if (!p_curp) {
1986 rc = -EBUSY;
1987 goto out;
1988 }
1989
1990 /* Prepare packet and BD, and perhaps send a doorbell to FW */
1991 qed_ll2_prepare_tx_packet_set(p_hwfn, p_tx, p_curp, pkt, notify_fw);
1992
1993 qed_ll2_prepare_tx_packet_set_bd(p_hwfn, p_ll2_conn, p_curp, pkt);
1994
1995 qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
1996
1997 out:
1998 spin_unlock_irqrestore(&p_tx->lock, flags);
1999 return rc;
2000 }
2001
qed_ll2_set_fragment_of_tx_packet(void * cxt,u8 connection_handle,dma_addr_t addr,u16 nbytes)2002 int qed_ll2_set_fragment_of_tx_packet(void *cxt,
2003 u8 connection_handle,
2004 dma_addr_t addr, u16 nbytes)
2005 {
2006 struct qed_ll2_tx_packet *p_cur_send_packet = NULL;
2007 struct qed_hwfn *p_hwfn = cxt;
2008 struct qed_ll2_info *p_ll2_conn = NULL;
2009 u16 cur_send_frag_num = 0;
2010 struct core_tx_bd *p_bd;
2011 unsigned long flags;
2012
2013 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
2014 if (!p_ll2_conn)
2015 return -EINVAL;
2016
2017 if (!p_ll2_conn->tx_queue.cur_send_packet)
2018 return -EINVAL;
2019
2020 p_cur_send_packet = p_ll2_conn->tx_queue.cur_send_packet;
2021 cur_send_frag_num = p_ll2_conn->tx_queue.cur_send_frag_num;
2022
2023 if (cur_send_frag_num >= p_cur_send_packet->bd_used)
2024 return -EINVAL;
2025
2026 /* Fill the BD information, and possibly notify FW */
2027 p_bd = p_cur_send_packet->bds_set[cur_send_frag_num].txq_bd;
2028 DMA_REGPAIR_LE(p_bd->addr, addr);
2029 p_bd->nbytes = cpu_to_le16(nbytes);
2030 p_cur_send_packet->bds_set[cur_send_frag_num].tx_frag = addr;
2031 p_cur_send_packet->bds_set[cur_send_frag_num].frag_len = nbytes;
2032
2033 p_ll2_conn->tx_queue.cur_send_frag_num++;
2034
2035 spin_lock_irqsave(&p_ll2_conn->tx_queue.lock, flags);
2036 qed_ll2_tx_packet_notify(p_hwfn, p_ll2_conn);
2037 spin_unlock_irqrestore(&p_ll2_conn->tx_queue.lock, flags);
2038
2039 return 0;
2040 }
2041
qed_ll2_terminate_connection(void * cxt,u8 connection_handle)2042 int qed_ll2_terminate_connection(void *cxt, u8 connection_handle)
2043 {
2044 struct qed_hwfn *p_hwfn = cxt;
2045 struct qed_ll2_info *p_ll2_conn = NULL;
2046 int rc = -EINVAL;
2047 struct qed_ptt *p_ptt;
2048
2049 p_ptt = qed_ptt_acquire(p_hwfn);
2050 if (!p_ptt)
2051 return -EAGAIN;
2052
2053 p_ll2_conn = qed_ll2_handle_sanity_lock(p_hwfn, connection_handle);
2054 if (!p_ll2_conn) {
2055 rc = -EINVAL;
2056 goto out;
2057 }
2058
2059 /* Stop Tx & Rx of connection, if needed */
2060 if (QED_LL2_TX_REGISTERED(p_ll2_conn)) {
2061 p_ll2_conn->tx_queue.b_cb_registered = false;
2062 smp_wmb(); /* Make sure this is seen by ll2_lb_rxq_completion */
2063 rc = qed_sp_ll2_tx_queue_stop(p_hwfn, p_ll2_conn);
2064 if (rc)
2065 goto out;
2066
2067 qed_ll2_txq_flush(p_hwfn, connection_handle);
2068 qed_int_unregister_cb(p_hwfn, p_ll2_conn->tx_queue.tx_sb_index);
2069 }
2070
2071 if (QED_LL2_RX_REGISTERED(p_ll2_conn)) {
2072 p_ll2_conn->rx_queue.b_cb_registered = false;
2073 smp_wmb(); /* Make sure this is seen by ll2_lb_rxq_completion */
2074
2075 if (p_ll2_conn->rx_queue.ctx_based)
2076 qed_db_recovery_del(p_hwfn->cdev,
2077 p_ll2_conn->rx_queue.set_prod_addr,
2078 &p_ll2_conn->rx_queue.db_data);
2079
2080 rc = qed_sp_ll2_rx_queue_stop(p_hwfn, p_ll2_conn);
2081 if (rc)
2082 goto out;
2083
2084 qed_ll2_rxq_flush(p_hwfn, connection_handle);
2085 qed_int_unregister_cb(p_hwfn, p_ll2_conn->rx_queue.rx_sb_index);
2086 }
2087
2088 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_OOO)
2089 qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
2090
2091 if (p_ll2_conn->input.conn_type == QED_LL2_TYPE_FCOE) {
2092 if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
2093 qed_llh_remove_protocol_filter(p_hwfn->cdev, 0,
2094 QED_LLH_FILTER_ETHERTYPE,
2095 ETH_P_FCOE, 0);
2096 qed_llh_remove_protocol_filter(p_hwfn->cdev, 0,
2097 QED_LLH_FILTER_ETHERTYPE,
2098 ETH_P_FIP, 0);
2099 }
2100
2101 out:
2102 qed_ptt_release(p_hwfn, p_ptt);
2103 return rc;
2104 }
2105
qed_ll2_release_connection_ooo(struct qed_hwfn * p_hwfn,struct qed_ll2_info * p_ll2_conn)2106 static void qed_ll2_release_connection_ooo(struct qed_hwfn *p_hwfn,
2107 struct qed_ll2_info *p_ll2_conn)
2108 {
2109 struct qed_ooo_buffer *p_buffer;
2110
2111 if (p_ll2_conn->input.conn_type != QED_LL2_TYPE_OOO)
2112 return;
2113
2114 qed_ooo_release_all_isles(p_hwfn, p_hwfn->p_ooo_info);
2115 while ((p_buffer = qed_ooo_get_free_buffer(p_hwfn,
2116 p_hwfn->p_ooo_info))) {
2117 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2118 p_buffer->rx_buffer_size,
2119 p_buffer->rx_buffer_virt_addr,
2120 p_buffer->rx_buffer_phys_addr);
2121 kfree(p_buffer);
2122 }
2123 }
2124
qed_ll2_release_connection(void * cxt,u8 connection_handle)2125 void qed_ll2_release_connection(void *cxt, u8 connection_handle)
2126 {
2127 struct qed_hwfn *p_hwfn = cxt;
2128 struct qed_ll2_info *p_ll2_conn = NULL;
2129
2130 p_ll2_conn = qed_ll2_handle_sanity(p_hwfn, connection_handle);
2131 if (!p_ll2_conn)
2132 return;
2133
2134 kfree(p_ll2_conn->tx_queue.descq_mem);
2135 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->tx_queue.txq_chain);
2136
2137 kfree(p_ll2_conn->rx_queue.descq_array);
2138 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rxq_chain);
2139 qed_chain_free(p_hwfn->cdev, &p_ll2_conn->rx_queue.rcq_chain);
2140
2141 qed_cxt_release_cid(p_hwfn, p_ll2_conn->cid);
2142
2143 qed_ll2_release_connection_ooo(p_hwfn, p_ll2_conn);
2144
2145 mutex_lock(&p_ll2_conn->mutex);
2146 p_ll2_conn->b_active = false;
2147 mutex_unlock(&p_ll2_conn->mutex);
2148 }
2149
qed_ll2_alloc(struct qed_hwfn * p_hwfn)2150 int qed_ll2_alloc(struct qed_hwfn *p_hwfn)
2151 {
2152 struct qed_ll2_info *p_ll2_connections;
2153 u8 i;
2154
2155 /* Allocate LL2's set struct */
2156 p_ll2_connections = kcalloc(QED_MAX_NUM_OF_LL2_CONNECTIONS,
2157 sizeof(struct qed_ll2_info), GFP_KERNEL);
2158 if (!p_ll2_connections) {
2159 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_ll2'\n");
2160 return -ENOMEM;
2161 }
2162
2163 for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
2164 p_ll2_connections[i].my_id = i;
2165
2166 p_hwfn->p_ll2_info = p_ll2_connections;
2167 return 0;
2168 }
2169
qed_ll2_setup(struct qed_hwfn * p_hwfn)2170 void qed_ll2_setup(struct qed_hwfn *p_hwfn)
2171 {
2172 int i;
2173
2174 for (i = 0; i < QED_MAX_NUM_OF_LL2_CONNECTIONS; i++)
2175 mutex_init(&p_hwfn->p_ll2_info[i].mutex);
2176 }
2177
qed_ll2_free(struct qed_hwfn * p_hwfn)2178 void qed_ll2_free(struct qed_hwfn *p_hwfn)
2179 {
2180 if (!p_hwfn->p_ll2_info)
2181 return;
2182
2183 kfree(p_hwfn->p_ll2_info);
2184 p_hwfn->p_ll2_info = NULL;
2185 }
2186
_qed_ll2_get_port_stats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_ll2_stats * p_stats)2187 static void _qed_ll2_get_port_stats(struct qed_hwfn *p_hwfn,
2188 struct qed_ptt *p_ptt,
2189 struct qed_ll2_stats *p_stats)
2190 {
2191 struct core_ll2_port_stats port_stats;
2192
2193 memset(&port_stats, 0, sizeof(port_stats));
2194 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
2195 BAR0_MAP_REG_TSDM_RAM +
2196 TSTORM_LL2_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)),
2197 sizeof(port_stats));
2198
2199 p_stats->gsi_invalid_hdr += HILO_64_REGPAIR(port_stats.gsi_invalid_hdr);
2200 p_stats->gsi_invalid_pkt_length +=
2201 HILO_64_REGPAIR(port_stats.gsi_invalid_pkt_length);
2202 p_stats->gsi_unsupported_pkt_typ +=
2203 HILO_64_REGPAIR(port_stats.gsi_unsupported_pkt_typ);
2204 p_stats->gsi_crcchksm_error +=
2205 HILO_64_REGPAIR(port_stats.gsi_crcchksm_error);
2206 }
2207
_qed_ll2_get_tstats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_ll2_info * p_ll2_conn,struct qed_ll2_stats * p_stats)2208 static void _qed_ll2_get_tstats(struct qed_hwfn *p_hwfn,
2209 struct qed_ptt *p_ptt,
2210 struct qed_ll2_info *p_ll2_conn,
2211 struct qed_ll2_stats *p_stats)
2212 {
2213 struct core_ll2_tstorm_per_queue_stat tstats;
2214 u8 qid = p_ll2_conn->queue_id;
2215 u32 tstats_addr;
2216
2217 memset(&tstats, 0, sizeof(tstats));
2218 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
2219 CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(qid);
2220 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, sizeof(tstats));
2221
2222 p_stats->packet_too_big_discard +=
2223 HILO_64_REGPAIR(tstats.packet_too_big_discard);
2224 p_stats->no_buff_discard += HILO_64_REGPAIR(tstats.no_buff_discard);
2225 }
2226
_qed_ll2_get_ustats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_ll2_info * p_ll2_conn,struct qed_ll2_stats * p_stats)2227 static void _qed_ll2_get_ustats(struct qed_hwfn *p_hwfn,
2228 struct qed_ptt *p_ptt,
2229 struct qed_ll2_info *p_ll2_conn,
2230 struct qed_ll2_stats *p_stats)
2231 {
2232 struct core_ll2_ustorm_per_queue_stat ustats;
2233 u8 qid = p_ll2_conn->queue_id;
2234 u32 ustats_addr;
2235
2236 memset(&ustats, 0, sizeof(ustats));
2237 ustats_addr = BAR0_MAP_REG_USDM_RAM +
2238 CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(qid);
2239 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, sizeof(ustats));
2240
2241 p_stats->rcv_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
2242 p_stats->rcv_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
2243 p_stats->rcv_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
2244 p_stats->rcv_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
2245 p_stats->rcv_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
2246 p_stats->rcv_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
2247 }
2248
_qed_ll2_get_pstats(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_ll2_info * p_ll2_conn,struct qed_ll2_stats * p_stats)2249 static void _qed_ll2_get_pstats(struct qed_hwfn *p_hwfn,
2250 struct qed_ptt *p_ptt,
2251 struct qed_ll2_info *p_ll2_conn,
2252 struct qed_ll2_stats *p_stats)
2253 {
2254 struct core_ll2_pstorm_per_queue_stat pstats;
2255 u8 stats_id = p_ll2_conn->tx_stats_id;
2256 u32 pstats_addr;
2257
2258 memset(&pstats, 0, sizeof(pstats));
2259 pstats_addr = BAR0_MAP_REG_PSDM_RAM +
2260 CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(stats_id);
2261 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, sizeof(pstats));
2262
2263 p_stats->sent_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
2264 p_stats->sent_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
2265 p_stats->sent_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
2266 p_stats->sent_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
2267 p_stats->sent_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
2268 p_stats->sent_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
2269 }
2270
__qed_ll2_get_stats(void * cxt,u8 connection_handle,struct qed_ll2_stats * p_stats)2271 static int __qed_ll2_get_stats(void *cxt, u8 connection_handle,
2272 struct qed_ll2_stats *p_stats)
2273 {
2274 struct qed_hwfn *p_hwfn = cxt;
2275 struct qed_ll2_info *p_ll2_conn = NULL;
2276 struct qed_ptt *p_ptt;
2277
2278 if ((connection_handle >= QED_MAX_NUM_OF_LL2_CONNECTIONS) ||
2279 !p_hwfn->p_ll2_info)
2280 return -EINVAL;
2281
2282 p_ll2_conn = &p_hwfn->p_ll2_info[connection_handle];
2283
2284 p_ptt = qed_ptt_acquire(p_hwfn);
2285 if (!p_ptt) {
2286 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
2287 return -EINVAL;
2288 }
2289
2290 if (p_ll2_conn->input.gsi_enable)
2291 _qed_ll2_get_port_stats(p_hwfn, p_ptt, p_stats);
2292
2293 _qed_ll2_get_tstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
2294
2295 _qed_ll2_get_ustats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
2296
2297 if (p_ll2_conn->tx_stats_en)
2298 _qed_ll2_get_pstats(p_hwfn, p_ptt, p_ll2_conn, p_stats);
2299
2300 qed_ptt_release(p_hwfn, p_ptt);
2301
2302 return 0;
2303 }
2304
qed_ll2_get_stats(void * cxt,u8 connection_handle,struct qed_ll2_stats * p_stats)2305 int qed_ll2_get_stats(void *cxt,
2306 u8 connection_handle, struct qed_ll2_stats *p_stats)
2307 {
2308 memset(p_stats, 0, sizeof(*p_stats));
2309 return __qed_ll2_get_stats(cxt, connection_handle, p_stats);
2310 }
2311
qed_ll2b_release_rx_packet(void * cxt,u8 connection_handle,void * cookie,dma_addr_t rx_buf_addr,bool b_last_packet)2312 static void qed_ll2b_release_rx_packet(void *cxt,
2313 u8 connection_handle,
2314 void *cookie,
2315 dma_addr_t rx_buf_addr,
2316 bool b_last_packet)
2317 {
2318 struct qed_hwfn *p_hwfn = cxt;
2319
2320 qed_ll2_dealloc_buffer(p_hwfn->cdev, cookie);
2321 }
2322
qed_ll2_register_cb_ops(struct qed_dev * cdev,const struct qed_ll2_cb_ops * ops,void * cookie)2323 static void qed_ll2_register_cb_ops(struct qed_dev *cdev,
2324 const struct qed_ll2_cb_ops *ops,
2325 void *cookie)
2326 {
2327 cdev->ll2->cbs = ops;
2328 cdev->ll2->cb_cookie = cookie;
2329 }
2330
2331 static struct qed_ll2_cbs ll2_cbs = {
2332 .rx_comp_cb = &qed_ll2b_complete_rx_packet,
2333 .rx_release_cb = &qed_ll2b_release_rx_packet,
2334 .tx_comp_cb = &qed_ll2b_complete_tx_packet,
2335 .tx_release_cb = &qed_ll2b_complete_tx_packet,
2336 };
2337
qed_ll2_set_conn_data(struct qed_hwfn * p_hwfn,struct qed_ll2_acquire_data * data,struct qed_ll2_params * params,enum qed_ll2_conn_type conn_type,u8 * handle,bool lb)2338 static void qed_ll2_set_conn_data(struct qed_hwfn *p_hwfn,
2339 struct qed_ll2_acquire_data *data,
2340 struct qed_ll2_params *params,
2341 enum qed_ll2_conn_type conn_type,
2342 u8 *handle, bool lb)
2343 {
2344 memset(data, 0, sizeof(*data));
2345
2346 data->input.conn_type = conn_type;
2347 data->input.mtu = params->mtu;
2348 data->input.rx_num_desc = QED_LL2_RX_SIZE;
2349 data->input.rx_drop_ttl0_flg = params->drop_ttl0_packets;
2350 data->input.rx_vlan_removal_en = params->rx_vlan_stripping;
2351 data->input.tx_num_desc = QED_LL2_TX_SIZE;
2352 data->p_connection_handle = handle;
2353 data->cbs = &ll2_cbs;
2354 ll2_cbs.cookie = p_hwfn;
2355
2356 if (lb) {
2357 data->input.tx_tc = PKT_LB_TC;
2358 data->input.tx_dest = QED_LL2_TX_DEST_LB;
2359 } else {
2360 data->input.tx_tc = 0;
2361 data->input.tx_dest = QED_LL2_TX_DEST_NW;
2362 }
2363 }
2364
qed_ll2_start_ooo(struct qed_hwfn * p_hwfn,struct qed_ll2_params * params)2365 static int qed_ll2_start_ooo(struct qed_hwfn *p_hwfn,
2366 struct qed_ll2_params *params)
2367 {
2368 u8 *handle = &p_hwfn->pf_params.iscsi_pf_params.ll2_ooo_queue_id;
2369 struct qed_ll2_acquire_data data;
2370 int rc;
2371
2372 qed_ll2_set_conn_data(p_hwfn, &data, params,
2373 QED_LL2_TYPE_OOO, handle, true);
2374
2375 rc = qed_ll2_acquire_connection(p_hwfn, &data);
2376 if (rc) {
2377 DP_INFO(p_hwfn, "Failed to acquire LL2 OOO connection\n");
2378 goto out;
2379 }
2380
2381 rc = qed_ll2_establish_connection(p_hwfn, *handle);
2382 if (rc) {
2383 DP_INFO(p_hwfn, "Failed to establish LL2 OOO connection\n");
2384 goto fail;
2385 }
2386
2387 return 0;
2388
2389 fail:
2390 qed_ll2_release_connection(p_hwfn, *handle);
2391 out:
2392 *handle = QED_LL2_UNUSED_HANDLE;
2393 return rc;
2394 }
2395
qed_ll2_is_storage_eng1(struct qed_dev * cdev)2396 static bool qed_ll2_is_storage_eng1(struct qed_dev *cdev)
2397 {
2398 return (QED_IS_FCOE_PERSONALITY(QED_LEADING_HWFN(cdev)) ||
2399 QED_IS_ISCSI_PERSONALITY(QED_LEADING_HWFN(cdev))) &&
2400 (QED_AFFIN_HWFN(cdev) != QED_LEADING_HWFN(cdev));
2401 }
2402
__qed_ll2_stop(struct qed_hwfn * p_hwfn)2403 static int __qed_ll2_stop(struct qed_hwfn *p_hwfn)
2404 {
2405 struct qed_dev *cdev = p_hwfn->cdev;
2406 int rc;
2407
2408 rc = qed_ll2_terminate_connection(p_hwfn, cdev->ll2->handle);
2409 if (rc)
2410 DP_INFO(cdev, "Failed to terminate LL2 connection\n");
2411
2412 qed_ll2_release_connection(p_hwfn, cdev->ll2->handle);
2413
2414 return rc;
2415 }
2416
qed_ll2_stop(struct qed_dev * cdev)2417 static int qed_ll2_stop(struct qed_dev *cdev)
2418 {
2419 bool b_is_storage_eng1 = qed_ll2_is_storage_eng1(cdev);
2420 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev);
2421 int rc = 0, rc2 = 0;
2422
2423 if (cdev->ll2->handle == QED_LL2_UNUSED_HANDLE)
2424 return 0;
2425
2426 qed_llh_remove_mac_filter(cdev, 0, cdev->ll2_mac_address);
2427 eth_zero_addr(cdev->ll2_mac_address);
2428
2429 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2430 qed_ll2_stop_ooo(p_hwfn);
2431
2432 /* In CMT mode, LL2 is always started on engine 0 for a storage PF */
2433 if (b_is_storage_eng1) {
2434 rc2 = __qed_ll2_stop(QED_LEADING_HWFN(cdev));
2435 if (rc2)
2436 DP_NOTICE(QED_LEADING_HWFN(cdev),
2437 "Failed to stop LL2 on engine 0\n");
2438 }
2439
2440 rc = __qed_ll2_stop(p_hwfn);
2441 if (rc)
2442 DP_NOTICE(p_hwfn, "Failed to stop LL2\n");
2443
2444 qed_ll2_kill_buffers(cdev);
2445
2446 cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
2447
2448 return rc | rc2;
2449 }
2450
__qed_ll2_start(struct qed_hwfn * p_hwfn,struct qed_ll2_params * params)2451 static int __qed_ll2_start(struct qed_hwfn *p_hwfn,
2452 struct qed_ll2_params *params)
2453 {
2454 struct qed_ll2_buffer *buffer, *tmp_buffer;
2455 struct qed_dev *cdev = p_hwfn->cdev;
2456 enum qed_ll2_conn_type conn_type;
2457 struct qed_ll2_acquire_data data;
2458 int rc, rx_cnt;
2459
2460 switch (p_hwfn->hw_info.personality) {
2461 case QED_PCI_FCOE:
2462 conn_type = QED_LL2_TYPE_FCOE;
2463 break;
2464 case QED_PCI_ISCSI:
2465 conn_type = QED_LL2_TYPE_ISCSI;
2466 break;
2467 case QED_PCI_ETH_ROCE:
2468 conn_type = QED_LL2_TYPE_ROCE;
2469 break;
2470 default:
2471
2472 conn_type = QED_LL2_TYPE_TEST;
2473 }
2474
2475 qed_ll2_set_conn_data(p_hwfn, &data, params, conn_type,
2476 &cdev->ll2->handle, false);
2477
2478 rc = qed_ll2_acquire_connection(p_hwfn, &data);
2479 if (rc) {
2480 DP_INFO(p_hwfn, "Failed to acquire LL2 connection\n");
2481 return rc;
2482 }
2483
2484 rc = qed_ll2_establish_connection(p_hwfn, cdev->ll2->handle);
2485 if (rc) {
2486 DP_INFO(p_hwfn, "Failed to establish LL2 connection\n");
2487 goto release_conn;
2488 }
2489
2490 /* Post all Rx buffers to FW */
2491 spin_lock_bh(&cdev->ll2->lock);
2492 rx_cnt = cdev->ll2->rx_cnt;
2493 list_for_each_entry_safe(buffer, tmp_buffer, &cdev->ll2->list, list) {
2494 rc = qed_ll2_post_rx_buffer(p_hwfn,
2495 cdev->ll2->handle,
2496 buffer->phys_addr, 0, buffer, 1);
2497 if (rc) {
2498 DP_INFO(p_hwfn,
2499 "Failed to post an Rx buffer; Deleting it\n");
2500 dma_unmap_single(&cdev->pdev->dev, buffer->phys_addr,
2501 cdev->ll2->rx_size, DMA_FROM_DEVICE);
2502 kfree(buffer->data);
2503 list_del(&buffer->list);
2504 kfree(buffer);
2505 } else {
2506 rx_cnt++;
2507 }
2508 }
2509 spin_unlock_bh(&cdev->ll2->lock);
2510
2511 if (rx_cnt == cdev->ll2->rx_cnt) {
2512 DP_NOTICE(p_hwfn, "Failed passing even a single Rx buffer\n");
2513 goto terminate_conn;
2514 }
2515 cdev->ll2->rx_cnt = rx_cnt;
2516
2517 return 0;
2518
2519 terminate_conn:
2520 qed_ll2_terminate_connection(p_hwfn, cdev->ll2->handle);
2521 release_conn:
2522 qed_ll2_release_connection(p_hwfn, cdev->ll2->handle);
2523 return rc;
2524 }
2525
qed_ll2_start(struct qed_dev * cdev,struct qed_ll2_params * params)2526 static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
2527 {
2528 bool b_is_storage_eng1 = qed_ll2_is_storage_eng1(cdev);
2529 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev);
2530 struct qed_ll2_buffer *buffer;
2531 int rx_num_desc, i, rc;
2532
2533 if (!is_valid_ether_addr(params->ll2_mac_address)) {
2534 DP_NOTICE(cdev, "Invalid Ethernet address\n");
2535 return -EINVAL;
2536 }
2537
2538 WARN_ON(!cdev->ll2->cbs);
2539
2540 /* Initialize LL2 locks & lists */
2541 INIT_LIST_HEAD(&cdev->ll2->list);
2542 spin_lock_init(&cdev->ll2->lock);
2543
2544 cdev->ll2->rx_size = NET_SKB_PAD + ETH_HLEN +
2545 L1_CACHE_BYTES + params->mtu;
2546
2547 /* Allocate memory for LL2.
2548 * In CMT mode, in case of a storage PF which is affintized to engine 1,
2549 * LL2 is started also on engine 0 and thus we need twofold buffers.
2550 */
2551 rx_num_desc = QED_LL2_RX_SIZE * (b_is_storage_eng1 ? 2 : 1);
2552 DP_INFO(cdev, "Allocating %d LL2 buffers of size %08x bytes\n",
2553 rx_num_desc, cdev->ll2->rx_size);
2554 for (i = 0; i < rx_num_desc; i++) {
2555 buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
2556 if (!buffer) {
2557 DP_INFO(cdev, "Failed to allocate LL2 buffers\n");
2558 rc = -ENOMEM;
2559 goto err0;
2560 }
2561
2562 rc = qed_ll2_alloc_buffer(cdev, (u8 **)&buffer->data,
2563 &buffer->phys_addr);
2564 if (rc) {
2565 kfree(buffer);
2566 goto err0;
2567 }
2568
2569 list_add_tail(&buffer->list, &cdev->ll2->list);
2570 }
2571
2572 rc = __qed_ll2_start(p_hwfn, params);
2573 if (rc) {
2574 DP_NOTICE(cdev, "Failed to start LL2\n");
2575 goto err0;
2576 }
2577
2578 /* In CMT mode, always need to start LL2 on engine 0 for a storage PF,
2579 * since broadcast/mutlicast packets are routed to engine 0.
2580 */
2581 if (b_is_storage_eng1) {
2582 rc = __qed_ll2_start(QED_LEADING_HWFN(cdev), params);
2583 if (rc) {
2584 DP_NOTICE(QED_LEADING_HWFN(cdev),
2585 "Failed to start LL2 on engine 0\n");
2586 goto err1;
2587 }
2588 }
2589
2590 if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) {
2591 DP_VERBOSE(cdev, QED_MSG_STORAGE, "Starting OOO LL2 queue\n");
2592 rc = qed_ll2_start_ooo(p_hwfn, params);
2593 if (rc) {
2594 DP_NOTICE(cdev, "Failed to start OOO LL2\n");
2595 goto err2;
2596 }
2597 }
2598
2599 rc = qed_llh_add_mac_filter(cdev, 0, params->ll2_mac_address);
2600 if (rc) {
2601 DP_NOTICE(cdev, "Failed to add an LLH filter\n");
2602 goto err3;
2603 }
2604
2605 ether_addr_copy(cdev->ll2_mac_address, params->ll2_mac_address);
2606
2607 return 0;
2608
2609 err3:
2610 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2611 qed_ll2_stop_ooo(p_hwfn);
2612 err2:
2613 if (b_is_storage_eng1)
2614 __qed_ll2_stop(QED_LEADING_HWFN(cdev));
2615 err1:
2616 __qed_ll2_stop(p_hwfn);
2617 err0:
2618 qed_ll2_kill_buffers(cdev);
2619 cdev->ll2->handle = QED_LL2_UNUSED_HANDLE;
2620 return rc;
2621 }
2622
qed_ll2_start_xmit(struct qed_dev * cdev,struct sk_buff * skb,unsigned long xmit_flags)2623 static int qed_ll2_start_xmit(struct qed_dev *cdev, struct sk_buff *skb,
2624 unsigned long xmit_flags)
2625 {
2626 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev);
2627 struct qed_ll2_tx_pkt_info pkt;
2628 const skb_frag_t *frag;
2629 u8 flags = 0, nr_frags;
2630 int rc = -EINVAL, i;
2631 dma_addr_t mapping;
2632 u16 vlan = 0;
2633
2634 if (unlikely(skb->ip_summed != CHECKSUM_NONE)) {
2635 DP_INFO(cdev, "Cannot transmit a checksummed packet\n");
2636 return -EINVAL;
2637 }
2638
2639 /* Cache number of fragments from SKB since SKB may be freed by
2640 * the completion routine after calling qed_ll2_prepare_tx_packet()
2641 */
2642 nr_frags = skb_shinfo(skb)->nr_frags;
2643
2644 if (1 + nr_frags > CORE_LL2_TX_MAX_BDS_PER_PACKET) {
2645 DP_ERR(cdev, "Cannot transmit a packet with %d fragments\n",
2646 1 + nr_frags);
2647 return -EINVAL;
2648 }
2649
2650 mapping = dma_map_single(&cdev->pdev->dev, skb->data,
2651 skb->len, DMA_TO_DEVICE);
2652 if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
2653 DP_NOTICE(cdev, "SKB mapping failed\n");
2654 return -EINVAL;
2655 }
2656
2657 /* Request HW to calculate IP csum */
2658 if (!((vlan_get_protocol(skb) == htons(ETH_P_IPV6)) &&
2659 ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
2660 flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT);
2661
2662 if (skb_vlan_tag_present(skb)) {
2663 vlan = skb_vlan_tag_get(skb);
2664 flags |= BIT(CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT);
2665 }
2666
2667 memset(&pkt, 0, sizeof(pkt));
2668 pkt.num_of_bds = 1 + nr_frags;
2669 pkt.vlan = vlan;
2670 pkt.bd_flags = flags;
2671 pkt.tx_dest = QED_LL2_TX_DEST_NW;
2672 pkt.first_frag = mapping;
2673 pkt.first_frag_len = skb->len;
2674 pkt.cookie = skb;
2675 if (test_bit(QED_MF_UFP_SPECIFIC, &cdev->mf_bits) &&
2676 test_bit(QED_LL2_XMIT_FLAGS_FIP_DISCOVERY, &xmit_flags))
2677 pkt.remove_stag = true;
2678
2679 /* qed_ll2_prepare_tx_packet() may actually send the packet if
2680 * there are no fragments in the skb and subsequently the completion
2681 * routine may run and free the SKB, so no dereferencing the SKB
2682 * beyond this point unless skb has any fragments.
2683 */
2684 rc = qed_ll2_prepare_tx_packet(p_hwfn, cdev->ll2->handle,
2685 &pkt, 1);
2686 if (rc)
2687 goto err;
2688
2689 for (i = 0; i < nr_frags; i++) {
2690 frag = &skb_shinfo(skb)->frags[i];
2691
2692 mapping = skb_frag_dma_map(&cdev->pdev->dev, frag, 0,
2693 skb_frag_size(frag), DMA_TO_DEVICE);
2694
2695 if (unlikely(dma_mapping_error(&cdev->pdev->dev, mapping))) {
2696 DP_NOTICE(cdev,
2697 "Unable to map frag - dropping packet\n");
2698 rc = -ENOMEM;
2699 goto err;
2700 }
2701
2702 rc = qed_ll2_set_fragment_of_tx_packet(p_hwfn,
2703 cdev->ll2->handle,
2704 mapping,
2705 skb_frag_size(frag));
2706
2707 /* if failed not much to do here, partial packet has been posted
2708 * we can't free memory, will need to wait for completion
2709 */
2710 if (rc)
2711 goto err2;
2712 }
2713
2714 return 0;
2715
2716 err:
2717 dma_unmap_single(&cdev->pdev->dev, mapping, skb->len, DMA_TO_DEVICE);
2718 err2:
2719 return rc;
2720 }
2721
qed_ll2_stats(struct qed_dev * cdev,struct qed_ll2_stats * stats)2722 static int qed_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats)
2723 {
2724 bool b_is_storage_eng1 = qed_ll2_is_storage_eng1(cdev);
2725 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev);
2726 int rc;
2727
2728 if (!cdev->ll2)
2729 return -EINVAL;
2730
2731 rc = qed_ll2_get_stats(p_hwfn, cdev->ll2->handle, stats);
2732 if (rc) {
2733 DP_NOTICE(p_hwfn, "Failed to get LL2 stats\n");
2734 return rc;
2735 }
2736
2737 /* In CMT mode, LL2 is always started on engine 0 for a storage PF */
2738 if (b_is_storage_eng1) {
2739 rc = __qed_ll2_get_stats(QED_LEADING_HWFN(cdev),
2740 cdev->ll2->handle, stats);
2741 if (rc) {
2742 DP_NOTICE(QED_LEADING_HWFN(cdev),
2743 "Failed to get LL2 stats on engine 0\n");
2744 return rc;
2745 }
2746 }
2747
2748 return 0;
2749 }
2750
2751 const struct qed_ll2_ops qed_ll2_ops_pass = {
2752 .start = &qed_ll2_start,
2753 .stop = &qed_ll2_stop,
2754 .start_xmit = &qed_ll2_start_xmit,
2755 .register_cb_ops = &qed_ll2_register_cb_ops,
2756 .get_stats = &qed_ll2_stats,
2757 };
2758
qed_ll2_alloc_if(struct qed_dev * cdev)2759 int qed_ll2_alloc_if(struct qed_dev *cdev)
2760 {
2761 cdev->ll2 = kzalloc(sizeof(*cdev->ll2), GFP_KERNEL);
2762 return cdev->ll2 ? 0 : -ENOMEM;
2763 }
2764
qed_ll2_dealloc_if(struct qed_dev * cdev)2765 void qed_ll2_dealloc_if(struct qed_dev *cdev)
2766 {
2767 kfree(cdev->ll2);
2768 cdev->ll2 = NULL;
2769 }
2770