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1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20 
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22 
ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc * desc)23 static u8 *ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc *desc)
24 {
25 	return desc->hdr_status;
26 }
27 
ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc * desc)28 static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc *desc)
29 {
30 	if (!(__le32_to_cpu(desc->mpdu_start.info1) &
31 	    RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID))
32 		return HAL_ENCRYPT_TYPE_OPEN;
33 
34 	return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
35 			 __le32_to_cpu(desc->mpdu_start.info2));
36 }
37 
ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc * desc)38 static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc *desc)
39 {
40 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
41 			 __le32_to_cpu(desc->msdu_start.info2));
42 }
43 
ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc * desc)44 static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc *desc)
45 {
46 	return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
47 			 __le32_to_cpu(desc->msdu_start.info2));
48 }
49 
ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc * desc)50 static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc *desc)
51 {
52 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
53 			   __le32_to_cpu(desc->mpdu_start.info1));
54 }
55 
ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc * desc)56 static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc *desc)
57 {
58 	return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
59 			   __le32_to_cpu(desc->mpdu_start.info1));
60 }
61 
ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff * skb)62 static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff *skb)
63 {
64 	struct ieee80211_hdr *hdr;
65 
66 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
67 	return ieee80211_has_morefrags(hdr->frame_control);
68 }
69 
ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff * skb)70 static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff *skb)
71 {
72 	struct ieee80211_hdr *hdr;
73 
74 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
75 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
76 }
77 
ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc * desc)78 static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc *desc)
79 {
80 	return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
81 			 __le32_to_cpu(desc->mpdu_start.info1));
82 }
83 
ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc * desc)84 static bool ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc *desc)
85 {
86 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
87 			   __le32_to_cpu(desc->attention.info2));
88 }
89 
ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc * desc)90 static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc *desc)
91 {
92 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
93 			   __le32_to_cpu(desc->attention.info1));
94 }
95 
ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc * desc)96 static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc *desc)
97 {
98 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
99 			   __le32_to_cpu(desc->attention.info1));
100 }
101 
ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc * desc)102 static bool ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc *desc)
103 {
104 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
105 			  __le32_to_cpu(desc->attention.info2)) ==
106 		RX_DESC_DECRYPT_STATUS_CODE_OK);
107 }
108 
ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc * desc)109 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc *desc)
110 {
111 	u32 info = __le32_to_cpu(desc->attention.info1);
112 	u32 errmap = 0;
113 
114 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
115 		errmap |= DP_RX_MPDU_ERR_FCS;
116 
117 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
118 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
119 
120 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
121 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
122 
123 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
124 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
125 
126 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
127 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
128 
129 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
130 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
131 
132 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
133 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
134 
135 	return errmap;
136 }
137 
ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc * desc)138 static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc *desc)
139 {
140 	return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
141 			 __le32_to_cpu(desc->msdu_start.info1));
142 }
143 
ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc * desc)144 static u8 ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc *desc)
145 {
146 	return FIELD_GET(RX_MSDU_START_INFO3_SGI,
147 			 __le32_to_cpu(desc->msdu_start.info3));
148 }
149 
ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc * desc)150 static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc *desc)
151 {
152 	return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
153 			 __le32_to_cpu(desc->msdu_start.info3));
154 }
155 
ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc * desc)156 static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc *desc)
157 {
158 	return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
159 			 __le32_to_cpu(desc->msdu_start.info3));
160 }
161 
ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc * desc)162 static u32 ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc *desc)
163 {
164 	return __le32_to_cpu(desc->msdu_start.phy_meta_data);
165 }
166 
ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc * desc)167 static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc *desc)
168 {
169 	return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
170 			 __le32_to_cpu(desc->msdu_start.info3));
171 }
172 
ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc * desc)173 static u8 ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc *desc)
174 {
175 	u8 mimo_ss_bitmap = FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
176 				      __le32_to_cpu(desc->msdu_start.info3));
177 
178 	return hweight8(mimo_ss_bitmap);
179 }
180 
ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc * desc)181 static u8 ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc *desc)
182 {
183 	return FIELD_GET(RX_MPDU_START_INFO2_TID,
184 			 __le32_to_cpu(desc->mpdu_start.info2));
185 }
186 
ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc * desc)187 static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc *desc)
188 {
189 	return __le16_to_cpu(desc->mpdu_start.sw_peer_id);
190 }
191 
ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc * desc)192 static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc *desc)
193 {
194 	return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
195 			 __le32_to_cpu(desc->msdu_end.info2));
196 }
197 
ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc * desc)198 static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc *desc)
199 {
200 	return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
201 			   __le32_to_cpu(desc->msdu_end.info2));
202 }
203 
ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc * desc)204 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc *desc)
205 {
206 	return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
207 			   __le32_to_cpu(desc->msdu_end.info2));
208 }
209 
ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)210 static void ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc *fdesc,
211 					   struct hal_rx_desc *ldesc)
212 {
213 	memcpy((u8 *)&fdesc->msdu_end, (u8 *)&ldesc->msdu_end,
214 	       sizeof(struct rx_msdu_end));
215 	memcpy((u8 *)&fdesc->attention, (u8 *)&ldesc->attention,
216 	       sizeof(struct rx_attention));
217 	memcpy((u8 *)&fdesc->mpdu_end, (u8 *)&ldesc->mpdu_end,
218 	       sizeof(struct rx_mpdu_end));
219 }
220 
ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc * rx_desc)221 static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc *rx_desc)
222 {
223 	struct rx_attention *rx_attn;
224 
225 	rx_attn = &rx_desc->attention;
226 
227 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
228 			 __le32_to_cpu(rx_attn->info1));
229 }
230 
ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc * rx_desc)231 static u32 ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc *rx_desc)
232 {
233 	struct rx_msdu_start *rx_msdu_start;
234 
235 	rx_msdu_start = &rx_desc->msdu_start;
236 
237 	return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
238 			 __le32_to_cpu(rx_msdu_start->info2));
239 }
240 
ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc * rx_desc)241 static u8 *ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc *rx_desc)
242 {
243 	u8 *rx_pkt_hdr;
244 
245 	rx_pkt_hdr = &rx_desc->msdu_payload[0];
246 
247 	return rx_pkt_hdr;
248 }
249 
ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc * rx_desc)250 static bool ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc *rx_desc)
251 {
252 	u32 tlv_tag;
253 
254 	tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG,
255 			    __le32_to_cpu(rx_desc->mpdu_start_tag));
256 
257 	return tlv_tag == HAL_RX_MPDU_START;
258 }
259 
ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc * rx_desc)260 static u32 ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc *rx_desc)
261 {
262 	return __le16_to_cpu(rx_desc->mpdu_start.phy_ppdu_id);
263 }
264 
ath11k_dp_service_mon_ring(struct timer_list * t)265 static void ath11k_dp_service_mon_ring(struct timer_list *t)
266 {
267 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
268 	int i;
269 
270 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
271 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
272 
273 	mod_timer(&ab->mon_reap_timer, jiffies +
274 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
275 }
276 
277 /* Returns number of Rx buffers replenished */
ath11k_dp_rxbufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)278 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
279 			       struct dp_rxdma_ring *rx_ring,
280 			       int req_entries,
281 			       enum hal_rx_buf_return_buf_manager mgr)
282 {
283 	struct hal_srng *srng;
284 	u32 *desc;
285 	struct sk_buff *skb;
286 	int num_free;
287 	int num_remain;
288 	int buf_id;
289 	u32 cookie;
290 	dma_addr_t paddr;
291 
292 	req_entries = min(req_entries, rx_ring->bufs_max);
293 
294 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
295 
296 	spin_lock_bh(&srng->lock);
297 
298 	ath11k_hal_srng_access_begin(ab, srng);
299 
300 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
301 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
302 		req_entries = num_free;
303 
304 	req_entries = min(num_free, req_entries);
305 	num_remain = req_entries;
306 
307 	while (num_remain > 0) {
308 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
309 				    DP_RX_BUFFER_ALIGN_SIZE);
310 		if (!skb)
311 			break;
312 
313 		if (!IS_ALIGNED((unsigned long)skb->data,
314 				DP_RX_BUFFER_ALIGN_SIZE)) {
315 			skb_pull(skb,
316 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
317 				 skb->data);
318 		}
319 
320 		paddr = dma_map_single(ab->dev, skb->data,
321 				       skb->len + skb_tailroom(skb),
322 				       DMA_FROM_DEVICE);
323 		if (dma_mapping_error(ab->dev, paddr))
324 			goto fail_free_skb;
325 
326 		spin_lock_bh(&rx_ring->idr_lock);
327 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
328 				   rx_ring->bufs_max * 3, GFP_ATOMIC);
329 		spin_unlock_bh(&rx_ring->idr_lock);
330 		if (buf_id < 0)
331 			goto fail_dma_unmap;
332 
333 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
334 		if (!desc)
335 			goto fail_idr_remove;
336 
337 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
338 
339 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
340 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
341 
342 		num_remain--;
343 
344 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
345 	}
346 
347 	ath11k_hal_srng_access_end(ab, srng);
348 
349 	spin_unlock_bh(&srng->lock);
350 
351 	return req_entries - num_remain;
352 
353 fail_idr_remove:
354 	spin_lock_bh(&rx_ring->idr_lock);
355 	idr_remove(&rx_ring->bufs_idr, buf_id);
356 	spin_unlock_bh(&rx_ring->idr_lock);
357 fail_dma_unmap:
358 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
359 			 DMA_FROM_DEVICE);
360 fail_free_skb:
361 	dev_kfree_skb_any(skb);
362 
363 	ath11k_hal_srng_access_end(ab, srng);
364 
365 	spin_unlock_bh(&srng->lock);
366 
367 	return req_entries - num_remain;
368 }
369 
ath11k_dp_rxdma_buf_ring_free(struct ath11k * ar,struct dp_rxdma_ring * rx_ring)370 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
371 					 struct dp_rxdma_ring *rx_ring)
372 {
373 	struct ath11k_pdev_dp *dp = &ar->dp;
374 	struct sk_buff *skb;
375 	int buf_id;
376 
377 	spin_lock_bh(&rx_ring->idr_lock);
378 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
379 		idr_remove(&rx_ring->bufs_idr, buf_id);
380 		/* TODO: Understand where internal driver does this dma_unmap of
381 		 * of rxdma_buffer.
382 		 */
383 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
384 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
385 		dev_kfree_skb_any(skb);
386 	}
387 
388 	idr_destroy(&rx_ring->bufs_idr);
389 	spin_unlock_bh(&rx_ring->idr_lock);
390 
391 	/* if rxdma1_enable is false, mon_status_refill_ring
392 	 * isn't setup, so don't clean.
393 	 */
394 	if (!ar->ab->hw_params.rxdma1_enable)
395 		return 0;
396 
397 	rx_ring = &dp->rx_mon_status_refill_ring[0];
398 
399 	spin_lock_bh(&rx_ring->idr_lock);
400 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
401 		idr_remove(&rx_ring->bufs_idr, buf_id);
402 		/* XXX: Understand where internal driver does this dma_unmap of
403 		 * of rxdma_buffer.
404 		 */
405 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
406 				 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
407 		dev_kfree_skb_any(skb);
408 	}
409 
410 	idr_destroy(&rx_ring->bufs_idr);
411 	spin_unlock_bh(&rx_ring->idr_lock);
412 
413 	return 0;
414 }
415 
ath11k_dp_rxdma_pdev_buf_free(struct ath11k * ar)416 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
417 {
418 	struct ath11k_pdev_dp *dp = &ar->dp;
419 	struct ath11k_base *ab = ar->ab;
420 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
421 	int i;
422 
423 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
424 
425 	rx_ring = &dp->rxdma_mon_buf_ring;
426 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
427 
428 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
429 		rx_ring = &dp->rx_mon_status_refill_ring[i];
430 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
431 	}
432 
433 	return 0;
434 }
435 
ath11k_dp_rxdma_ring_buf_setup(struct ath11k * ar,struct dp_rxdma_ring * rx_ring,u32 ringtype)436 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
437 					  struct dp_rxdma_ring *rx_ring,
438 					  u32 ringtype)
439 {
440 	struct ath11k_pdev_dp *dp = &ar->dp;
441 	int num_entries;
442 
443 	num_entries = rx_ring->refill_buf_ring.size /
444 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
445 
446 	rx_ring->bufs_max = num_entries;
447 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
448 				   HAL_RX_BUF_RBM_SW3_BM);
449 	return 0;
450 }
451 
ath11k_dp_rxdma_pdev_buf_setup(struct ath11k * ar)452 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
453 {
454 	struct ath11k_pdev_dp *dp = &ar->dp;
455 	struct ath11k_base *ab = ar->ab;
456 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
457 	int i;
458 
459 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
460 
461 	if (ar->ab->hw_params.rxdma1_enable) {
462 		rx_ring = &dp->rxdma_mon_buf_ring;
463 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
464 	}
465 
466 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
467 		rx_ring = &dp->rx_mon_status_refill_ring[i];
468 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
469 	}
470 
471 	return 0;
472 }
473 
ath11k_dp_rx_pdev_srng_free(struct ath11k * ar)474 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
475 {
476 	struct ath11k_pdev_dp *dp = &ar->dp;
477 	struct ath11k_base *ab = ar->ab;
478 	int i;
479 
480 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
481 
482 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
483 		if (ab->hw_params.rx_mac_buf_ring)
484 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
485 
486 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
487 		ath11k_dp_srng_cleanup(ab,
488 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
489 	}
490 
491 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
492 }
493 
ath11k_dp_pdev_reo_cleanup(struct ath11k_base * ab)494 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
495 {
496 	struct ath11k_dp *dp = &ab->dp;
497 	int i;
498 
499 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
500 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
501 }
502 
ath11k_dp_pdev_reo_setup(struct ath11k_base * ab)503 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
504 {
505 	struct ath11k_dp *dp = &ab->dp;
506 	int ret;
507 	int i;
508 
509 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
510 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
511 					   HAL_REO_DST, i, 0,
512 					   DP_REO_DST_RING_SIZE);
513 		if (ret) {
514 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
515 			goto err_reo_cleanup;
516 		}
517 	}
518 
519 	return 0;
520 
521 err_reo_cleanup:
522 	ath11k_dp_pdev_reo_cleanup(ab);
523 
524 	return ret;
525 }
526 
ath11k_dp_rx_pdev_srng_alloc(struct ath11k * ar)527 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
528 {
529 	struct ath11k_pdev_dp *dp = &ar->dp;
530 	struct ath11k_base *ab = ar->ab;
531 	struct dp_srng *srng = NULL;
532 	int i;
533 	int ret;
534 
535 	ret = ath11k_dp_srng_setup(ar->ab,
536 				   &dp->rx_refill_buf_ring.refill_buf_ring,
537 				   HAL_RXDMA_BUF, 0,
538 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
539 	if (ret) {
540 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
541 		return ret;
542 	}
543 
544 	if (ar->ab->hw_params.rx_mac_buf_ring) {
545 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
546 			ret = ath11k_dp_srng_setup(ar->ab,
547 						   &dp->rx_mac_buf_ring[i],
548 						   HAL_RXDMA_BUF, 1,
549 						   dp->mac_id + i, 1024);
550 			if (ret) {
551 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
552 					    i);
553 				return ret;
554 			}
555 		}
556 	}
557 
558 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
559 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
560 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
561 					   DP_RXDMA_ERR_DST_RING_SIZE);
562 		if (ret) {
563 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
564 			return ret;
565 		}
566 	}
567 
568 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
569 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
570 		ret = ath11k_dp_srng_setup(ar->ab,
571 					   srng,
572 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
573 					   DP_RXDMA_MON_STATUS_RING_SIZE);
574 		if (ret) {
575 			ath11k_warn(ar->ab,
576 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
577 			return ret;
578 		}
579 	}
580 
581 	/* if rxdma1_enable is false, then it doesn't need
582 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
583 	 * and rxdma_mon_desc_ring.
584 	 * init reap timer for QCA6390.
585 	 */
586 	if (!ar->ab->hw_params.rxdma1_enable) {
587 		//init mon status buffer reap timer
588 		timer_setup(&ar->ab->mon_reap_timer,
589 			    ath11k_dp_service_mon_ring, 0);
590 		return 0;
591 	}
592 
593 	ret = ath11k_dp_srng_setup(ar->ab,
594 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
595 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
596 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
597 	if (ret) {
598 		ath11k_warn(ar->ab,
599 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
600 		return ret;
601 	}
602 
603 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
604 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
605 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
606 	if (ret) {
607 		ath11k_warn(ar->ab,
608 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
609 		return ret;
610 	}
611 
612 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
613 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
614 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
615 	if (ret) {
616 		ath11k_warn(ar->ab,
617 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
618 		return ret;
619 	}
620 
621 	return 0;
622 }
623 
ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base * ab)624 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
625 {
626 	struct ath11k_dp *dp = &ab->dp;
627 	struct dp_reo_cmd *cmd, *tmp;
628 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
629 
630 	spin_lock_bh(&dp->reo_cmd_lock);
631 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
632 		list_del(&cmd->list);
633 		dma_unmap_single(ab->dev, cmd->data.paddr,
634 				 cmd->data.size, DMA_BIDIRECTIONAL);
635 		kfree(cmd->data.vaddr);
636 		kfree(cmd);
637 	}
638 
639 	list_for_each_entry_safe(cmd_cache, tmp_cache,
640 				 &dp->reo_cmd_cache_flush_list, list) {
641 		list_del(&cmd_cache->list);
642 		dp->reo_cmd_cache_flush_count--;
643 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
644 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
645 		kfree(cmd_cache->data.vaddr);
646 		kfree(cmd_cache);
647 	}
648 	spin_unlock_bh(&dp->reo_cmd_lock);
649 }
650 
ath11k_dp_reo_cmd_free(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)651 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
652 				   enum hal_reo_cmd_status status)
653 {
654 	struct dp_rx_tid *rx_tid = ctx;
655 
656 	if (status != HAL_REO_CMD_SUCCESS)
657 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
658 			    rx_tid->tid, status);
659 
660 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
661 			 DMA_BIDIRECTIONAL);
662 	kfree(rx_tid->vaddr);
663 }
664 
ath11k_dp_reo_cache_flush(struct ath11k_base * ab,struct dp_rx_tid * rx_tid)665 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
666 				      struct dp_rx_tid *rx_tid)
667 {
668 	struct ath11k_hal_reo_cmd cmd = {0};
669 	unsigned long tot_desc_sz, desc_sz;
670 	int ret;
671 
672 	tot_desc_sz = rx_tid->size;
673 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
674 
675 	while (tot_desc_sz > desc_sz) {
676 		tot_desc_sz -= desc_sz;
677 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
678 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
679 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
680 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
681 						NULL);
682 		if (ret)
683 			ath11k_warn(ab,
684 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
685 				    rx_tid->tid, ret);
686 	}
687 
688 	memset(&cmd, 0, sizeof(cmd));
689 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
690 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
691 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
692 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
693 					HAL_REO_CMD_FLUSH_CACHE,
694 					&cmd, ath11k_dp_reo_cmd_free);
695 	if (ret) {
696 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
697 			   rx_tid->tid, ret);
698 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
699 				 DMA_BIDIRECTIONAL);
700 		kfree(rx_tid->vaddr);
701 	}
702 }
703 
ath11k_dp_rx_tid_del_func(struct ath11k_dp * dp,void * ctx,enum hal_reo_cmd_status status)704 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
705 				      enum hal_reo_cmd_status status)
706 {
707 	struct ath11k_base *ab = dp->ab;
708 	struct dp_rx_tid *rx_tid = ctx;
709 	struct dp_reo_cache_flush_elem *elem, *tmp;
710 
711 	if (status == HAL_REO_CMD_DRAIN) {
712 		goto free_desc;
713 	} else if (status != HAL_REO_CMD_SUCCESS) {
714 		/* Shouldn't happen! Cleanup in case of other failure? */
715 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
716 			    rx_tid->tid, status);
717 		return;
718 	}
719 
720 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
721 	if (!elem)
722 		goto free_desc;
723 
724 	elem->ts = jiffies;
725 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
726 
727 	spin_lock_bh(&dp->reo_cmd_lock);
728 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
729 	dp->reo_cmd_cache_flush_count++;
730 
731 	/* Flush and invalidate aged REO desc from HW cache */
732 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
733 				 list) {
734 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
735 		    time_after(jiffies, elem->ts +
736 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
737 			list_del(&elem->list);
738 			dp->reo_cmd_cache_flush_count--;
739 			spin_unlock_bh(&dp->reo_cmd_lock);
740 
741 			ath11k_dp_reo_cache_flush(ab, &elem->data);
742 			kfree(elem);
743 			spin_lock_bh(&dp->reo_cmd_lock);
744 		}
745 	}
746 	spin_unlock_bh(&dp->reo_cmd_lock);
747 
748 	return;
749 free_desc:
750 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
751 			 DMA_BIDIRECTIONAL);
752 	kfree(rx_tid->vaddr);
753 }
754 
ath11k_peer_rx_tid_delete(struct ath11k * ar,struct ath11k_peer * peer,u8 tid)755 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
756 			       struct ath11k_peer *peer, u8 tid)
757 {
758 	struct ath11k_hal_reo_cmd cmd = {0};
759 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
760 	int ret;
761 
762 	if (!rx_tid->active)
763 		return;
764 
765 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
766 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
767 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
768 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
769 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
770 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
771 					ath11k_dp_rx_tid_del_func);
772 	if (ret) {
773 		ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
774 			   tid, ret);
775 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
776 				 DMA_BIDIRECTIONAL);
777 		kfree(rx_tid->vaddr);
778 	}
779 
780 	rx_tid->active = false;
781 }
782 
ath11k_dp_rx_link_desc_return(struct ath11k_base * ab,u32 * link_desc,enum hal_wbm_rel_bm_act action)783 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
784 					 u32 *link_desc,
785 					 enum hal_wbm_rel_bm_act action)
786 {
787 	struct ath11k_dp *dp = &ab->dp;
788 	struct hal_srng *srng;
789 	u32 *desc;
790 	int ret = 0;
791 
792 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
793 
794 	spin_lock_bh(&srng->lock);
795 
796 	ath11k_hal_srng_access_begin(ab, srng);
797 
798 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
799 	if (!desc) {
800 		ret = -ENOBUFS;
801 		goto exit;
802 	}
803 
804 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
805 					 action);
806 
807 exit:
808 	ath11k_hal_srng_access_end(ab, srng);
809 
810 	spin_unlock_bh(&srng->lock);
811 
812 	return ret;
813 }
814 
ath11k_dp_rx_frags_cleanup(struct dp_rx_tid * rx_tid,bool rel_link_desc)815 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
816 {
817 	struct ath11k_base *ab = rx_tid->ab;
818 
819 	lockdep_assert_held(&ab->base_lock);
820 
821 	if (rx_tid->dst_ring_desc) {
822 		if (rel_link_desc)
823 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
824 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
825 		kfree(rx_tid->dst_ring_desc);
826 		rx_tid->dst_ring_desc = NULL;
827 	}
828 
829 	rx_tid->cur_sn = 0;
830 	rx_tid->last_frag_no = 0;
831 	rx_tid->rx_frag_bitmap = 0;
832 	__skb_queue_purge(&rx_tid->rx_frags);
833 }
834 
ath11k_peer_frags_flush(struct ath11k * ar,struct ath11k_peer * peer)835 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
836 {
837 	struct dp_rx_tid *rx_tid;
838 	int i;
839 
840 	lockdep_assert_held(&ar->ab->base_lock);
841 
842 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
843 		rx_tid = &peer->rx_tid[i];
844 
845 		spin_unlock_bh(&ar->ab->base_lock);
846 		del_timer_sync(&rx_tid->frag_timer);
847 		spin_lock_bh(&ar->ab->base_lock);
848 
849 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
850 	}
851 }
852 
ath11k_peer_rx_tid_cleanup(struct ath11k * ar,struct ath11k_peer * peer)853 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
854 {
855 	struct dp_rx_tid *rx_tid;
856 	int i;
857 
858 	lockdep_assert_held(&ar->ab->base_lock);
859 
860 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
861 		rx_tid = &peer->rx_tid[i];
862 
863 		ath11k_peer_rx_tid_delete(ar, peer, i);
864 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
865 
866 		spin_unlock_bh(&ar->ab->base_lock);
867 		del_timer_sync(&rx_tid->frag_timer);
868 		spin_lock_bh(&ar->ab->base_lock);
869 	}
870 }
871 
ath11k_peer_rx_tid_reo_update(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,u32 ba_win_sz,u16 ssn,bool update_ssn)872 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
873 					 struct ath11k_peer *peer,
874 					 struct dp_rx_tid *rx_tid,
875 					 u32 ba_win_sz, u16 ssn,
876 					 bool update_ssn)
877 {
878 	struct ath11k_hal_reo_cmd cmd = {0};
879 	int ret;
880 
881 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
882 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
883 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
884 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
885 	cmd.ba_window_size = ba_win_sz;
886 
887 	if (update_ssn) {
888 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
889 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
890 	}
891 
892 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
893 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
894 					NULL);
895 	if (ret) {
896 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
897 			    rx_tid->tid, ret);
898 		return ret;
899 	}
900 
901 	rx_tid->ba_win_sz = ba_win_sz;
902 
903 	return 0;
904 }
905 
ath11k_dp_rx_tid_mem_free(struct ath11k_base * ab,const u8 * peer_mac,int vdev_id,u8 tid)906 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
907 				      const u8 *peer_mac, int vdev_id, u8 tid)
908 {
909 	struct ath11k_peer *peer;
910 	struct dp_rx_tid *rx_tid;
911 
912 	spin_lock_bh(&ab->base_lock);
913 
914 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
915 	if (!peer) {
916 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
917 		goto unlock_exit;
918 	}
919 
920 	rx_tid = &peer->rx_tid[tid];
921 	if (!rx_tid->active)
922 		goto unlock_exit;
923 
924 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
925 			 DMA_BIDIRECTIONAL);
926 	kfree(rx_tid->vaddr);
927 
928 	rx_tid->active = false;
929 
930 unlock_exit:
931 	spin_unlock_bh(&ab->base_lock);
932 }
933 
ath11k_peer_rx_tid_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id,u8 tid,u32 ba_win_sz,u16 ssn,enum hal_pn_type pn_type)934 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
935 			     u8 tid, u32 ba_win_sz, u16 ssn,
936 			     enum hal_pn_type pn_type)
937 {
938 	struct ath11k_base *ab = ar->ab;
939 	struct ath11k_peer *peer;
940 	struct dp_rx_tid *rx_tid;
941 	u32 hw_desc_sz;
942 	u32 *addr_aligned;
943 	void *vaddr;
944 	dma_addr_t paddr;
945 	int ret;
946 
947 	spin_lock_bh(&ab->base_lock);
948 
949 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
950 	if (!peer) {
951 		ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
952 		spin_unlock_bh(&ab->base_lock);
953 		return -ENOENT;
954 	}
955 
956 	rx_tid = &peer->rx_tid[tid];
957 	/* Update the tid queue if it is already setup */
958 	if (rx_tid->active) {
959 		paddr = rx_tid->paddr;
960 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
961 						    ba_win_sz, ssn, true);
962 		spin_unlock_bh(&ab->base_lock);
963 		if (ret) {
964 			ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
965 			return ret;
966 		}
967 
968 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
969 							     peer_mac, paddr,
970 							     tid, 1, ba_win_sz);
971 		if (ret)
972 			ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
973 				    tid, ret);
974 		return ret;
975 	}
976 
977 	rx_tid->tid = tid;
978 
979 	rx_tid->ba_win_sz = ba_win_sz;
980 
981 	/* TODO: Optimize the memory allocation for qos tid based on the
982 	 * the actual BA window size in REO tid update path.
983 	 */
984 	if (tid == HAL_DESC_REO_NON_QOS_TID)
985 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
986 	else
987 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
988 
989 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
990 	if (!vaddr) {
991 		spin_unlock_bh(&ab->base_lock);
992 		return -ENOMEM;
993 	}
994 
995 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
996 
997 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
998 				   ssn, pn_type);
999 
1000 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1001 			       DMA_BIDIRECTIONAL);
1002 
1003 	ret = dma_mapping_error(ab->dev, paddr);
1004 	if (ret) {
1005 		spin_unlock_bh(&ab->base_lock);
1006 		goto err_mem_free;
1007 	}
1008 
1009 	rx_tid->vaddr = vaddr;
1010 	rx_tid->paddr = paddr;
1011 	rx_tid->size = hw_desc_sz;
1012 	rx_tid->active = true;
1013 
1014 	spin_unlock_bh(&ab->base_lock);
1015 
1016 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1017 						     paddr, tid, 1, ba_win_sz);
1018 	if (ret) {
1019 		ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1020 			    tid, ret);
1021 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1022 	}
1023 
1024 	return ret;
1025 
1026 err_mem_free:
1027 	kfree(vaddr);
1028 
1029 	return ret;
1030 }
1031 
ath11k_dp_rx_ampdu_start(struct ath11k * ar,struct ieee80211_ampdu_params * params)1032 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1033 			     struct ieee80211_ampdu_params *params)
1034 {
1035 	struct ath11k_base *ab = ar->ab;
1036 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1037 	int vdev_id = arsta->arvif->vdev_id;
1038 	int ret;
1039 
1040 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1041 				       params->tid, params->buf_size,
1042 				       params->ssn, arsta->pn_type);
1043 	if (ret)
1044 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1045 
1046 	return ret;
1047 }
1048 
ath11k_dp_rx_ampdu_stop(struct ath11k * ar,struct ieee80211_ampdu_params * params)1049 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1050 			    struct ieee80211_ampdu_params *params)
1051 {
1052 	struct ath11k_base *ab = ar->ab;
1053 	struct ath11k_peer *peer;
1054 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1055 	int vdev_id = arsta->arvif->vdev_id;
1056 	dma_addr_t paddr;
1057 	bool active;
1058 	int ret;
1059 
1060 	spin_lock_bh(&ab->base_lock);
1061 
1062 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1063 	if (!peer) {
1064 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1065 		spin_unlock_bh(&ab->base_lock);
1066 		return -ENOENT;
1067 	}
1068 
1069 	paddr = peer->rx_tid[params->tid].paddr;
1070 	active = peer->rx_tid[params->tid].active;
1071 
1072 	if (!active) {
1073 		spin_unlock_bh(&ab->base_lock);
1074 		return 0;
1075 	}
1076 
1077 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1078 	spin_unlock_bh(&ab->base_lock);
1079 	if (ret) {
1080 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1081 			    params->tid, ret);
1082 		return ret;
1083 	}
1084 
1085 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1086 						     params->sta->addr, paddr,
1087 						     params->tid, 1, 1);
1088 	if (ret)
1089 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1090 			    ret);
1091 
1092 	return ret;
1093 }
1094 
ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif * arvif,const u8 * peer_addr,enum set_key_cmd key_cmd,struct ieee80211_key_conf * key)1095 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1096 				       const u8 *peer_addr,
1097 				       enum set_key_cmd key_cmd,
1098 				       struct ieee80211_key_conf *key)
1099 {
1100 	struct ath11k *ar = arvif->ar;
1101 	struct ath11k_base *ab = ar->ab;
1102 	struct ath11k_hal_reo_cmd cmd = {0};
1103 	struct ath11k_peer *peer;
1104 	struct dp_rx_tid *rx_tid;
1105 	u8 tid;
1106 	int ret = 0;
1107 
1108 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1109 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1110 	 * for now.
1111 	 */
1112 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1113 		return 0;
1114 
1115 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1116 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1117 		    HAL_REO_CMD_UPD0_PN_SIZE |
1118 		    HAL_REO_CMD_UPD0_PN_VALID |
1119 		    HAL_REO_CMD_UPD0_PN_CHECK |
1120 		    HAL_REO_CMD_UPD0_SVLD;
1121 
1122 	switch (key->cipher) {
1123 	case WLAN_CIPHER_SUITE_TKIP:
1124 	case WLAN_CIPHER_SUITE_CCMP:
1125 	case WLAN_CIPHER_SUITE_CCMP_256:
1126 	case WLAN_CIPHER_SUITE_GCMP:
1127 	case WLAN_CIPHER_SUITE_GCMP_256:
1128 		if (key_cmd == SET_KEY) {
1129 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1130 			cmd.pn_size = 48;
1131 		}
1132 		break;
1133 	default:
1134 		break;
1135 	}
1136 
1137 	spin_lock_bh(&ab->base_lock);
1138 
1139 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1140 	if (!peer) {
1141 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1142 		spin_unlock_bh(&ab->base_lock);
1143 		return -ENOENT;
1144 	}
1145 
1146 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1147 		rx_tid = &peer->rx_tid[tid];
1148 		if (!rx_tid->active)
1149 			continue;
1150 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1151 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1152 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1153 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1154 						&cmd, NULL);
1155 		if (ret) {
1156 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1157 				    tid, ret);
1158 			break;
1159 		}
1160 	}
1161 
1162 	spin_unlock_bh(&ar->ab->base_lock);
1163 
1164 	return ret;
1165 }
1166 
ath11k_get_ppdu_user_index(struct htt_ppdu_stats * ppdu_stats,u16 peer_id)1167 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1168 					     u16 peer_id)
1169 {
1170 	int i;
1171 
1172 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1173 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1174 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1175 				return i;
1176 		} else {
1177 			return i;
1178 		}
1179 	}
1180 
1181 	return -EINVAL;
1182 }
1183 
ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base * ab,u16 tag,u16 len,const void * ptr,void * data)1184 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1185 					   u16 tag, u16 len, const void *ptr,
1186 					   void *data)
1187 {
1188 	struct htt_ppdu_stats_info *ppdu_info;
1189 	struct htt_ppdu_user_stats *user_stats;
1190 	int cur_user;
1191 	u16 peer_id;
1192 
1193 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1194 
1195 	switch (tag) {
1196 	case HTT_PPDU_STATS_TAG_COMMON:
1197 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1198 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1199 				    len, tag);
1200 			return -EINVAL;
1201 		}
1202 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1203 		       sizeof(struct htt_ppdu_stats_common));
1204 		break;
1205 	case HTT_PPDU_STATS_TAG_USR_RATE:
1206 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1207 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1208 				    len, tag);
1209 			return -EINVAL;
1210 		}
1211 
1212 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1213 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1214 						      peer_id);
1215 		if (cur_user < 0)
1216 			return -EINVAL;
1217 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1218 		user_stats->peer_id = peer_id;
1219 		user_stats->is_valid_peer_id = true;
1220 		memcpy((void *)&user_stats->rate, ptr,
1221 		       sizeof(struct htt_ppdu_stats_user_rate));
1222 		user_stats->tlv_flags |= BIT(tag);
1223 		break;
1224 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1225 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1226 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1227 				    len, tag);
1228 			return -EINVAL;
1229 		}
1230 
1231 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1232 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1233 						      peer_id);
1234 		if (cur_user < 0)
1235 			return -EINVAL;
1236 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1237 		user_stats->peer_id = peer_id;
1238 		user_stats->is_valid_peer_id = true;
1239 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1240 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1241 		user_stats->tlv_flags |= BIT(tag);
1242 		break;
1243 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1244 		if (len <
1245 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1246 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1247 				    len, tag);
1248 			return -EINVAL;
1249 		}
1250 
1251 		peer_id =
1252 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1253 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1254 						      peer_id);
1255 		if (cur_user < 0)
1256 			return -EINVAL;
1257 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1258 		user_stats->peer_id = peer_id;
1259 		user_stats->is_valid_peer_id = true;
1260 		memcpy((void *)&user_stats->ack_ba, ptr,
1261 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1262 		user_stats->tlv_flags |= BIT(tag);
1263 		break;
1264 	}
1265 	return 0;
1266 }
1267 
ath11k_dp_htt_tlv_iter(struct ath11k_base * ab,const void * ptr,size_t len,int (* iter)(struct ath11k_base * ar,u16 tag,u16 len,const void * ptr,void * data),void * data)1268 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1269 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1270 				       const void *ptr, void *data),
1271 			   void *data)
1272 {
1273 	const struct htt_tlv *tlv;
1274 	const void *begin = ptr;
1275 	u16 tlv_tag, tlv_len;
1276 	int ret = -EINVAL;
1277 
1278 	while (len > 0) {
1279 		if (len < sizeof(*tlv)) {
1280 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1281 				   ptr - begin, len, sizeof(*tlv));
1282 			return -EINVAL;
1283 		}
1284 		tlv = (struct htt_tlv *)ptr;
1285 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1286 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1287 		ptr += sizeof(*tlv);
1288 		len -= sizeof(*tlv);
1289 
1290 		if (tlv_len > len) {
1291 			ath11k_err(ab, "htt tlv parse failure of tag %hhu at byte %zd (%zu bytes left, %hhu expected)\n",
1292 				   tlv_tag, ptr - begin, len, tlv_len);
1293 			return -EINVAL;
1294 		}
1295 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1296 		if (ret == -ENOMEM)
1297 			return ret;
1298 
1299 		ptr += tlv_len;
1300 		len -= tlv_len;
1301 	}
1302 	return 0;
1303 }
1304 
ath11k_he_gi_to_nl80211_he_gi(u8 sgi)1305 static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi)
1306 {
1307 	u32 ret = 0;
1308 
1309 	switch (sgi) {
1310 	case RX_MSDU_START_SGI_0_8_US:
1311 		ret = NL80211_RATE_INFO_HE_GI_0_8;
1312 		break;
1313 	case RX_MSDU_START_SGI_1_6_US:
1314 		ret = NL80211_RATE_INFO_HE_GI_1_6;
1315 		break;
1316 	case RX_MSDU_START_SGI_3_2_US:
1317 		ret = NL80211_RATE_INFO_HE_GI_3_2;
1318 		break;
1319 	}
1320 
1321 	return ret;
1322 }
1323 
1324 static void
ath11k_update_per_peer_tx_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats,u8 user)1325 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1326 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1327 {
1328 	struct ath11k_base *ab = ar->ab;
1329 	struct ath11k_peer *peer;
1330 	struct ieee80211_sta *sta;
1331 	struct ath11k_sta *arsta;
1332 	struct htt_ppdu_stats_user_rate *user_rate;
1333 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1334 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1335 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1336 	int ret;
1337 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1338 	u32 succ_bytes = 0;
1339 	u16 rate = 0, succ_pkts = 0;
1340 	u32 tx_duration = 0;
1341 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1342 	bool is_ampdu = false;
1343 
1344 	if (!usr_stats)
1345 		return;
1346 
1347 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1348 		return;
1349 
1350 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1351 		is_ampdu =
1352 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1353 
1354 	if (usr_stats->tlv_flags &
1355 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1356 		succ_bytes = usr_stats->ack_ba.success_bytes;
1357 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1358 				      usr_stats->ack_ba.info);
1359 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1360 				usr_stats->ack_ba.info);
1361 	}
1362 
1363 	if (common->fes_duration_us)
1364 		tx_duration = common->fes_duration_us;
1365 
1366 	user_rate = &usr_stats->rate;
1367 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1368 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1369 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1370 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1371 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1372 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1373 
1374 	/* Note: If host configured fixed rates and in some other special
1375 	 * cases, the broadcast/management frames are sent in different rates.
1376 	 * Firmware rate's control to be skipped for this?
1377 	 */
1378 
1379 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) {
1380 		ath11k_warn(ab, "Invalid HE mcs %hhd peer stats",  mcs);
1381 		return;
1382 	}
1383 
1384 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1385 		ath11k_warn(ab, "Invalid HE mcs %hhd peer stats",  mcs);
1386 		return;
1387 	}
1388 
1389 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1390 		ath11k_warn(ab, "Invalid VHT mcs %hhd peer stats",  mcs);
1391 		return;
1392 	}
1393 
1394 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1395 		ath11k_warn(ab, "Invalid HT mcs %hhd nss %hhd peer stats",
1396 			    mcs, nss);
1397 		return;
1398 	}
1399 
1400 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1401 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1402 							    flags,
1403 							    &rate_idx,
1404 							    &rate);
1405 		if (ret < 0)
1406 			return;
1407 	}
1408 
1409 	rcu_read_lock();
1410 	spin_lock_bh(&ab->base_lock);
1411 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1412 
1413 	if (!peer || !peer->sta) {
1414 		spin_unlock_bh(&ab->base_lock);
1415 		rcu_read_unlock();
1416 		return;
1417 	}
1418 
1419 	sta = peer->sta;
1420 	arsta = (struct ath11k_sta *)sta->drv_priv;
1421 
1422 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1423 
1424 	switch (flags) {
1425 	case WMI_RATE_PREAMBLE_OFDM:
1426 		arsta->txrate.legacy = rate;
1427 		break;
1428 	case WMI_RATE_PREAMBLE_CCK:
1429 		arsta->txrate.legacy = rate;
1430 		break;
1431 	case WMI_RATE_PREAMBLE_HT:
1432 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1433 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1434 		if (sgi)
1435 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1436 		break;
1437 	case WMI_RATE_PREAMBLE_VHT:
1438 		arsta->txrate.mcs = mcs;
1439 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1440 		if (sgi)
1441 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1442 		break;
1443 	case WMI_RATE_PREAMBLE_HE:
1444 		arsta->txrate.mcs = mcs;
1445 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1446 		arsta->txrate.he_dcm = dcm;
1447 		arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
1448 		arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(
1449 						(user_rate->ru_end -
1450 						 user_rate->ru_start) + 1);
1451 		break;
1452 	}
1453 
1454 	arsta->txrate.nss = nss;
1455 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1456 	arsta->tx_duration += tx_duration;
1457 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1458 
1459 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1460 	 * So skip peer stats update for mgmt packets.
1461 	 */
1462 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1463 		memset(peer_stats, 0, sizeof(*peer_stats));
1464 		peer_stats->succ_pkts = succ_pkts;
1465 		peer_stats->succ_bytes = succ_bytes;
1466 		peer_stats->is_ampdu = is_ampdu;
1467 		peer_stats->duration = tx_duration;
1468 		peer_stats->ba_fails =
1469 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1470 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1471 
1472 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1473 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1474 	}
1475 
1476 	spin_unlock_bh(&ab->base_lock);
1477 	rcu_read_unlock();
1478 }
1479 
ath11k_htt_update_ppdu_stats(struct ath11k * ar,struct htt_ppdu_stats * ppdu_stats)1480 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1481 					 struct htt_ppdu_stats *ppdu_stats)
1482 {
1483 	u8 user;
1484 
1485 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1486 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1487 }
1488 
1489 static
ath11k_dp_htt_get_ppdu_desc(struct ath11k * ar,u32 ppdu_id)1490 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1491 							u32 ppdu_id)
1492 {
1493 	struct htt_ppdu_stats_info *ppdu_info;
1494 
1495 	spin_lock_bh(&ar->data_lock);
1496 	if (!list_empty(&ar->ppdu_stats_info)) {
1497 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1498 			if (ppdu_info->ppdu_id == ppdu_id) {
1499 				spin_unlock_bh(&ar->data_lock);
1500 				return ppdu_info;
1501 			}
1502 		}
1503 
1504 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1505 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1506 						     typeof(*ppdu_info), list);
1507 			list_del(&ppdu_info->list);
1508 			ar->ppdu_stat_list_depth--;
1509 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1510 			kfree(ppdu_info);
1511 		}
1512 	}
1513 	spin_unlock_bh(&ar->data_lock);
1514 
1515 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1516 	if (!ppdu_info)
1517 		return NULL;
1518 
1519 	spin_lock_bh(&ar->data_lock);
1520 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1521 	ar->ppdu_stat_list_depth++;
1522 	spin_unlock_bh(&ar->data_lock);
1523 
1524 	return ppdu_info;
1525 }
1526 
ath11k_htt_pull_ppdu_stats(struct ath11k_base * ab,struct sk_buff * skb)1527 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1528 				      struct sk_buff *skb)
1529 {
1530 	struct ath11k_htt_ppdu_stats_msg *msg;
1531 	struct htt_ppdu_stats_info *ppdu_info;
1532 	struct ath11k *ar;
1533 	int ret;
1534 	u8 pdev_id;
1535 	u32 ppdu_id, len;
1536 
1537 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1538 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1539 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1540 	ppdu_id = msg->ppdu_id;
1541 
1542 	rcu_read_lock();
1543 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1544 	if (!ar) {
1545 		ret = -EINVAL;
1546 		goto exit;
1547 	}
1548 
1549 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1550 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1551 
1552 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1553 	if (!ppdu_info) {
1554 		ret = -EINVAL;
1555 		goto exit;
1556 	}
1557 
1558 	ppdu_info->ppdu_id = ppdu_id;
1559 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1560 				     ath11k_htt_tlv_ppdu_stats_parse,
1561 				     (void *)ppdu_info);
1562 	if (ret) {
1563 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1564 		goto exit;
1565 	}
1566 
1567 exit:
1568 	rcu_read_unlock();
1569 
1570 	return ret;
1571 }
1572 
ath11k_htt_pktlog(struct ath11k_base * ab,struct sk_buff * skb)1573 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1574 {
1575 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1576 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1577 	struct ath11k *ar;
1578 	u8 pdev_id;
1579 
1580 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1581 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1582 	if (!ar) {
1583 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1584 		return;
1585 	}
1586 
1587 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1588 				ar->ab->pktlog_defs_checksum);
1589 }
1590 
ath11k_htt_backpressure_event_handler(struct ath11k_base * ab,struct sk_buff * skb)1591 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1592 						  struct sk_buff *skb)
1593 {
1594 	u32 *data = (u32 *)skb->data;
1595 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1596 	u16 hp, tp;
1597 	u32 backpressure_time;
1598 	struct ath11k_bp_stats *bp_stats;
1599 
1600 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1601 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1602 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1603 	++data;
1604 
1605 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1606 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1607 	++data;
1608 
1609 	backpressure_time = *data;
1610 
1611 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1612 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1613 
1614 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1615 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1616 			return;
1617 
1618 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1619 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1620 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1621 
1622 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1623 			return;
1624 
1625 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1626 	} else {
1627 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1628 			    ring_type);
1629 		return;
1630 	}
1631 
1632 	spin_lock_bh(&ab->base_lock);
1633 	bp_stats->hp = hp;
1634 	bp_stats->tp = tp;
1635 	bp_stats->count++;
1636 	bp_stats->jiffies = jiffies;
1637 	spin_unlock_bh(&ab->base_lock);
1638 }
1639 
ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base * ab,struct sk_buff * skb)1640 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1641 				       struct sk_buff *skb)
1642 {
1643 	struct ath11k_dp *dp = &ab->dp;
1644 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1645 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1646 	u16 peer_id;
1647 	u8 vdev_id;
1648 	u8 mac_addr[ETH_ALEN];
1649 	u16 peer_mac_h16;
1650 	u16 ast_hash;
1651 
1652 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1653 
1654 	switch (type) {
1655 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1656 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1657 						  resp->version_msg.version);
1658 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1659 						  resp->version_msg.version);
1660 		complete(&dp->htt_tgt_version_received);
1661 		break;
1662 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1663 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1664 				    resp->peer_map_ev.info);
1665 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1666 				    resp->peer_map_ev.info);
1667 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1668 					 resp->peer_map_ev.info1);
1669 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1670 				       peer_mac_h16, mac_addr);
1671 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0);
1672 		break;
1673 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1674 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1675 				    resp->peer_map_ev.info);
1676 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1677 				    resp->peer_map_ev.info);
1678 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1679 					 resp->peer_map_ev.info1);
1680 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1681 				       peer_mac_h16, mac_addr);
1682 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1683 				     resp->peer_map_ev.info2);
1684 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash);
1685 		break;
1686 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1687 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1688 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1689 				    resp->peer_unmap_ev.info);
1690 		ath11k_peer_unmap_event(ab, peer_id);
1691 		break;
1692 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1693 		ath11k_htt_pull_ppdu_stats(ab, skb);
1694 		break;
1695 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1696 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1697 		break;
1698 	case HTT_T2H_MSG_TYPE_PKTLOG:
1699 		ath11k_htt_pktlog(ab, skb);
1700 		break;
1701 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1702 		ath11k_htt_backpressure_event_handler(ab, skb);
1703 		break;
1704 	default:
1705 		ath11k_warn(ab, "htt event %d not handled\n", type);
1706 		break;
1707 	}
1708 
1709 	dev_kfree_skb_any(skb);
1710 }
1711 
ath11k_dp_rx_msdu_coalesce(struct ath11k * ar,struct sk_buff_head * msdu_list,struct sk_buff * first,struct sk_buff * last,u8 l3pad_bytes,int msdu_len)1712 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1713 				      struct sk_buff_head *msdu_list,
1714 				      struct sk_buff *first, struct sk_buff *last,
1715 				      u8 l3pad_bytes, int msdu_len)
1716 {
1717 	struct sk_buff *skb;
1718 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1719 	int buf_first_hdr_len, buf_first_len;
1720 	struct hal_rx_desc *ldesc;
1721 	int space_extra;
1722 	int rem_len;
1723 	int buf_len;
1724 
1725 	/* As the msdu is spread across multiple rx buffers,
1726 	 * find the offset to the start of msdu for computing
1727 	 * the length of the msdu in the first buffer.
1728 	 */
1729 	buf_first_hdr_len = HAL_RX_DESC_SIZE + l3pad_bytes;
1730 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1731 
1732 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1733 		skb_put(first, buf_first_hdr_len + msdu_len);
1734 		skb_pull(first, buf_first_hdr_len);
1735 		return 0;
1736 	}
1737 
1738 	ldesc = (struct hal_rx_desc *)last->data;
1739 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ldesc);
1740 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ldesc);
1741 
1742 	/* MSDU spans over multiple buffers because the length of the MSDU
1743 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1744 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1745 	 */
1746 	skb_put(first, DP_RX_BUFFER_SIZE);
1747 	skb_pull(first, buf_first_hdr_len);
1748 
1749 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1750 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1751 	 */
1752 	ath11k_dp_rx_desc_end_tlv_copy(rxcb->rx_desc, ldesc);
1753 
1754 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1755 	if (space_extra > 0 &&
1756 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1757 		/* Free up all buffers of the MSDU */
1758 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1759 			rxcb = ATH11K_SKB_RXCB(skb);
1760 			if (!rxcb->is_continuation) {
1761 				dev_kfree_skb_any(skb);
1762 				break;
1763 			}
1764 			dev_kfree_skb_any(skb);
1765 		}
1766 		return -ENOMEM;
1767 	}
1768 
1769 	rem_len = msdu_len - buf_first_len;
1770 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1771 		rxcb = ATH11K_SKB_RXCB(skb);
1772 		if (rxcb->is_continuation)
1773 			buf_len = DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE;
1774 		else
1775 			buf_len = rem_len;
1776 
1777 		if (buf_len > (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)) {
1778 			WARN_ON_ONCE(1);
1779 			dev_kfree_skb_any(skb);
1780 			return -EINVAL;
1781 		}
1782 
1783 		skb_put(skb, buf_len + HAL_RX_DESC_SIZE);
1784 		skb_pull(skb, HAL_RX_DESC_SIZE);
1785 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1786 					  buf_len);
1787 		dev_kfree_skb_any(skb);
1788 
1789 		rem_len -= buf_len;
1790 		if (!rxcb->is_continuation)
1791 			break;
1792 	}
1793 
1794 	return 0;
1795 }
1796 
ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head * msdu_list,struct sk_buff * first)1797 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1798 						      struct sk_buff *first)
1799 {
1800 	struct sk_buff *skb;
1801 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1802 
1803 	if (!rxcb->is_continuation)
1804 		return first;
1805 
1806 	skb_queue_walk(msdu_list, skb) {
1807 		rxcb = ATH11K_SKB_RXCB(skb);
1808 		if (!rxcb->is_continuation)
1809 			return skb;
1810 	}
1811 
1812 	return NULL;
1813 }
1814 
ath11k_dp_rx_h_csum_offload(struct sk_buff * msdu)1815 static void ath11k_dp_rx_h_csum_offload(struct sk_buff *msdu)
1816 {
1817 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1818 	bool ip_csum_fail, l4_csum_fail;
1819 
1820 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rxcb->rx_desc);
1821 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rxcb->rx_desc);
1822 
1823 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1824 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1825 }
1826 
ath11k_dp_rx_crypto_mic_len(struct ath11k * ar,enum hal_encrypt_type enctype)1827 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1828 				       enum hal_encrypt_type enctype)
1829 {
1830 	switch (enctype) {
1831 	case HAL_ENCRYPT_TYPE_OPEN:
1832 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1833 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1834 		return 0;
1835 	case HAL_ENCRYPT_TYPE_CCMP_128:
1836 		return IEEE80211_CCMP_MIC_LEN;
1837 	case HAL_ENCRYPT_TYPE_CCMP_256:
1838 		return IEEE80211_CCMP_256_MIC_LEN;
1839 	case HAL_ENCRYPT_TYPE_GCMP_128:
1840 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1841 		return IEEE80211_GCMP_MIC_LEN;
1842 	case HAL_ENCRYPT_TYPE_WEP_40:
1843 	case HAL_ENCRYPT_TYPE_WEP_104:
1844 	case HAL_ENCRYPT_TYPE_WEP_128:
1845 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1846 	case HAL_ENCRYPT_TYPE_WAPI:
1847 		break;
1848 	}
1849 
1850 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1851 	return 0;
1852 }
1853 
ath11k_dp_rx_crypto_param_len(struct ath11k * ar,enum hal_encrypt_type enctype)1854 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1855 					 enum hal_encrypt_type enctype)
1856 {
1857 	switch (enctype) {
1858 	case HAL_ENCRYPT_TYPE_OPEN:
1859 		return 0;
1860 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1861 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1862 		return IEEE80211_TKIP_IV_LEN;
1863 	case HAL_ENCRYPT_TYPE_CCMP_128:
1864 		return IEEE80211_CCMP_HDR_LEN;
1865 	case HAL_ENCRYPT_TYPE_CCMP_256:
1866 		return IEEE80211_CCMP_256_HDR_LEN;
1867 	case HAL_ENCRYPT_TYPE_GCMP_128:
1868 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1869 		return IEEE80211_GCMP_HDR_LEN;
1870 	case HAL_ENCRYPT_TYPE_WEP_40:
1871 	case HAL_ENCRYPT_TYPE_WEP_104:
1872 	case HAL_ENCRYPT_TYPE_WEP_128:
1873 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1874 	case HAL_ENCRYPT_TYPE_WAPI:
1875 		break;
1876 	}
1877 
1878 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1879 	return 0;
1880 }
1881 
ath11k_dp_rx_crypto_icv_len(struct ath11k * ar,enum hal_encrypt_type enctype)1882 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1883 				       enum hal_encrypt_type enctype)
1884 {
1885 	switch (enctype) {
1886 	case HAL_ENCRYPT_TYPE_OPEN:
1887 	case HAL_ENCRYPT_TYPE_CCMP_128:
1888 	case HAL_ENCRYPT_TYPE_CCMP_256:
1889 	case HAL_ENCRYPT_TYPE_GCMP_128:
1890 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1891 		return 0;
1892 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1893 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1894 		return IEEE80211_TKIP_ICV_LEN;
1895 	case HAL_ENCRYPT_TYPE_WEP_40:
1896 	case HAL_ENCRYPT_TYPE_WEP_104:
1897 	case HAL_ENCRYPT_TYPE_WEP_128:
1898 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1899 	case HAL_ENCRYPT_TYPE_WAPI:
1900 		break;
1901 	}
1902 
1903 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1904 	return 0;
1905 }
1906 
ath11k_dp_rx_h_undecap_nwifi(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)1907 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1908 					 struct sk_buff *msdu,
1909 					 u8 *first_hdr,
1910 					 enum hal_encrypt_type enctype,
1911 					 struct ieee80211_rx_status *status)
1912 {
1913 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1914 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1915 	struct ieee80211_hdr *hdr;
1916 	size_t hdr_len;
1917 	u8 da[ETH_ALEN];
1918 	u8 sa[ETH_ALEN];
1919 	u16 qos_ctl = 0;
1920 	u8 *qos;
1921 
1922 	/* copy SA & DA and pull decapped header */
1923 	hdr = (struct ieee80211_hdr *)msdu->data;
1924 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1925 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1926 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1927 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1928 
1929 	if (rxcb->is_first_msdu) {
1930 		/* original 802.11 header is valid for the first msdu
1931 		 * hence we can reuse the same header
1932 		 */
1933 		hdr = (struct ieee80211_hdr *)first_hdr;
1934 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1935 
1936 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1937 		 * so strip the A-MSDU bit from QoS Ctl.
1938 		 */
1939 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1940 			qos = ieee80211_get_qos_ctl(hdr);
1941 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1942 		}
1943 	} else {
1944 		/*  Rebuild qos header if this is a middle/last msdu */
1945 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1946 
1947 		/* Reset the order bit as the HT_Control header is stripped */
1948 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1949 
1950 		qos_ctl = rxcb->tid;
1951 
1952 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(rxcb->rx_desc))
1953 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1954 
1955 		/* TODO Add other QoS ctl fields when required */
1956 
1957 		/* copy decap header before overwriting for reuse below */
1958 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
1959 	}
1960 
1961 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
1962 		memcpy(skb_push(msdu,
1963 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
1964 		       (void *)hdr + hdr_len,
1965 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
1966 	}
1967 
1968 	if (!rxcb->is_first_msdu) {
1969 		memcpy(skb_push(msdu,
1970 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
1971 				IEEE80211_QOS_CTL_LEN);
1972 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
1973 		return;
1974 	}
1975 
1976 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
1977 
1978 	/* original 802.11 header has a different DA and in
1979 	 * case of 4addr it may also have different SA
1980 	 */
1981 	hdr = (struct ieee80211_hdr *)msdu->data;
1982 	ether_addr_copy(ieee80211_get_DA(hdr), da);
1983 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
1984 }
1985 
ath11k_dp_rx_h_undecap_raw(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)1986 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
1987 				       enum hal_encrypt_type enctype,
1988 				       struct ieee80211_rx_status *status,
1989 				       bool decrypted)
1990 {
1991 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1992 	struct ieee80211_hdr *hdr;
1993 	size_t hdr_len;
1994 	size_t crypto_len;
1995 
1996 	if (!rxcb->is_first_msdu ||
1997 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
1998 		WARN_ON_ONCE(1);
1999 		return;
2000 	}
2001 
2002 	skb_trim(msdu, msdu->len - FCS_LEN);
2003 
2004 	if (!decrypted)
2005 		return;
2006 
2007 	hdr = (void *)msdu->data;
2008 
2009 	/* Tail */
2010 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2011 		skb_trim(msdu, msdu->len -
2012 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2013 
2014 		skb_trim(msdu, msdu->len -
2015 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2016 	} else {
2017 		/* MIC */
2018 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2019 			skb_trim(msdu, msdu->len -
2020 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2021 
2022 		/* ICV */
2023 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2024 			skb_trim(msdu, msdu->len -
2025 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2026 	}
2027 
2028 	/* MMIC */
2029 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2030 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2031 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2032 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2033 
2034 	/* Head */
2035 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2036 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2037 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2038 
2039 		memmove((void *)msdu->data + crypto_len,
2040 			(void *)msdu->data, hdr_len);
2041 		skb_pull(msdu, crypto_len);
2042 	}
2043 }
2044 
ath11k_dp_rx_h_find_rfc1042(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype)2045 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2046 					 struct sk_buff *msdu,
2047 					 enum hal_encrypt_type enctype)
2048 {
2049 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2050 	struct ieee80211_hdr *hdr;
2051 	size_t hdr_len, crypto_len;
2052 	void *rfc1042;
2053 	bool is_amsdu;
2054 
2055 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2056 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(rxcb->rx_desc);
2057 	rfc1042 = hdr;
2058 
2059 	if (rxcb->is_first_msdu) {
2060 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2061 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2062 
2063 		rfc1042 += hdr_len + crypto_len;
2064 	}
2065 
2066 	if (is_amsdu)
2067 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2068 
2069 	return rfc1042;
2070 }
2071 
ath11k_dp_rx_h_undecap_eth(struct ath11k * ar,struct sk_buff * msdu,u8 * first_hdr,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status)2072 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2073 				       struct sk_buff *msdu,
2074 				       u8 *first_hdr,
2075 				       enum hal_encrypt_type enctype,
2076 				       struct ieee80211_rx_status *status)
2077 {
2078 	struct ieee80211_hdr *hdr;
2079 	struct ethhdr *eth;
2080 	size_t hdr_len;
2081 	u8 da[ETH_ALEN];
2082 	u8 sa[ETH_ALEN];
2083 	void *rfc1042;
2084 
2085 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2086 	if (WARN_ON_ONCE(!rfc1042))
2087 		return;
2088 
2089 	/* pull decapped header and copy SA & DA */
2090 	eth = (struct ethhdr *)msdu->data;
2091 	ether_addr_copy(da, eth->h_dest);
2092 	ether_addr_copy(sa, eth->h_source);
2093 	skb_pull(msdu, sizeof(struct ethhdr));
2094 
2095 	/* push rfc1042/llc/snap */
2096 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2097 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2098 
2099 	/* push original 802.11 header */
2100 	hdr = (struct ieee80211_hdr *)first_hdr;
2101 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2102 
2103 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2104 		memcpy(skb_push(msdu,
2105 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2106 		       (void *)hdr + hdr_len,
2107 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2108 	}
2109 
2110 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2111 
2112 	/* original 802.11 header has a different DA and in
2113 	 * case of 4addr it may also have different SA
2114 	 */
2115 	hdr = (struct ieee80211_hdr *)msdu->data;
2116 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2117 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2118 }
2119 
ath11k_dp_rx_h_undecap(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,enum hal_encrypt_type enctype,struct ieee80211_rx_status * status,bool decrypted)2120 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2121 				   struct hal_rx_desc *rx_desc,
2122 				   enum hal_encrypt_type enctype,
2123 				   struct ieee80211_rx_status *status,
2124 				   bool decrypted)
2125 {
2126 	u8 *first_hdr;
2127 	u8 decap;
2128 
2129 	first_hdr = ath11k_dp_rx_h_80211_hdr(rx_desc);
2130 	decap = ath11k_dp_rx_h_msdu_start_decap_type(rx_desc);
2131 
2132 	switch (decap) {
2133 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2134 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2135 					     enctype, status);
2136 		break;
2137 	case DP_RX_DECAP_TYPE_RAW:
2138 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2139 					   decrypted);
2140 		break;
2141 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2142 		/* TODO undecap support for middle/last msdu's of amsdu */
2143 		ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2144 					   enctype, status);
2145 		break;
2146 	case DP_RX_DECAP_TYPE_8023:
2147 		/* TODO: Handle undecap for these formats */
2148 		break;
2149 	}
2150 }
2151 
ath11k_dp_rx_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2152 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2153 				struct sk_buff *msdu,
2154 				struct hal_rx_desc *rx_desc,
2155 				struct ieee80211_rx_status *rx_status)
2156 {
2157 	bool  fill_crypto_hdr, mcast;
2158 	enum hal_encrypt_type enctype;
2159 	bool is_decrypted = false;
2160 	struct ieee80211_hdr *hdr;
2161 	struct ath11k_peer *peer;
2162 	u32 err_bitmap;
2163 
2164 	hdr = (struct ieee80211_hdr *)msdu->data;
2165 
2166 	/* PN for multicast packets will be checked in mac80211 */
2167 
2168 	mcast = is_multicast_ether_addr(hdr->addr1);
2169 	fill_crypto_hdr = mcast;
2170 
2171 	spin_lock_bh(&ar->ab->base_lock);
2172 	peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2);
2173 	if (peer) {
2174 		if (mcast)
2175 			enctype = peer->sec_type_grp;
2176 		else
2177 			enctype = peer->sec_type;
2178 	} else {
2179 		enctype = HAL_ENCRYPT_TYPE_OPEN;
2180 	}
2181 	spin_unlock_bh(&ar->ab->base_lock);
2182 
2183 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_desc);
2184 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2185 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
2186 
2187 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2188 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2189 			     RX_FLAG_MMIC_ERROR |
2190 			     RX_FLAG_DECRYPTED |
2191 			     RX_FLAG_IV_STRIPPED |
2192 			     RX_FLAG_MMIC_STRIPPED);
2193 
2194 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2195 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2196 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2197 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2198 
2199 	if (is_decrypted) {
2200 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2201 
2202 		if (fill_crypto_hdr)
2203 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2204 					RX_FLAG_ICV_STRIPPED;
2205 		else
2206 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2207 					   RX_FLAG_PN_VALIDATED;
2208 	}
2209 
2210 	ath11k_dp_rx_h_csum_offload(msdu);
2211 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2212 			       enctype, rx_status, is_decrypted);
2213 
2214 	if (!is_decrypted || fill_crypto_hdr)
2215 		return;
2216 
2217 	hdr = (void *)msdu->data;
2218 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2219 }
2220 
ath11k_dp_rx_h_rate(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2221 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2222 				struct ieee80211_rx_status *rx_status)
2223 {
2224 	struct ieee80211_supported_band *sband;
2225 	enum rx_msdu_start_pkt_type pkt_type;
2226 	u8 bw;
2227 	u8 rate_mcs, nss;
2228 	u8 sgi;
2229 	bool is_cck;
2230 
2231 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(rx_desc);
2232 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(rx_desc);
2233 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(rx_desc);
2234 	nss = ath11k_dp_rx_h_msdu_start_nss(rx_desc);
2235 	sgi = ath11k_dp_rx_h_msdu_start_sgi(rx_desc);
2236 
2237 	switch (pkt_type) {
2238 	case RX_MSDU_START_PKT_TYPE_11A:
2239 	case RX_MSDU_START_PKT_TYPE_11B:
2240 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2241 		sband = &ar->mac.sbands[rx_status->band];
2242 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2243 								is_cck);
2244 		break;
2245 	case RX_MSDU_START_PKT_TYPE_11N:
2246 		rx_status->encoding = RX_ENC_HT;
2247 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2248 			ath11k_warn(ar->ab,
2249 				    "Received with invalid mcs in HT mode %d\n",
2250 				     rate_mcs);
2251 			break;
2252 		}
2253 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2254 		if (sgi)
2255 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2256 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2257 		break;
2258 	case RX_MSDU_START_PKT_TYPE_11AC:
2259 		rx_status->encoding = RX_ENC_VHT;
2260 		rx_status->rate_idx = rate_mcs;
2261 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2262 			ath11k_warn(ar->ab,
2263 				    "Received with invalid mcs in VHT mode %d\n",
2264 				     rate_mcs);
2265 			break;
2266 		}
2267 		rx_status->nss = nss;
2268 		if (sgi)
2269 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2270 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2271 		break;
2272 	case RX_MSDU_START_PKT_TYPE_11AX:
2273 		rx_status->rate_idx = rate_mcs;
2274 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2275 			ath11k_warn(ar->ab,
2276 				    "Received with invalid mcs in HE mode %d\n",
2277 				    rate_mcs);
2278 			break;
2279 		}
2280 		rx_status->encoding = RX_ENC_HE;
2281 		rx_status->nss = nss;
2282 		rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi);
2283 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2284 		break;
2285 	}
2286 }
2287 
ath11k_dp_rx_h_ppdu(struct ath11k * ar,struct hal_rx_desc * rx_desc,struct ieee80211_rx_status * rx_status)2288 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2289 				struct ieee80211_rx_status *rx_status)
2290 {
2291 	u8 channel_num;
2292 	u32 center_freq;
2293 	struct ieee80211_channel *channel;
2294 
2295 	rx_status->freq = 0;
2296 	rx_status->rate_idx = 0;
2297 	rx_status->nss = 0;
2298 	rx_status->encoding = RX_ENC_LEGACY;
2299 	rx_status->bw = RATE_INFO_BW_20;
2300 
2301 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2302 
2303 	channel_num = ath11k_dp_rx_h_msdu_start_freq(rx_desc);
2304 	center_freq = ath11k_dp_rx_h_msdu_start_freq(rx_desc) >> 16;
2305 
2306 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2307 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2308 		rx_status->band = NL80211_BAND_6GHZ;
2309 		rx_status->freq = center_freq;
2310 	} else if (channel_num >= 1 && channel_num <= 14) {
2311 		rx_status->band = NL80211_BAND_2GHZ;
2312 	} else if (channel_num >= 36 && channel_num <= 173) {
2313 		rx_status->band = NL80211_BAND_5GHZ;
2314 	} else {
2315 		spin_lock_bh(&ar->data_lock);
2316 		channel = ar->rx_channel;
2317 		if (channel) {
2318 			rx_status->band = channel->band;
2319 			channel_num =
2320 				ieee80211_frequency_to_channel(channel->center_freq);
2321 		}
2322 		spin_unlock_bh(&ar->data_lock);
2323 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2324 				rx_desc, sizeof(struct hal_rx_desc));
2325 	}
2326 
2327 	if (rx_status->band != NL80211_BAND_6GHZ)
2328 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2329 								 rx_status->band);
2330 
2331 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2332 }
2333 
ath11k_print_get_tid(struct ieee80211_hdr * hdr,char * out,size_t size)2334 static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out,
2335 				  size_t size)
2336 {
2337 	u8 *qc;
2338 	int tid;
2339 
2340 	if (!ieee80211_is_data_qos(hdr->frame_control))
2341 		return "";
2342 
2343 	qc = ieee80211_get_qos_ctl(hdr);
2344 	tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
2345 	snprintf(out, size, "tid %d", tid);
2346 
2347 	return out;
2348 }
2349 
ath11k_dp_rx_deliver_msdu(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu)2350 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2351 				      struct sk_buff *msdu)
2352 {
2353 	static const struct ieee80211_radiotap_he known = {
2354 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2355 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2356 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2357 	};
2358 	struct ieee80211_rx_status *status;
2359 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
2360 	struct ieee80211_radiotap_he *he = NULL;
2361 	char tid[32];
2362 
2363 	status = IEEE80211_SKB_RXCB(msdu);
2364 	if (status->encoding == RX_ENC_HE) {
2365 		he = skb_push(msdu, sizeof(known));
2366 		memcpy(he, &known, sizeof(known));
2367 		status->flag |= RX_FLAG_RADIOTAP_HE;
2368 	}
2369 
2370 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2371 		   "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2372 		   msdu,
2373 		   msdu->len,
2374 		   ieee80211_get_SA(hdr),
2375 		   ath11k_print_get_tid(hdr, tid, sizeof(tid)),
2376 		   is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
2377 							"mcast" : "ucast",
2378 		   (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
2379 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2380 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2381 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2382 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2383 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2384 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2385 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2386 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2387 		   status->rate_idx,
2388 		   status->nss,
2389 		   status->freq,
2390 		   status->band, status->flag,
2391 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2392 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2393 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2394 
2395 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2396 			msdu->data, msdu->len);
2397 
2398 	/* TODO: trace rx packet */
2399 
2400 	ieee80211_rx_napi(ar->hw, NULL, msdu, napi);
2401 }
2402 
ath11k_dp_rx_process_msdu(struct ath11k * ar,struct sk_buff * msdu,struct sk_buff_head * msdu_list)2403 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2404 				     struct sk_buff *msdu,
2405 				     struct sk_buff_head *msdu_list)
2406 {
2407 	struct hal_rx_desc *rx_desc, *lrx_desc;
2408 	struct ieee80211_rx_status rx_status = {0};
2409 	struct ieee80211_rx_status *status;
2410 	struct ath11k_skb_rxcb *rxcb;
2411 	struct ieee80211_hdr *hdr;
2412 	struct sk_buff *last_buf;
2413 	u8 l3_pad_bytes;
2414 	u8 *hdr_status;
2415 	u16 msdu_len;
2416 	int ret;
2417 
2418 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2419 	if (!last_buf) {
2420 		ath11k_warn(ar->ab,
2421 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2422 		ret = -EIO;
2423 		goto free_out;
2424 	}
2425 
2426 	rx_desc = (struct hal_rx_desc *)msdu->data;
2427 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2428 	if (!ath11k_dp_rx_h_attn_msdu_done(lrx_desc)) {
2429 		ath11k_warn(ar->ab, "msdu_done bit in attention is not set\n");
2430 		ret = -EIO;
2431 		goto free_out;
2432 	}
2433 
2434 	rxcb = ATH11K_SKB_RXCB(msdu);
2435 	rxcb->rx_desc = rx_desc;
2436 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
2437 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(lrx_desc);
2438 
2439 	if (rxcb->is_frag) {
2440 		skb_pull(msdu, HAL_RX_DESC_SIZE);
2441 	} else if (!rxcb->is_continuation) {
2442 		if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
2443 			hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
2444 			ret = -EINVAL;
2445 			ath11k_warn(ar->ab, "invalid msdu len %u\n", msdu_len);
2446 			ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2447 					sizeof(struct ieee80211_hdr));
2448 			ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2449 					sizeof(struct hal_rx_desc));
2450 			goto free_out;
2451 		}
2452 		skb_put(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes + msdu_len);
2453 		skb_pull(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes);
2454 	} else {
2455 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2456 						 msdu, last_buf,
2457 						 l3_pad_bytes, msdu_len);
2458 		if (ret) {
2459 			ath11k_warn(ar->ab,
2460 				    "failed to coalesce msdu rx buffer%d\n", ret);
2461 			goto free_out;
2462 		}
2463 	}
2464 
2465 	hdr = (struct ieee80211_hdr *)msdu->data;
2466 
2467 	/* Process only data frames */
2468 	if (!ieee80211_is_data(hdr->frame_control))
2469 		return -EINVAL;
2470 
2471 	ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status);
2472 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status);
2473 
2474 	rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2475 
2476 	status = IEEE80211_SKB_RXCB(msdu);
2477 	*status = rx_status;
2478 	return 0;
2479 
2480 free_out:
2481 	return ret;
2482 }
2483 
ath11k_dp_rx_process_received_packets(struct ath11k_base * ab,struct napi_struct * napi,struct sk_buff_head * msdu_list,int * quota,int ring_id)2484 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2485 						  struct napi_struct *napi,
2486 						  struct sk_buff_head *msdu_list,
2487 						  int *quota, int ring_id)
2488 {
2489 	struct ath11k_skb_rxcb *rxcb;
2490 	struct sk_buff *msdu;
2491 	struct ath11k *ar;
2492 	u8 mac_id;
2493 	int ret;
2494 
2495 	if (skb_queue_empty(msdu_list))
2496 		return;
2497 
2498 	rcu_read_lock();
2499 
2500 	while (*quota && (msdu = __skb_dequeue(msdu_list))) {
2501 		rxcb = ATH11K_SKB_RXCB(msdu);
2502 		mac_id = rxcb->mac_id;
2503 		ar = ab->pdevs[mac_id].ar;
2504 		if (!rcu_dereference(ab->pdevs_active[mac_id])) {
2505 			dev_kfree_skb_any(msdu);
2506 			continue;
2507 		}
2508 
2509 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
2510 			dev_kfree_skb_any(msdu);
2511 			continue;
2512 		}
2513 
2514 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list);
2515 		if (ret) {
2516 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2517 				   "Unable to process msdu %d", ret);
2518 			dev_kfree_skb_any(msdu);
2519 			continue;
2520 		}
2521 
2522 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
2523 		(*quota)--;
2524 	}
2525 
2526 	rcu_read_unlock();
2527 }
2528 
ath11k_dp_process_rx(struct ath11k_base * ab,int ring_id,struct napi_struct * napi,int budget)2529 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2530 			 struct napi_struct *napi, int budget)
2531 {
2532 	struct ath11k_dp *dp = &ab->dp;
2533 	struct dp_rxdma_ring *rx_ring;
2534 	int num_buffs_reaped[MAX_RADIOS] = {0};
2535 	struct sk_buff_head msdu_list;
2536 	struct ath11k_skb_rxcb *rxcb;
2537 	int total_msdu_reaped = 0;
2538 	struct hal_srng *srng;
2539 	struct sk_buff *msdu;
2540 	int quota = budget;
2541 	bool done = false;
2542 	int buf_id, mac_id;
2543 	struct ath11k *ar;
2544 	u32 *rx_desc;
2545 	int i;
2546 
2547 	__skb_queue_head_init(&msdu_list);
2548 
2549 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2550 
2551 	spin_lock_bh(&srng->lock);
2552 
2553 	ath11k_hal_srng_access_begin(ab, srng);
2554 
2555 try_again:
2556 	while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
2557 		struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc;
2558 		enum hal_reo_dest_ring_push_reason push_reason;
2559 		u32 cookie;
2560 
2561 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2562 				   desc.buf_addr_info.info1);
2563 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2564 				   cookie);
2565 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2566 
2567 		ar = ab->pdevs[mac_id].ar;
2568 		rx_ring = &ar->dp.rx_refill_buf_ring;
2569 		spin_lock_bh(&rx_ring->idr_lock);
2570 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2571 		if (!msdu) {
2572 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2573 				    buf_id);
2574 			spin_unlock_bh(&rx_ring->idr_lock);
2575 			continue;
2576 		}
2577 
2578 		idr_remove(&rx_ring->bufs_idr, buf_id);
2579 		spin_unlock_bh(&rx_ring->idr_lock);
2580 
2581 		rxcb = ATH11K_SKB_RXCB(msdu);
2582 		dma_unmap_single(ab->dev, rxcb->paddr,
2583 				 msdu->len + skb_tailroom(msdu),
2584 				 DMA_FROM_DEVICE);
2585 
2586 		num_buffs_reaped[mac_id]++;
2587 		total_msdu_reaped++;
2588 
2589 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2590 					desc.info0);
2591 		if (push_reason !=
2592 		    HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
2593 			dev_kfree_skb_any(msdu);
2594 			ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2595 			continue;
2596 		}
2597 
2598 		rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 &
2599 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2600 		rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 &
2601 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2602 		rxcb->is_continuation = !!(desc.rx_msdu_info.info0 &
2603 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2604 		rxcb->mac_id = mac_id;
2605 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2606 				      desc.info0);
2607 
2608 		__skb_queue_tail(&msdu_list, msdu);
2609 
2610 		if (total_msdu_reaped >= quota && !rxcb->is_continuation) {
2611 			done = true;
2612 			break;
2613 		}
2614 	}
2615 
2616 	/* Hw might have updated the head pointer after we cached it.
2617 	 * In this case, even though there are entries in the ring we'll
2618 	 * get rx_desc NULL. Give the read another try with updated cached
2619 	 * head pointer so that we can reap complete MPDU in the current
2620 	 * rx processing.
2621 	 */
2622 	if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) {
2623 		ath11k_hal_srng_access_end(ab, srng);
2624 		goto try_again;
2625 	}
2626 
2627 	ath11k_hal_srng_access_end(ab, srng);
2628 
2629 	spin_unlock_bh(&srng->lock);
2630 
2631 	if (!total_msdu_reaped)
2632 		goto exit;
2633 
2634 	for (i = 0; i < ab->num_radios; i++) {
2635 		if (!num_buffs_reaped[i])
2636 			continue;
2637 
2638 		ar = ab->pdevs[i].ar;
2639 		rx_ring = &ar->dp.rx_refill_buf_ring;
2640 
2641 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2642 					   HAL_RX_BUF_RBM_SW3_BM);
2643 	}
2644 
2645 	ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list,
2646 					      &quota, ring_id);
2647 
2648 exit:
2649 	return budget - quota;
2650 }
2651 
ath11k_dp_rx_update_peer_stats(struct ath11k_sta * arsta,struct hal_rx_mon_ppdu_info * ppdu_info)2652 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2653 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2654 {
2655 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2656 	u32 num_msdu;
2657 
2658 	if (!rx_stats)
2659 		return;
2660 
2661 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2662 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2663 
2664 	rx_stats->num_msdu += num_msdu;
2665 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2666 				    ppdu_info->tcp_ack_msdu_count;
2667 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2668 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2669 
2670 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2671 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2672 		ppdu_info->nss = 1;
2673 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2674 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2675 	}
2676 
2677 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2678 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2679 
2680 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2681 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2682 
2683 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2684 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2685 
2686 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2687 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2688 
2689 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2690 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2691 
2692 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2693 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2694 
2695 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2696 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2697 
2698 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2699 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2700 
2701 	if (ppdu_info->is_stbc)
2702 		rx_stats->stbc_count += num_msdu;
2703 
2704 	if (ppdu_info->beamformed)
2705 		rx_stats->beamformed_count += num_msdu;
2706 
2707 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2708 		rx_stats->ampdu_msdu_count += num_msdu;
2709 	else
2710 		rx_stats->non_ampdu_msdu_count += num_msdu;
2711 
2712 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2713 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2714 	rx_stats->dcm_count += ppdu_info->dcm;
2715 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2716 
2717 	arsta->rssi_comb = ppdu_info->rssi_comb;
2718 	rx_stats->rx_duration += ppdu_info->rx_duration;
2719 	arsta->rx_duration = rx_stats->rx_duration;
2720 }
2721 
ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base * ab,struct dp_rxdma_ring * rx_ring,int * buf_id)2722 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2723 							 struct dp_rxdma_ring *rx_ring,
2724 							 int *buf_id)
2725 {
2726 	struct sk_buff *skb;
2727 	dma_addr_t paddr;
2728 
2729 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2730 			    DP_RX_BUFFER_ALIGN_SIZE);
2731 
2732 	if (!skb)
2733 		goto fail_alloc_skb;
2734 
2735 	if (!IS_ALIGNED((unsigned long)skb->data,
2736 			DP_RX_BUFFER_ALIGN_SIZE)) {
2737 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2738 			 skb->data);
2739 	}
2740 
2741 	paddr = dma_map_single(ab->dev, skb->data,
2742 			       skb->len + skb_tailroom(skb),
2743 			       DMA_BIDIRECTIONAL);
2744 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2745 		goto fail_free_skb;
2746 
2747 	spin_lock_bh(&rx_ring->idr_lock);
2748 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2749 			    rx_ring->bufs_max, GFP_ATOMIC);
2750 	spin_unlock_bh(&rx_ring->idr_lock);
2751 	if (*buf_id < 0)
2752 		goto fail_dma_unmap;
2753 
2754 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2755 	return skb;
2756 
2757 fail_dma_unmap:
2758 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2759 			 DMA_BIDIRECTIONAL);
2760 fail_free_skb:
2761 	dev_kfree_skb_any(skb);
2762 fail_alloc_skb:
2763 	return NULL;
2764 }
2765 
ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base * ab,int mac_id,struct dp_rxdma_ring * rx_ring,int req_entries,enum hal_rx_buf_return_buf_manager mgr)2766 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2767 					   struct dp_rxdma_ring *rx_ring,
2768 					   int req_entries,
2769 					   enum hal_rx_buf_return_buf_manager mgr)
2770 {
2771 	struct hal_srng *srng;
2772 	u32 *desc;
2773 	struct sk_buff *skb;
2774 	int num_free;
2775 	int num_remain;
2776 	int buf_id;
2777 	u32 cookie;
2778 	dma_addr_t paddr;
2779 
2780 	req_entries = min(req_entries, rx_ring->bufs_max);
2781 
2782 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2783 
2784 	spin_lock_bh(&srng->lock);
2785 
2786 	ath11k_hal_srng_access_begin(ab, srng);
2787 
2788 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2789 
2790 	req_entries = min(num_free, req_entries);
2791 	num_remain = req_entries;
2792 
2793 	while (num_remain > 0) {
2794 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2795 							&buf_id);
2796 		if (!skb)
2797 			break;
2798 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2799 
2800 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2801 		if (!desc)
2802 			goto fail_desc_get;
2803 
2804 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2805 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2806 
2807 		num_remain--;
2808 
2809 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2810 	}
2811 
2812 	ath11k_hal_srng_access_end(ab, srng);
2813 
2814 	spin_unlock_bh(&srng->lock);
2815 
2816 	return req_entries - num_remain;
2817 
2818 fail_desc_get:
2819 	spin_lock_bh(&rx_ring->idr_lock);
2820 	idr_remove(&rx_ring->bufs_idr, buf_id);
2821 	spin_unlock_bh(&rx_ring->idr_lock);
2822 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2823 			 DMA_BIDIRECTIONAL);
2824 	dev_kfree_skb_any(skb);
2825 	ath11k_hal_srng_access_end(ab, srng);
2826 	spin_unlock_bh(&srng->lock);
2827 
2828 	return req_entries - num_remain;
2829 }
2830 
ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)2831 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2832 					     int *budget, struct sk_buff_head *skb_list)
2833 {
2834 	struct ath11k *ar;
2835 	struct ath11k_pdev_dp *dp;
2836 	struct dp_rxdma_ring *rx_ring;
2837 	struct hal_srng *srng;
2838 	void *rx_mon_status_desc;
2839 	struct sk_buff *skb;
2840 	struct ath11k_skb_rxcb *rxcb;
2841 	struct hal_tlv_hdr *tlv;
2842 	u32 cookie;
2843 	int buf_id, srng_id;
2844 	dma_addr_t paddr;
2845 	u8 rbm;
2846 	int num_buffs_reaped = 0;
2847 
2848 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2849 	dp = &ar->dp;
2850 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2851 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2852 
2853 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2854 
2855 	spin_lock_bh(&srng->lock);
2856 
2857 	ath11k_hal_srng_access_begin(ab, srng);
2858 	while (*budget) {
2859 		*budget -= 1;
2860 		rx_mon_status_desc =
2861 			ath11k_hal_srng_src_peek(ab, srng);
2862 		if (!rx_mon_status_desc)
2863 			break;
2864 
2865 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
2866 						&cookie, &rbm);
2867 		if (paddr) {
2868 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
2869 
2870 			spin_lock_bh(&rx_ring->idr_lock);
2871 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
2872 			if (!skb) {
2873 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
2874 					    buf_id);
2875 				spin_unlock_bh(&rx_ring->idr_lock);
2876 				goto move_next;
2877 			}
2878 
2879 			idr_remove(&rx_ring->bufs_idr, buf_id);
2880 			spin_unlock_bh(&rx_ring->idr_lock);
2881 
2882 			rxcb = ATH11K_SKB_RXCB(skb);
2883 
2884 			dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
2885 						skb->len + skb_tailroom(skb),
2886 						DMA_FROM_DEVICE);
2887 
2888 			dma_unmap_single(ab->dev, rxcb->paddr,
2889 					 skb->len + skb_tailroom(skb),
2890 					 DMA_BIDIRECTIONAL);
2891 
2892 			tlv = (struct hal_tlv_hdr *)skb->data;
2893 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
2894 					HAL_RX_STATUS_BUFFER_DONE) {
2895 				ath11k_warn(ab, "mon status DONE not set %lx\n",
2896 					    FIELD_GET(HAL_TLV_HDR_TAG,
2897 						      tlv->tl));
2898 				dev_kfree_skb_any(skb);
2899 				goto move_next;
2900 			}
2901 
2902 			__skb_queue_tail(skb_list, skb);
2903 		}
2904 move_next:
2905 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2906 							&buf_id);
2907 
2908 		if (!skb) {
2909 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
2910 							HAL_RX_BUF_RBM_SW3_BM);
2911 			num_buffs_reaped++;
2912 			break;
2913 		}
2914 		rxcb = ATH11K_SKB_RXCB(skb);
2915 
2916 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2917 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2918 
2919 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
2920 						cookie, HAL_RX_BUF_RBM_SW3_BM);
2921 		ath11k_hal_srng_src_get_next_entry(ab, srng);
2922 		num_buffs_reaped++;
2923 	}
2924 	ath11k_hal_srng_access_end(ab, srng);
2925 	spin_unlock_bh(&srng->lock);
2926 
2927 	return num_buffs_reaped;
2928 }
2929 
ath11k_dp_rx_process_mon_status(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)2930 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
2931 				    struct napi_struct *napi, int budget)
2932 {
2933 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
2934 	enum hal_rx_mon_status hal_status;
2935 	struct sk_buff *skb;
2936 	struct sk_buff_head skb_list;
2937 	struct hal_rx_mon_ppdu_info ppdu_info;
2938 	struct ath11k_peer *peer;
2939 	struct ath11k_sta *arsta;
2940 	int num_buffs_reaped = 0;
2941 
2942 	__skb_queue_head_init(&skb_list);
2943 
2944 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
2945 							     &skb_list);
2946 	if (!num_buffs_reaped)
2947 		goto exit;
2948 
2949 	while ((skb = __skb_dequeue(&skb_list))) {
2950 		memset(&ppdu_info, 0, sizeof(ppdu_info));
2951 		ppdu_info.peer_id = HAL_INVALID_PEERID;
2952 
2953 		if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar))
2954 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2955 
2956 		hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
2957 
2958 		if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
2959 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
2960 			dev_kfree_skb_any(skb);
2961 			continue;
2962 		}
2963 
2964 		rcu_read_lock();
2965 		spin_lock_bh(&ab->base_lock);
2966 		peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
2967 
2968 		if (!peer || !peer->sta) {
2969 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2970 				   "failed to find the peer with peer_id %d\n",
2971 				   ppdu_info.peer_id);
2972 			spin_unlock_bh(&ab->base_lock);
2973 			rcu_read_unlock();
2974 			dev_kfree_skb_any(skb);
2975 			continue;
2976 		}
2977 
2978 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
2979 		ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
2980 
2981 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
2982 			trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
2983 
2984 		spin_unlock_bh(&ab->base_lock);
2985 		rcu_read_unlock();
2986 
2987 		dev_kfree_skb_any(skb);
2988 	}
2989 exit:
2990 	return num_buffs_reaped;
2991 }
2992 
ath11k_dp_rx_frag_timer(struct timer_list * timer)2993 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
2994 {
2995 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
2996 
2997 	spin_lock_bh(&rx_tid->ab->base_lock);
2998 	if (rx_tid->last_frag_no &&
2999 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3000 		spin_unlock_bh(&rx_tid->ab->base_lock);
3001 		return;
3002 	}
3003 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3004 	spin_unlock_bh(&rx_tid->ab->base_lock);
3005 }
3006 
ath11k_peer_rx_frag_setup(struct ath11k * ar,const u8 * peer_mac,int vdev_id)3007 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3008 {
3009 	struct ath11k_base *ab = ar->ab;
3010 	struct crypto_shash *tfm;
3011 	struct ath11k_peer *peer;
3012 	struct dp_rx_tid *rx_tid;
3013 	int i;
3014 
3015 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3016 	if (IS_ERR(tfm))
3017 		return PTR_ERR(tfm);
3018 
3019 	spin_lock_bh(&ab->base_lock);
3020 
3021 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3022 	if (!peer) {
3023 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3024 		spin_unlock_bh(&ab->base_lock);
3025 		return -ENOENT;
3026 	}
3027 
3028 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3029 		rx_tid = &peer->rx_tid[i];
3030 		rx_tid->ab = ab;
3031 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3032 		skb_queue_head_init(&rx_tid->rx_frags);
3033 	}
3034 
3035 	peer->tfm_mmic = tfm;
3036 	spin_unlock_bh(&ab->base_lock);
3037 
3038 	return 0;
3039 }
3040 
ath11k_dp_rx_h_michael_mic(struct crypto_shash * tfm,u8 * key,struct ieee80211_hdr * hdr,u8 * data,size_t data_len,u8 * mic)3041 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3042 				      struct ieee80211_hdr *hdr, u8 *data,
3043 				      size_t data_len, u8 *mic)
3044 {
3045 	SHASH_DESC_ON_STACK(desc, tfm);
3046 	u8 mic_hdr[16] = {0};
3047 	u8 tid = 0;
3048 	int ret;
3049 
3050 	if (!tfm)
3051 		return -EINVAL;
3052 
3053 	desc->tfm = tfm;
3054 
3055 	ret = crypto_shash_setkey(tfm, key, 8);
3056 	if (ret)
3057 		goto out;
3058 
3059 	ret = crypto_shash_init(desc);
3060 	if (ret)
3061 		goto out;
3062 
3063 	/* TKIP MIC header */
3064 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3065 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3066 	if (ieee80211_is_data_qos(hdr->frame_control))
3067 		tid = ieee80211_get_tid(hdr);
3068 	mic_hdr[12] = tid;
3069 
3070 	ret = crypto_shash_update(desc, mic_hdr, 16);
3071 	if (ret)
3072 		goto out;
3073 	ret = crypto_shash_update(desc, data, data_len);
3074 	if (ret)
3075 		goto out;
3076 	ret = crypto_shash_final(desc, mic);
3077 out:
3078 	shash_desc_zero(desc);
3079 	return ret;
3080 }
3081 
ath11k_dp_rx_h_verify_tkip_mic(struct ath11k * ar,struct ath11k_peer * peer,struct sk_buff * msdu)3082 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3083 					  struct sk_buff *msdu)
3084 {
3085 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3086 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3087 	struct ieee80211_key_conf *key_conf;
3088 	struct ieee80211_hdr *hdr;
3089 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3090 	int head_len, tail_len, ret;
3091 	size_t data_len;
3092 	u32 hdr_len;
3093 	u8 *key, *data;
3094 	u8 key_idx;
3095 
3096 	if (ath11k_dp_rx_h_mpdu_start_enctype(rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
3097 		return 0;
3098 
3099 	hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3100 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3101 	head_len = hdr_len + HAL_RX_DESC_SIZE + IEEE80211_TKIP_IV_LEN;
3102 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3103 
3104 	if (!is_multicast_ether_addr(hdr->addr1))
3105 		key_idx = peer->ucast_keyidx;
3106 	else
3107 		key_idx = peer->mcast_keyidx;
3108 
3109 	key_conf = peer->keys[key_idx];
3110 
3111 	data = msdu->data + head_len;
3112 	data_len = msdu->len - head_len - tail_len;
3113 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3114 
3115 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3116 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3117 		goto mic_fail;
3118 
3119 	return 0;
3120 
3121 mic_fail:
3122 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3123 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3124 
3125 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3126 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3127 	skb_pull(msdu, HAL_RX_DESC_SIZE);
3128 
3129 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3130 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3131 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3132 	ieee80211_rx(ar->hw, msdu);
3133 	return -EINVAL;
3134 }
3135 
ath11k_dp_rx_h_undecap_frag(struct ath11k * ar,struct sk_buff * msdu,enum hal_encrypt_type enctype,u32 flags)3136 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3137 					enum hal_encrypt_type enctype, u32 flags)
3138 {
3139 	struct ieee80211_hdr *hdr;
3140 	size_t hdr_len;
3141 	size_t crypto_len;
3142 
3143 	if (!flags)
3144 		return;
3145 
3146 	hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE);
3147 
3148 	if (flags & RX_FLAG_MIC_STRIPPED)
3149 		skb_trim(msdu, msdu->len -
3150 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3151 
3152 	if (flags & RX_FLAG_ICV_STRIPPED)
3153 		skb_trim(msdu, msdu->len -
3154 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3155 
3156 	if (flags & RX_FLAG_IV_STRIPPED) {
3157 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3158 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3159 
3160 		memmove((void *)msdu->data + HAL_RX_DESC_SIZE + crypto_len,
3161 			(void *)msdu->data + HAL_RX_DESC_SIZE, hdr_len);
3162 		skb_pull(msdu, crypto_len);
3163 	}
3164 }
3165 
ath11k_dp_rx_h_defrag(struct ath11k * ar,struct ath11k_peer * peer,struct dp_rx_tid * rx_tid,struct sk_buff ** defrag_skb)3166 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3167 				 struct ath11k_peer *peer,
3168 				 struct dp_rx_tid *rx_tid,
3169 				 struct sk_buff **defrag_skb)
3170 {
3171 	struct hal_rx_desc *rx_desc;
3172 	struct sk_buff *skb, *first_frag, *last_frag;
3173 	struct ieee80211_hdr *hdr;
3174 	enum hal_encrypt_type enctype;
3175 	bool is_decrypted = false;
3176 	int msdu_len = 0;
3177 	int extra_space;
3178 	u32 flags;
3179 
3180 	first_frag = skb_peek(&rx_tid->rx_frags);
3181 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3182 
3183 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3184 		flags = 0;
3185 		rx_desc = (struct hal_rx_desc *)skb->data;
3186 		hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3187 
3188 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(rx_desc);
3189 		if (enctype != HAL_ENCRYPT_TYPE_OPEN)
3190 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc);
3191 
3192 		if (is_decrypted) {
3193 			if (skb != first_frag)
3194 				flags |=  RX_FLAG_IV_STRIPPED;
3195 			if (skb != last_frag)
3196 				flags |= RX_FLAG_ICV_STRIPPED |
3197 					 RX_FLAG_MIC_STRIPPED;
3198 		}
3199 
3200 		/* RX fragments are always raw packets */
3201 		if (skb != last_frag)
3202 			skb_trim(skb, skb->len - FCS_LEN);
3203 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3204 
3205 		if (skb != first_frag)
3206 			skb_pull(skb, HAL_RX_DESC_SIZE +
3207 				      ieee80211_hdrlen(hdr->frame_control));
3208 		msdu_len += skb->len;
3209 	}
3210 
3211 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3212 	if (extra_space > 0 &&
3213 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3214 		return -ENOMEM;
3215 
3216 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3217 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3218 		skb_put_data(first_frag, skb->data, skb->len);
3219 		dev_kfree_skb_any(skb);
3220 	}
3221 
3222 	hdr = (struct ieee80211_hdr *)(first_frag->data + HAL_RX_DESC_SIZE);
3223 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3224 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3225 
3226 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3227 		first_frag = NULL;
3228 
3229 	*defrag_skb = first_frag;
3230 	return 0;
3231 }
3232 
ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k * ar,struct dp_rx_tid * rx_tid,struct sk_buff * defrag_skb)3233 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3234 					      struct sk_buff *defrag_skb)
3235 {
3236 	struct ath11k_base *ab = ar->ab;
3237 	struct ath11k_pdev_dp *dp = &ar->dp;
3238 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3239 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3240 	struct hal_reo_entrance_ring *reo_ent_ring;
3241 	struct hal_reo_dest_ring *reo_dest_ring;
3242 	struct dp_link_desc_bank *link_desc_banks;
3243 	struct hal_rx_msdu_link *msdu_link;
3244 	struct hal_rx_msdu_details *msdu0;
3245 	struct hal_srng *srng;
3246 	dma_addr_t paddr;
3247 	u32 desc_bank, msdu_info, mpdu_info;
3248 	u32 dst_idx, cookie;
3249 	u32 *msdu_len_offset;
3250 	int ret, buf_id;
3251 
3252 	link_desc_banks = ab->dp.link_desc_banks;
3253 	reo_dest_ring = rx_tid->dst_ring_desc;
3254 
3255 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3256 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3257 			(paddr - link_desc_banks[desc_bank].paddr));
3258 	msdu0 = &msdu_link->msdu_link[0];
3259 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3260 	memset(msdu0, 0, sizeof(*msdu0));
3261 
3262 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3263 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3264 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3265 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3266 			       defrag_skb->len - HAL_RX_DESC_SIZE) |
3267 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3268 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3269 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3270 	msdu0->rx_msdu_info.info0 = msdu_info;
3271 
3272 	/* change msdu len in hal rx desc */
3273 	msdu_len_offset = (u32 *)&rx_desc->msdu_start;
3274 	*msdu_len_offset &= ~(RX_MSDU_START_INFO1_MSDU_LENGTH);
3275 	*msdu_len_offset |= defrag_skb->len - HAL_RX_DESC_SIZE;
3276 
3277 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3278 			       defrag_skb->len + skb_tailroom(defrag_skb),
3279 			       DMA_TO_DEVICE);
3280 	if (dma_mapping_error(ab->dev, paddr))
3281 		return -ENOMEM;
3282 
3283 	spin_lock_bh(&rx_refill_ring->idr_lock);
3284 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3285 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3286 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3287 	if (buf_id < 0) {
3288 		ret = -ENOMEM;
3289 		goto err_unmap_dma;
3290 	}
3291 
3292 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3293 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3294 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3295 
3296 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM);
3297 
3298 	/* Fill mpdu details into reo entrace ring */
3299 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3300 
3301 	spin_lock_bh(&srng->lock);
3302 	ath11k_hal_srng_access_begin(ab, srng);
3303 
3304 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3305 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3306 	if (!reo_ent_ring) {
3307 		ath11k_hal_srng_access_end(ab, srng);
3308 		spin_unlock_bh(&srng->lock);
3309 		ret = -ENOSPC;
3310 		goto err_free_idr;
3311 	}
3312 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3313 
3314 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3315 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3316 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3317 
3318 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3319 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3320 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3321 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3322 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3323 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3324 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3325 
3326 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3327 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3328 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3329 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3330 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3331 						   reo_dest_ring->info0)) |
3332 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3333 	ath11k_hal_srng_access_end(ab, srng);
3334 	spin_unlock_bh(&srng->lock);
3335 
3336 	return 0;
3337 
3338 err_free_idr:
3339 	spin_lock_bh(&rx_refill_ring->idr_lock);
3340 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3341 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3342 err_unmap_dma:
3343 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3344 			 DMA_TO_DEVICE);
3345 	return ret;
3346 }
3347 
ath11k_dp_rx_h_cmp_frags(struct sk_buff * a,struct sk_buff * b)3348 static int ath11k_dp_rx_h_cmp_frags(struct sk_buff *a, struct sk_buff *b)
3349 {
3350 	int frag1, frag2;
3351 
3352 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(a);
3353 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(b);
3354 
3355 	return frag1 - frag2;
3356 }
3357 
ath11k_dp_rx_h_sort_frags(struct sk_buff_head * frag_list,struct sk_buff * cur_frag)3358 static void ath11k_dp_rx_h_sort_frags(struct sk_buff_head *frag_list,
3359 				      struct sk_buff *cur_frag)
3360 {
3361 	struct sk_buff *skb;
3362 	int cmp;
3363 
3364 	skb_queue_walk(frag_list, skb) {
3365 		cmp = ath11k_dp_rx_h_cmp_frags(skb, cur_frag);
3366 		if (cmp < 0)
3367 			continue;
3368 		__skb_queue_before(frag_list, skb, cur_frag);
3369 		return;
3370 	}
3371 	__skb_queue_tail(frag_list, cur_frag);
3372 }
3373 
ath11k_dp_rx_h_get_pn(struct sk_buff * skb)3374 static u64 ath11k_dp_rx_h_get_pn(struct sk_buff *skb)
3375 {
3376 	struct ieee80211_hdr *hdr;
3377 	u64 pn = 0;
3378 	u8 *ehdr;
3379 
3380 	hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE);
3381 	ehdr = skb->data + HAL_RX_DESC_SIZE + ieee80211_hdrlen(hdr->frame_control);
3382 
3383 	pn = ehdr[0];
3384 	pn |= (u64)ehdr[1] << 8;
3385 	pn |= (u64)ehdr[4] << 16;
3386 	pn |= (u64)ehdr[5] << 24;
3387 	pn |= (u64)ehdr[6] << 32;
3388 	pn |= (u64)ehdr[7] << 40;
3389 
3390 	return pn;
3391 }
3392 
3393 static bool
ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k * ar,struct dp_rx_tid * rx_tid)3394 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3395 {
3396 	enum hal_encrypt_type encrypt_type;
3397 	struct sk_buff *first_frag, *skb;
3398 	struct hal_rx_desc *desc;
3399 	u64 last_pn;
3400 	u64 cur_pn;
3401 
3402 	first_frag = skb_peek(&rx_tid->rx_frags);
3403 	desc = (struct hal_rx_desc *)first_frag->data;
3404 
3405 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(desc);
3406 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3407 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3408 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3409 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3410 		return true;
3411 
3412 	last_pn = ath11k_dp_rx_h_get_pn(first_frag);
3413 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3414 		if (skb == first_frag)
3415 			continue;
3416 
3417 		cur_pn = ath11k_dp_rx_h_get_pn(skb);
3418 		if (cur_pn != last_pn + 1)
3419 			return false;
3420 		last_pn = cur_pn;
3421 	}
3422 	return true;
3423 }
3424 
ath11k_dp_rx_frag_h_mpdu(struct ath11k * ar,struct sk_buff * msdu,u32 * ring_desc)3425 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3426 				    struct sk_buff *msdu,
3427 				    u32 *ring_desc)
3428 {
3429 	struct ath11k_base *ab = ar->ab;
3430 	struct hal_rx_desc *rx_desc;
3431 	struct ath11k_peer *peer;
3432 	struct dp_rx_tid *rx_tid;
3433 	struct sk_buff *defrag_skb = NULL;
3434 	u32 peer_id;
3435 	u16 seqno, frag_no;
3436 	u8 tid;
3437 	int ret = 0;
3438 	bool more_frags;
3439 
3440 	rx_desc = (struct hal_rx_desc *)msdu->data;
3441 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(rx_desc);
3442 	tid = ath11k_dp_rx_h_mpdu_start_tid(rx_desc);
3443 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(rx_desc);
3444 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(msdu);
3445 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(msdu);
3446 
3447 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(rx_desc) ||
3448 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(rx_desc) ||
3449 	    tid > IEEE80211_NUM_TIDS)
3450 		return -EINVAL;
3451 
3452 	/* received unfragmented packet in reo
3453 	 * exception ring, this shouldn't happen
3454 	 * as these packets typically come from
3455 	 * reo2sw srngs.
3456 	 */
3457 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3458 		return -EINVAL;
3459 
3460 	spin_lock_bh(&ab->base_lock);
3461 	peer = ath11k_peer_find_by_id(ab, peer_id);
3462 	if (!peer) {
3463 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3464 			    peer_id);
3465 		ret = -ENOENT;
3466 		goto out_unlock;
3467 	}
3468 	rx_tid = &peer->rx_tid[tid];
3469 
3470 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3471 	    skb_queue_empty(&rx_tid->rx_frags)) {
3472 		/* Flush stored fragments and start a new sequence */
3473 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3474 		rx_tid->cur_sn = seqno;
3475 	}
3476 
3477 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3478 		/* Fragment already present */
3479 		ret = -EINVAL;
3480 		goto out_unlock;
3481 	}
3482 
3483 	if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3484 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3485 	else
3486 		ath11k_dp_rx_h_sort_frags(&rx_tid->rx_frags, msdu);
3487 
3488 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3489 	if (!more_frags)
3490 		rx_tid->last_frag_no = frag_no;
3491 
3492 	if (frag_no == 0) {
3493 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3494 						sizeof(*rx_tid->dst_ring_desc),
3495 						GFP_ATOMIC);
3496 		if (!rx_tid->dst_ring_desc) {
3497 			ret = -ENOMEM;
3498 			goto out_unlock;
3499 		}
3500 	} else {
3501 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3502 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3503 	}
3504 
3505 	if (!rx_tid->last_frag_no ||
3506 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3507 		mod_timer(&rx_tid->frag_timer, jiffies +
3508 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3509 		goto out_unlock;
3510 	}
3511 
3512 	spin_unlock_bh(&ab->base_lock);
3513 	del_timer_sync(&rx_tid->frag_timer);
3514 	spin_lock_bh(&ab->base_lock);
3515 
3516 	peer = ath11k_peer_find_by_id(ab, peer_id);
3517 	if (!peer)
3518 		goto err_frags_cleanup;
3519 
3520 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3521 		goto err_frags_cleanup;
3522 
3523 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3524 		goto err_frags_cleanup;
3525 
3526 	if (!defrag_skb)
3527 		goto err_frags_cleanup;
3528 
3529 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3530 		goto err_frags_cleanup;
3531 
3532 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3533 	goto out_unlock;
3534 
3535 err_frags_cleanup:
3536 	dev_kfree_skb_any(defrag_skb);
3537 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3538 out_unlock:
3539 	spin_unlock_bh(&ab->base_lock);
3540 	return ret;
3541 }
3542 
3543 static int
ath11k_dp_process_rx_err_buf(struct ath11k * ar,u32 * ring_desc,int buf_id,bool drop)3544 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3545 {
3546 	struct ath11k_pdev_dp *dp = &ar->dp;
3547 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3548 	struct sk_buff *msdu;
3549 	struct ath11k_skb_rxcb *rxcb;
3550 	struct hal_rx_desc *rx_desc;
3551 	u8 *hdr_status;
3552 	u16 msdu_len;
3553 
3554 	spin_lock_bh(&rx_ring->idr_lock);
3555 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3556 	if (!msdu) {
3557 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3558 			    buf_id);
3559 		spin_unlock_bh(&rx_ring->idr_lock);
3560 		return -EINVAL;
3561 	}
3562 
3563 	idr_remove(&rx_ring->bufs_idr, buf_id);
3564 	spin_unlock_bh(&rx_ring->idr_lock);
3565 
3566 	rxcb = ATH11K_SKB_RXCB(msdu);
3567 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3568 			 msdu->len + skb_tailroom(msdu),
3569 			 DMA_FROM_DEVICE);
3570 
3571 	if (drop) {
3572 		dev_kfree_skb_any(msdu);
3573 		return 0;
3574 	}
3575 
3576 	rcu_read_lock();
3577 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3578 		dev_kfree_skb_any(msdu);
3579 		goto exit;
3580 	}
3581 
3582 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3583 		dev_kfree_skb_any(msdu);
3584 		goto exit;
3585 	}
3586 
3587 	rx_desc = (struct hal_rx_desc *)msdu->data;
3588 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc);
3589 	if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) {
3590 		hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc);
3591 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3592 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3593 				sizeof(struct ieee80211_hdr));
3594 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3595 				sizeof(struct hal_rx_desc));
3596 		dev_kfree_skb_any(msdu);
3597 		goto exit;
3598 	}
3599 
3600 	skb_put(msdu, HAL_RX_DESC_SIZE + msdu_len);
3601 
3602 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3603 		dev_kfree_skb_any(msdu);
3604 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3605 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3606 	}
3607 exit:
3608 	rcu_read_unlock();
3609 	return 0;
3610 }
3611 
ath11k_dp_process_rx_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3612 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3613 			     int budget)
3614 {
3615 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3616 	struct dp_link_desc_bank *link_desc_banks;
3617 	enum hal_rx_buf_return_buf_manager rbm;
3618 	int tot_n_bufs_reaped, quota, ret, i;
3619 	int n_bufs_reaped[MAX_RADIOS] = {0};
3620 	struct dp_rxdma_ring *rx_ring;
3621 	struct dp_srng *reo_except;
3622 	u32 desc_bank, num_msdus;
3623 	struct hal_srng *srng;
3624 	struct ath11k_dp *dp;
3625 	void *link_desc_va;
3626 	int buf_id, mac_id;
3627 	struct ath11k *ar;
3628 	dma_addr_t paddr;
3629 	u32 *desc;
3630 	bool is_frag;
3631 	u8 drop = 0;
3632 
3633 	tot_n_bufs_reaped = 0;
3634 	quota = budget;
3635 
3636 	dp = &ab->dp;
3637 	reo_except = &dp->reo_except_ring;
3638 	link_desc_banks = dp->link_desc_banks;
3639 
3640 	srng = &ab->hal.srng_list[reo_except->ring_id];
3641 
3642 	spin_lock_bh(&srng->lock);
3643 
3644 	ath11k_hal_srng_access_begin(ab, srng);
3645 
3646 	while (budget &&
3647 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3648 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3649 
3650 		ab->soc_stats.err_ring_pkts++;
3651 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3652 						    &desc_bank);
3653 		if (ret) {
3654 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3655 				    ret);
3656 			continue;
3657 		}
3658 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3659 			       (paddr - link_desc_banks[desc_bank].paddr);
3660 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3661 						 &rbm);
3662 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3663 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3664 			ab->soc_stats.invalid_rbm++;
3665 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3666 			ath11k_dp_rx_link_desc_return(ab, desc,
3667 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3668 			continue;
3669 		}
3670 
3671 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3672 
3673 		/* Process only rx fragments with one msdu per link desc below, and drop
3674 		 * msdu's indicated due to error reasons.
3675 		 */
3676 		if (!is_frag || num_msdus > 1) {
3677 			drop = 1;
3678 			/* Return the link desc back to wbm idle list */
3679 			ath11k_dp_rx_link_desc_return(ab, desc,
3680 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3681 		}
3682 
3683 		for (i = 0; i < num_msdus; i++) {
3684 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3685 					   msdu_cookies[i]);
3686 
3687 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3688 					   msdu_cookies[i]);
3689 
3690 			ar = ab->pdevs[mac_id].ar;
3691 
3692 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3693 				n_bufs_reaped[mac_id]++;
3694 				tot_n_bufs_reaped++;
3695 			}
3696 		}
3697 
3698 		if (tot_n_bufs_reaped >= quota) {
3699 			tot_n_bufs_reaped = quota;
3700 			goto exit;
3701 		}
3702 
3703 		budget = quota - tot_n_bufs_reaped;
3704 	}
3705 
3706 exit:
3707 	ath11k_hal_srng_access_end(ab, srng);
3708 
3709 	spin_unlock_bh(&srng->lock);
3710 
3711 	for (i = 0; i <  ab->num_radios; i++) {
3712 		if (!n_bufs_reaped[i])
3713 			continue;
3714 
3715 		ar = ab->pdevs[i].ar;
3716 		rx_ring = &ar->dp.rx_refill_buf_ring;
3717 
3718 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3719 					   HAL_RX_BUF_RBM_SW3_BM);
3720 	}
3721 
3722 	return tot_n_bufs_reaped;
3723 }
3724 
ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k * ar,int msdu_len,struct sk_buff_head * msdu_list)3725 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3726 					     int msdu_len,
3727 					     struct sk_buff_head *msdu_list)
3728 {
3729 	struct sk_buff *skb, *tmp;
3730 	struct ath11k_skb_rxcb *rxcb;
3731 	int n_buffs;
3732 
3733 	n_buffs = DIV_ROUND_UP(msdu_len,
3734 			       (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE));
3735 
3736 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3737 		rxcb = ATH11K_SKB_RXCB(skb);
3738 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3739 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3740 			if (!n_buffs)
3741 				break;
3742 			__skb_unlink(skb, msdu_list);
3743 			dev_kfree_skb_any(skb);
3744 			n_buffs--;
3745 		}
3746 	}
3747 }
3748 
ath11k_dp_rx_h_null_q_desc(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3749 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3750 				      struct ieee80211_rx_status *status,
3751 				      struct sk_buff_head *msdu_list)
3752 {
3753 	u16 msdu_len;
3754 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3755 	u8 l3pad_bytes;
3756 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3757 
3758 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3759 
3760 	if (!rxcb->is_frag && ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE)) {
3761 		/* First buffer will be freed by the caller, so deduct it's length */
3762 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE);
3763 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3764 		return -EINVAL;
3765 	}
3766 
3767 	if (!ath11k_dp_rx_h_attn_msdu_done(desc)) {
3768 		ath11k_warn(ar->ab,
3769 			    "msdu_done bit not set in null_q_des processing\n");
3770 		__skb_queue_purge(msdu_list);
3771 		return -EIO;
3772 	}
3773 
3774 	/* Handle NULL queue descriptor violations arising out a missing
3775 	 * REO queue for a given peer or a given TID. This typically
3776 	 * may happen if a packet is received on a QOS enabled TID before the
3777 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3778 	 * it may also happen for MC/BC frames if they are not routed to the
3779 	 * non-QOS TID queue, in the absence of any other default TID queue.
3780 	 * This error can show up both in a REO destination or WBM release ring.
3781 	 */
3782 
3783 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3784 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3785 
3786 	if (rxcb->is_frag) {
3787 		skb_pull(msdu, HAL_RX_DESC_SIZE);
3788 	} else {
3789 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3790 
3791 		if ((HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3792 			return -EINVAL;
3793 
3794 		skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3795 		skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3796 	}
3797 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3798 
3799 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3800 
3801 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(desc);
3802 
3803 	/* Please note that caller will having the access to msdu and completing
3804 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3805 	 */
3806 
3807 	return 0;
3808 }
3809 
ath11k_dp_rx_h_reo_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status,struct sk_buff_head * msdu_list)3810 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3811 				   struct ieee80211_rx_status *status,
3812 				   struct sk_buff_head *msdu_list)
3813 {
3814 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3815 	bool drop = false;
3816 
3817 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3818 
3819 	switch (rxcb->err_code) {
3820 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
3821 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
3822 			drop = true;
3823 		break;
3824 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
3825 		/* TODO: Do not drop PN failed packets in the driver;
3826 		 * instead, it is good to drop such packets in mac80211
3827 		 * after incrementing the replay counters.
3828 		 */
3829 		fallthrough;
3830 	default:
3831 		/* TODO: Review other errors and process them to mac80211
3832 		 * as appropriate.
3833 		 */
3834 		drop = true;
3835 		break;
3836 	}
3837 
3838 	return drop;
3839 }
3840 
ath11k_dp_rx_h_tkip_mic_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3841 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
3842 					struct ieee80211_rx_status *status)
3843 {
3844 	u16 msdu_len;
3845 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3846 	u8 l3pad_bytes;
3847 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3848 
3849 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc);
3850 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc);
3851 
3852 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc);
3853 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc);
3854 	skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len);
3855 	skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes);
3856 
3857 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3858 
3859 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
3860 			 RX_FLAG_DECRYPTED);
3861 
3862 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
3863 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
3864 }
3865 
ath11k_dp_rx_h_rxdma_err(struct ath11k * ar,struct sk_buff * msdu,struct ieee80211_rx_status * status)3866 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
3867 				     struct ieee80211_rx_status *status)
3868 {
3869 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3870 	bool drop = false;
3871 
3872 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
3873 
3874 	switch (rxcb->err_code) {
3875 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
3876 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
3877 		break;
3878 	default:
3879 		/* TODO: Review other rxdma error code to check if anything is
3880 		 * worth reporting to mac80211
3881 		 */
3882 		drop = true;
3883 		break;
3884 	}
3885 
3886 	return drop;
3887 }
3888 
ath11k_dp_rx_wbm_err(struct ath11k * ar,struct napi_struct * napi,struct sk_buff * msdu,struct sk_buff_head * msdu_list)3889 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
3890 				 struct napi_struct *napi,
3891 				 struct sk_buff *msdu,
3892 				 struct sk_buff_head *msdu_list)
3893 {
3894 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3895 	struct ieee80211_rx_status rxs = {0};
3896 	struct ieee80211_rx_status *status;
3897 	bool drop = true;
3898 
3899 	switch (rxcb->err_rel_src) {
3900 	case HAL_WBM_REL_SRC_MODULE_REO:
3901 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
3902 		break;
3903 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
3904 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
3905 		break;
3906 	default:
3907 		/* msdu will get freed */
3908 		break;
3909 	}
3910 
3911 	if (drop) {
3912 		dev_kfree_skb_any(msdu);
3913 		return;
3914 	}
3915 
3916 	status = IEEE80211_SKB_RXCB(msdu);
3917 	*status = rxs;
3918 
3919 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu);
3920 }
3921 
ath11k_dp_rx_process_wbm_err(struct ath11k_base * ab,struct napi_struct * napi,int budget)3922 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
3923 				 struct napi_struct *napi, int budget)
3924 {
3925 	struct ath11k *ar;
3926 	struct ath11k_dp *dp = &ab->dp;
3927 	struct dp_rxdma_ring *rx_ring;
3928 	struct hal_rx_wbm_rel_info err_info;
3929 	struct hal_srng *srng;
3930 	struct sk_buff *msdu;
3931 	struct sk_buff_head msdu_list[MAX_RADIOS];
3932 	struct ath11k_skb_rxcb *rxcb;
3933 	u32 *rx_desc;
3934 	int buf_id, mac_id;
3935 	int num_buffs_reaped[MAX_RADIOS] = {0};
3936 	int total_num_buffs_reaped = 0;
3937 	int ret, i;
3938 
3939 	for (i = 0; i < ab->num_radios; i++)
3940 		__skb_queue_head_init(&msdu_list[i]);
3941 
3942 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
3943 
3944 	spin_lock_bh(&srng->lock);
3945 
3946 	ath11k_hal_srng_access_begin(ab, srng);
3947 
3948 	while (budget) {
3949 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
3950 		if (!rx_desc)
3951 			break;
3952 
3953 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
3954 		if (ret) {
3955 			ath11k_warn(ab,
3956 				    "failed to parse rx error in wbm_rel ring desc %d\n",
3957 				    ret);
3958 			continue;
3959 		}
3960 
3961 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
3962 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
3963 
3964 		ar = ab->pdevs[mac_id].ar;
3965 		rx_ring = &ar->dp.rx_refill_buf_ring;
3966 
3967 		spin_lock_bh(&rx_ring->idr_lock);
3968 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3969 		if (!msdu) {
3970 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
3971 				    buf_id, mac_id);
3972 			spin_unlock_bh(&rx_ring->idr_lock);
3973 			continue;
3974 		}
3975 
3976 		idr_remove(&rx_ring->bufs_idr, buf_id);
3977 		spin_unlock_bh(&rx_ring->idr_lock);
3978 
3979 		rxcb = ATH11K_SKB_RXCB(msdu);
3980 		dma_unmap_single(ab->dev, rxcb->paddr,
3981 				 msdu->len + skb_tailroom(msdu),
3982 				 DMA_FROM_DEVICE);
3983 
3984 		num_buffs_reaped[mac_id]++;
3985 		total_num_buffs_reaped++;
3986 		budget--;
3987 
3988 		if (err_info.push_reason !=
3989 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
3990 			dev_kfree_skb_any(msdu);
3991 			continue;
3992 		}
3993 
3994 		rxcb->err_rel_src = err_info.err_rel_src;
3995 		rxcb->err_code = err_info.err_code;
3996 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
3997 		__skb_queue_tail(&msdu_list[mac_id], msdu);
3998 	}
3999 
4000 	ath11k_hal_srng_access_end(ab, srng);
4001 
4002 	spin_unlock_bh(&srng->lock);
4003 
4004 	if (!total_num_buffs_reaped)
4005 		goto done;
4006 
4007 	for (i = 0; i <  ab->num_radios; i++) {
4008 		if (!num_buffs_reaped[i])
4009 			continue;
4010 
4011 		ar = ab->pdevs[i].ar;
4012 		rx_ring = &ar->dp.rx_refill_buf_ring;
4013 
4014 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4015 					   HAL_RX_BUF_RBM_SW3_BM);
4016 	}
4017 
4018 	rcu_read_lock();
4019 	for (i = 0; i <  ab->num_radios; i++) {
4020 		if (!rcu_dereference(ab->pdevs_active[i])) {
4021 			__skb_queue_purge(&msdu_list[i]);
4022 			continue;
4023 		}
4024 
4025 		ar = ab->pdevs[i].ar;
4026 
4027 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4028 			__skb_queue_purge(&msdu_list[i]);
4029 			continue;
4030 		}
4031 
4032 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4033 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4034 	}
4035 	rcu_read_unlock();
4036 done:
4037 	return total_num_buffs_reaped;
4038 }
4039 
ath11k_dp_process_rxdma_err(struct ath11k_base * ab,int mac_id,int budget)4040 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4041 {
4042 	struct ath11k *ar;
4043 	struct dp_srng *err_ring;
4044 	struct dp_rxdma_ring *rx_ring;
4045 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4046 	struct hal_srng *srng;
4047 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4048 	enum hal_rx_buf_return_buf_manager rbm;
4049 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4050 	struct ath11k_skb_rxcb *rxcb;
4051 	struct sk_buff *skb;
4052 	struct hal_reo_entrance_ring *entr_ring;
4053 	void *desc;
4054 	int num_buf_freed = 0;
4055 	int quota = budget;
4056 	dma_addr_t paddr;
4057 	u32 desc_bank;
4058 	void *link_desc_va;
4059 	int num_msdus;
4060 	int i;
4061 	int buf_id;
4062 
4063 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4064 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4065 									  mac_id)];
4066 	rx_ring = &ar->dp.rx_refill_buf_ring;
4067 
4068 	srng = &ab->hal.srng_list[err_ring->ring_id];
4069 
4070 	spin_lock_bh(&srng->lock);
4071 
4072 	ath11k_hal_srng_access_begin(ab, srng);
4073 
4074 	while (quota-- &&
4075 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4076 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4077 
4078 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4079 		rxdma_err_code =
4080 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4081 				  entr_ring->info1);
4082 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4083 
4084 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4085 			       (paddr - link_desc_banks[desc_bank].paddr);
4086 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4087 						 msdu_cookies, &rbm);
4088 
4089 		for (i = 0; i < num_msdus; i++) {
4090 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4091 					   msdu_cookies[i]);
4092 
4093 			spin_lock_bh(&rx_ring->idr_lock);
4094 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4095 			if (!skb) {
4096 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4097 					    buf_id);
4098 				spin_unlock_bh(&rx_ring->idr_lock);
4099 				continue;
4100 			}
4101 
4102 			idr_remove(&rx_ring->bufs_idr, buf_id);
4103 			spin_unlock_bh(&rx_ring->idr_lock);
4104 
4105 			rxcb = ATH11K_SKB_RXCB(skb);
4106 			dma_unmap_single(ab->dev, rxcb->paddr,
4107 					 skb->len + skb_tailroom(skb),
4108 					 DMA_FROM_DEVICE);
4109 			dev_kfree_skb_any(skb);
4110 
4111 			num_buf_freed++;
4112 		}
4113 
4114 		ath11k_dp_rx_link_desc_return(ab, desc,
4115 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4116 	}
4117 
4118 	ath11k_hal_srng_access_end(ab, srng);
4119 
4120 	spin_unlock_bh(&srng->lock);
4121 
4122 	if (num_buf_freed)
4123 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4124 					   HAL_RX_BUF_RBM_SW3_BM);
4125 
4126 	return budget - quota;
4127 }
4128 
ath11k_dp_process_reo_status(struct ath11k_base * ab)4129 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4130 {
4131 	struct ath11k_dp *dp = &ab->dp;
4132 	struct hal_srng *srng;
4133 	struct dp_reo_cmd *cmd, *tmp;
4134 	bool found = false;
4135 	u32 *reo_desc;
4136 	u16 tag;
4137 	struct hal_reo_status reo_status;
4138 
4139 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4140 
4141 	memset(&reo_status, 0, sizeof(reo_status));
4142 
4143 	spin_lock_bh(&srng->lock);
4144 
4145 	ath11k_hal_srng_access_begin(ab, srng);
4146 
4147 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4148 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4149 
4150 		switch (tag) {
4151 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4152 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4153 							  &reo_status);
4154 			break;
4155 		case HAL_REO_FLUSH_QUEUE_STATUS:
4156 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4157 							  &reo_status);
4158 			break;
4159 		case HAL_REO_FLUSH_CACHE_STATUS:
4160 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4161 							  &reo_status);
4162 			break;
4163 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4164 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4165 							  &reo_status);
4166 			break;
4167 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4168 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4169 								 &reo_status);
4170 			break;
4171 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4172 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4173 								  &reo_status);
4174 			break;
4175 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4176 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4177 								  &reo_status);
4178 			break;
4179 		default:
4180 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4181 			continue;
4182 		}
4183 
4184 		spin_lock_bh(&dp->reo_cmd_lock);
4185 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4186 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4187 				found = true;
4188 				list_del(&cmd->list);
4189 				break;
4190 			}
4191 		}
4192 		spin_unlock_bh(&dp->reo_cmd_lock);
4193 
4194 		if (found) {
4195 			cmd->handler(dp, (void *)&cmd->data,
4196 				     reo_status.uniform_hdr.cmd_status);
4197 			kfree(cmd);
4198 		}
4199 
4200 		found = false;
4201 	}
4202 
4203 	ath11k_hal_srng_access_end(ab, srng);
4204 
4205 	spin_unlock_bh(&srng->lock);
4206 }
4207 
ath11k_dp_rx_pdev_free(struct ath11k_base * ab,int mac_id)4208 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4209 {
4210 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4211 
4212 	ath11k_dp_rx_pdev_srng_free(ar);
4213 	ath11k_dp_rxdma_pdev_buf_free(ar);
4214 }
4215 
ath11k_dp_rx_pdev_alloc(struct ath11k_base * ab,int mac_id)4216 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4217 {
4218 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4219 	struct ath11k_pdev_dp *dp = &ar->dp;
4220 	u32 ring_id;
4221 	int i;
4222 	int ret;
4223 
4224 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4225 	if (ret) {
4226 		ath11k_warn(ab, "failed to setup rx srngs\n");
4227 		return ret;
4228 	}
4229 
4230 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4231 	if (ret) {
4232 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4233 		return ret;
4234 	}
4235 
4236 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4237 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4238 	if (ret) {
4239 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4240 			    ret);
4241 		return ret;
4242 	}
4243 
4244 	if (ab->hw_params.rx_mac_buf_ring) {
4245 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4246 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4247 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4248 							  mac_id + i, HAL_RXDMA_BUF);
4249 			if (ret) {
4250 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4251 					    i, ret);
4252 				return ret;
4253 			}
4254 		}
4255 	}
4256 
4257 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4258 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4259 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4260 						  mac_id + i, HAL_RXDMA_DST);
4261 		if (ret) {
4262 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4263 				    i, ret);
4264 			return ret;
4265 		}
4266 	}
4267 
4268 	if (!ab->hw_params.rxdma1_enable)
4269 		goto config_refill_ring;
4270 
4271 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4272 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4273 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4274 	if (ret) {
4275 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4276 			    ret);
4277 		return ret;
4278 	}
4279 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4280 					  dp->rxdma_mon_dst_ring.ring_id,
4281 					  mac_id, HAL_RXDMA_MONITOR_DST);
4282 	if (ret) {
4283 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4284 			    ret);
4285 		return ret;
4286 	}
4287 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4288 					  dp->rxdma_mon_desc_ring.ring_id,
4289 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4290 	if (ret) {
4291 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4292 			    ret);
4293 		return ret;
4294 	}
4295 
4296 config_refill_ring:
4297 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4298 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4299 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4300 						  HAL_RXDMA_MONITOR_STATUS);
4301 		if (ret) {
4302 			ath11k_warn(ab,
4303 				    "failed to configure mon_status_refill_ring%d %d\n",
4304 				    i, ret);
4305 			return ret;
4306 		}
4307 	}
4308 
4309 	return 0;
4310 }
4311 
ath11k_dp_mon_set_frag_len(u32 * total_len,u32 * frag_len)4312 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4313 {
4314 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4315 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4316 		*total_len -= *frag_len;
4317 	} else {
4318 		*frag_len = *total_len;
4319 		*total_len = 0;
4320 	}
4321 }
4322 
4323 static
ath11k_dp_rx_monitor_link_desc_return(struct ath11k * ar,void * p_last_buf_addr_info,u8 mac_id)4324 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4325 					  void *p_last_buf_addr_info,
4326 					  u8 mac_id)
4327 {
4328 	struct ath11k_pdev_dp *dp = &ar->dp;
4329 	struct dp_srng *dp_srng;
4330 	void *hal_srng;
4331 	void *src_srng_desc;
4332 	int ret = 0;
4333 
4334 	if (ar->ab->hw_params.rxdma1_enable) {
4335 		dp_srng = &dp->rxdma_mon_desc_ring;
4336 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4337 	} else {
4338 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4339 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4340 	}
4341 
4342 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4343 
4344 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4345 
4346 	if (src_srng_desc) {
4347 		struct ath11k_buffer_addr *src_desc =
4348 				(struct ath11k_buffer_addr *)src_srng_desc;
4349 
4350 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4351 	} else {
4352 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4353 			   "Monitor Link Desc Ring %d Full", mac_id);
4354 		ret = -ENOMEM;
4355 	}
4356 
4357 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4358 	return ret;
4359 }
4360 
4361 static
ath11k_dp_rx_mon_next_link_desc_get(void * rx_msdu_link_desc,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,void ** pp_buf_addr_info)4362 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4363 					 dma_addr_t *paddr, u32 *sw_cookie,
4364 					 u8 *rbm,
4365 					 void **pp_buf_addr_info)
4366 {
4367 	struct hal_rx_msdu_link *msdu_link =
4368 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4369 	struct ath11k_buffer_addr *buf_addr_info;
4370 
4371 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4372 
4373 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4374 
4375 	*pp_buf_addr_info = (void *)buf_addr_info;
4376 }
4377 
ath11k_dp_pkt_set_pktlen(struct sk_buff * skb,u32 len)4378 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4379 {
4380 	if (skb->len > len) {
4381 		skb_trim(skb, len);
4382 	} else {
4383 		if (skb_tailroom(skb) < len - skb->len) {
4384 			if ((pskb_expand_head(skb, 0,
4385 					      len - skb->len - skb_tailroom(skb),
4386 					      GFP_ATOMIC))) {
4387 				dev_kfree_skb_any(skb);
4388 				return -ENOMEM;
4389 			}
4390 		}
4391 		skb_put(skb, (len - skb->len));
4392 	}
4393 	return 0;
4394 }
4395 
ath11k_hal_rx_msdu_list_get(struct ath11k * ar,void * msdu_link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)4396 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4397 					void *msdu_link_desc,
4398 					struct hal_rx_msdu_list *msdu_list,
4399 					u16 *num_msdus)
4400 {
4401 	struct hal_rx_msdu_details *msdu_details = NULL;
4402 	struct rx_msdu_desc *msdu_desc_info = NULL;
4403 	struct hal_rx_msdu_link *msdu_link = NULL;
4404 	int i;
4405 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4406 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4407 	u8  tmp  = 0;
4408 
4409 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4410 	msdu_details = &msdu_link->msdu_link[0];
4411 
4412 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4413 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4414 			      msdu_details[i].buf_addr_info.info0) == 0) {
4415 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4416 			msdu_desc_info->info0 |= last;
4417 			;
4418 			break;
4419 		}
4420 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4421 
4422 		if (!i)
4423 			msdu_desc_info->info0 |= first;
4424 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4425 			msdu_desc_info->info0 |= last;
4426 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4427 		msdu_list->msdu_info[i].msdu_len =
4428 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4429 		msdu_list->sw_cookie[i] =
4430 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4431 				  msdu_details[i].buf_addr_info.info1);
4432 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4433 				msdu_details[i].buf_addr_info.info1);
4434 		msdu_list->rbm[i] = tmp;
4435 	}
4436 	*num_msdus = i;
4437 }
4438 
ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id,u32 * ppdu_id,u32 * rx_bufs_used)4439 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4440 					u32 *rx_bufs_used)
4441 {
4442 	u32 ret = 0;
4443 
4444 	if ((*ppdu_id < msdu_ppdu_id) &&
4445 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4446 		*ppdu_id = msdu_ppdu_id;
4447 		ret = msdu_ppdu_id;
4448 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4449 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4450 		/* mon_dst is behind than mon_status
4451 		 * skip dst_ring and free it
4452 		 */
4453 		*rx_bufs_used += 1;
4454 		*ppdu_id = msdu_ppdu_id;
4455 		ret = msdu_ppdu_id;
4456 	}
4457 	return ret;
4458 }
4459 
ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)4460 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4461 				      bool *is_frag, u32 *total_len,
4462 				      u32 *frag_len, u32 *msdu_cnt)
4463 {
4464 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4465 		if (!*is_frag) {
4466 			*total_len = info->msdu_len;
4467 			*is_frag = true;
4468 		}
4469 		ath11k_dp_mon_set_frag_len(total_len,
4470 					   frag_len);
4471 	} else {
4472 		if (*is_frag) {
4473 			ath11k_dp_mon_set_frag_len(total_len,
4474 						   frag_len);
4475 		} else {
4476 			*frag_len = info->msdu_len;
4477 		}
4478 		*is_frag = false;
4479 		*msdu_cnt -= 1;
4480 	}
4481 }
4482 
4483 static u32
ath11k_dp_rx_mon_mpdu_pop(struct ath11k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,u32 * npackets,u32 * ppdu_id)4484 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4485 			  void *ring_entry, struct sk_buff **head_msdu,
4486 			  struct sk_buff **tail_msdu, u32 *npackets,
4487 			  u32 *ppdu_id)
4488 {
4489 	struct ath11k_pdev_dp *dp = &ar->dp;
4490 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4491 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4492 	struct sk_buff *msdu = NULL, *last = NULL;
4493 	struct hal_rx_msdu_list msdu_list;
4494 	void *p_buf_addr_info, *p_last_buf_addr_info;
4495 	struct hal_rx_desc *rx_desc;
4496 	void *rx_msdu_link_desc;
4497 	dma_addr_t paddr;
4498 	u16 num_msdus = 0;
4499 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4500 	u32 rx_bufs_used = 0, i = 0;
4501 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4502 	u32 total_len = 0, frag_len = 0;
4503 	bool is_frag, is_first_msdu;
4504 	bool drop_mpdu = false;
4505 	struct ath11k_skb_rxcb *rxcb;
4506 	struct hal_reo_entrance_ring *ent_desc =
4507 			(struct hal_reo_entrance_ring *)ring_entry;
4508 	int buf_id;
4509 	u32 rx_link_buf_info[2];
4510 	u8 rbm;
4511 
4512 	if (!ar->ab->hw_params.rxdma1_enable)
4513 		rx_ring = &dp->rx_refill_buf_ring;
4514 
4515 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4516 					    &sw_cookie,
4517 					    &p_last_buf_addr_info, &rbm,
4518 					    &msdu_cnt);
4519 
4520 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4521 		      ent_desc->info1) ==
4522 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4523 		u8 rxdma_err =
4524 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4525 				  ent_desc->info1);
4526 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4527 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4528 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4529 			drop_mpdu = true;
4530 			pmon->rx_mon_stats.dest_mpdu_drop++;
4531 		}
4532 	}
4533 
4534 	is_frag = false;
4535 	is_first_msdu = true;
4536 
4537 	do {
4538 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4539 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4540 			return rx_bufs_used;
4541 		}
4542 
4543 		if (ar->ab->hw_params.rxdma1_enable)
4544 			rx_msdu_link_desc =
4545 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4546 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4547 		else
4548 			rx_msdu_link_desc =
4549 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4550 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4551 
4552 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4553 					    &num_msdus);
4554 
4555 		for (i = 0; i < num_msdus; i++) {
4556 			u32 l2_hdr_offset;
4557 
4558 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4559 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4560 					   "i %d last_cookie %d is same\n",
4561 					   i, pmon->mon_last_buf_cookie);
4562 				drop_mpdu = true;
4563 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4564 				continue;
4565 			}
4566 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4567 					   msdu_list.sw_cookie[i]);
4568 
4569 			spin_lock_bh(&rx_ring->idr_lock);
4570 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4571 			spin_unlock_bh(&rx_ring->idr_lock);
4572 			if (!msdu) {
4573 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4574 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4575 				break;
4576 			}
4577 			rxcb = ATH11K_SKB_RXCB(msdu);
4578 			if (!rxcb->unmapped) {
4579 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4580 						 msdu->len +
4581 						 skb_tailroom(msdu),
4582 						 DMA_FROM_DEVICE);
4583 				rxcb->unmapped = 1;
4584 			}
4585 			if (drop_mpdu) {
4586 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4587 					   "i %d drop msdu %p *ppdu_id %x\n",
4588 					   i, msdu, *ppdu_id);
4589 				dev_kfree_skb_any(msdu);
4590 				msdu = NULL;
4591 				goto next_msdu;
4592 			}
4593 
4594 			rx_desc = (struct hal_rx_desc *)msdu->data;
4595 
4596 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4597 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(rx_desc);
4598 
4599 			if (is_first_msdu) {
4600 				if (!ath11k_dp_rxdesc_mpdu_valid(rx_desc)) {
4601 					drop_mpdu = true;
4602 					dev_kfree_skb_any(msdu);
4603 					msdu = NULL;
4604 					pmon->mon_last_linkdesc_paddr = paddr;
4605 					goto next_msdu;
4606 				}
4607 
4608 				msdu_ppdu_id =
4609 					ath11k_dp_rxdesc_get_ppduid(rx_desc);
4610 
4611 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4612 								 ppdu_id,
4613 								 &rx_bufs_used)) {
4614 					if (rx_bufs_used) {
4615 						drop_mpdu = true;
4616 						dev_kfree_skb_any(msdu);
4617 						msdu = NULL;
4618 						goto next_msdu;
4619 					}
4620 					return rx_bufs_used;
4621 				}
4622 				pmon->mon_last_linkdesc_paddr = paddr;
4623 				is_first_msdu = false;
4624 			}
4625 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4626 						  &is_frag, &total_len,
4627 						  &frag_len, &msdu_cnt);
4628 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4629 
4630 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4631 
4632 			if (!(*head_msdu))
4633 				*head_msdu = msdu;
4634 			else if (last)
4635 				last->next = msdu;
4636 
4637 			last = msdu;
4638 next_msdu:
4639 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4640 			rx_bufs_used++;
4641 			spin_lock_bh(&rx_ring->idr_lock);
4642 			idr_remove(&rx_ring->bufs_idr, buf_id);
4643 			spin_unlock_bh(&rx_ring->idr_lock);
4644 		}
4645 
4646 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4647 
4648 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4649 						    &sw_cookie, &rbm,
4650 						    &p_buf_addr_info);
4651 
4652 		if (ar->ab->hw_params.rxdma1_enable) {
4653 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4654 								  p_last_buf_addr_info,
4655 								  dp->mac_id))
4656 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4657 					   "dp_rx_monitor_link_desc_return failed");
4658 		} else {
4659 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4660 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4661 		}
4662 
4663 		p_last_buf_addr_info = p_buf_addr_info;
4664 
4665 	} while (paddr && msdu_cnt);
4666 
4667 	if (last)
4668 		last->next = NULL;
4669 
4670 	*tail_msdu = msdu;
4671 
4672 	if (msdu_cnt == 0)
4673 		*npackets = 1;
4674 
4675 	return rx_bufs_used;
4676 }
4677 
ath11k_dp_rx_msdus_set_payload(struct sk_buff * msdu)4678 static void ath11k_dp_rx_msdus_set_payload(struct sk_buff *msdu)
4679 {
4680 	u32 rx_pkt_offset, l2_hdr_offset;
4681 
4682 	rx_pkt_offset = sizeof(struct hal_rx_desc);
4683 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad((struct hal_rx_desc *)msdu->data);
4684 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4685 }
4686 
4687 static struct sk_buff *
ath11k_dp_rx_mon_merg_msdus(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * last_msdu,struct ieee80211_rx_status * rxs)4688 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4689 			    u32 mac_id, struct sk_buff *head_msdu,
4690 			    struct sk_buff *last_msdu,
4691 			    struct ieee80211_rx_status *rxs)
4692 {
4693 	struct sk_buff *msdu, *mpdu_buf, *prev_buf;
4694 	u32 decap_format, wifi_hdr_len;
4695 	struct hal_rx_desc *rx_desc;
4696 	char *hdr_desc;
4697 	u8 *dest;
4698 	struct ieee80211_hdr_3addr *wh;
4699 
4700 	mpdu_buf = NULL;
4701 
4702 	if (!head_msdu)
4703 		goto err_merge_fail;
4704 
4705 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4706 
4707 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_desc))
4708 		return NULL;
4709 
4710 	decap_format = ath11k_dp_rxdesc_get_decap_format(rx_desc);
4711 
4712 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4713 
4714 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4715 		ath11k_dp_rx_msdus_set_payload(head_msdu);
4716 
4717 		prev_buf = head_msdu;
4718 		msdu = head_msdu->next;
4719 
4720 		while (msdu) {
4721 			ath11k_dp_rx_msdus_set_payload(msdu);
4722 
4723 			prev_buf = msdu;
4724 			msdu = msdu->next;
4725 		}
4726 
4727 		prev_buf->next = NULL;
4728 
4729 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4730 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4731 		__le16 qos_field;
4732 		u8 qos_pkt = 0;
4733 
4734 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4735 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4736 
4737 		/* Base size */
4738 		wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4739 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4740 
4741 		if (ieee80211_is_data_qos(wh->frame_control)) {
4742 			struct ieee80211_qos_hdr *qwh =
4743 					(struct ieee80211_qos_hdr *)hdr_desc;
4744 
4745 			qos_field = qwh->qos_ctrl;
4746 			qos_pkt = 1;
4747 		}
4748 		msdu = head_msdu;
4749 
4750 		while (msdu) {
4751 			rx_desc = (struct hal_rx_desc *)msdu->data;
4752 			hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc);
4753 
4754 			if (qos_pkt) {
4755 				dest = skb_push(msdu, sizeof(__le16));
4756 				if (!dest)
4757 					goto err_merge_fail;
4758 				memcpy(dest, hdr_desc, wifi_hdr_len);
4759 				memcpy(dest + wifi_hdr_len,
4760 				       (u8 *)&qos_field, sizeof(__le16));
4761 			}
4762 			ath11k_dp_rx_msdus_set_payload(msdu);
4763 			prev_buf = msdu;
4764 			msdu = msdu->next;
4765 		}
4766 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4767 		if (!dest)
4768 			goto err_merge_fail;
4769 
4770 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4771 			   "mpdu_buf %pK mpdu_buf->len %u",
4772 			   prev_buf, prev_buf->len);
4773 	} else {
4774 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4775 			   "decap format %d is not supported!\n",
4776 			   decap_format);
4777 		goto err_merge_fail;
4778 	}
4779 
4780 	return head_msdu;
4781 
4782 err_merge_fail:
4783 	if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) {
4784 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4785 			   "err_merge_fail mpdu_buf %pK", mpdu_buf);
4786 		/* Free the head buffer */
4787 		dev_kfree_skb_any(mpdu_buf);
4788 	}
4789 	return NULL;
4790 }
4791 
ath11k_dp_rx_mon_deliver(struct ath11k * ar,u32 mac_id,struct sk_buff * head_msdu,struct sk_buff * tail_msdu,struct napi_struct * napi)4792 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4793 				    struct sk_buff *head_msdu,
4794 				    struct sk_buff *tail_msdu,
4795 				    struct napi_struct *napi)
4796 {
4797 	struct ath11k_pdev_dp *dp = &ar->dp;
4798 	struct sk_buff *mon_skb, *skb_next, *header;
4799 	struct ieee80211_rx_status *rxs = &dp->rx_status, *status;
4800 
4801 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4802 					      tail_msdu, rxs);
4803 
4804 	if (!mon_skb)
4805 		goto mon_deliver_fail;
4806 
4807 	header = mon_skb;
4808 
4809 	rxs->flag = 0;
4810 	do {
4811 		skb_next = mon_skb->next;
4812 		if (!skb_next)
4813 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4814 		else
4815 			rxs->flag |= RX_FLAG_AMSDU_MORE;
4816 
4817 		if (mon_skb == header) {
4818 			header = NULL;
4819 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
4820 		} else {
4821 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
4822 		}
4823 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
4824 
4825 		status = IEEE80211_SKB_RXCB(mon_skb);
4826 		*status = *rxs;
4827 
4828 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb);
4829 		mon_skb = skb_next;
4830 	} while (mon_skb);
4831 	rxs->flag = 0;
4832 
4833 	return 0;
4834 
4835 mon_deliver_fail:
4836 	mon_skb = head_msdu;
4837 	while (mon_skb) {
4838 		skb_next = mon_skb->next;
4839 		dev_kfree_skb_any(mon_skb);
4840 		mon_skb = skb_next;
4841 	}
4842 	return -EINVAL;
4843 }
4844 
ath11k_dp_rx_mon_dest_process(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4845 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
4846 					  u32 quota, struct napi_struct *napi)
4847 {
4848 	struct ath11k_pdev_dp *dp = &ar->dp;
4849 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4850 	void *ring_entry;
4851 	void *mon_dst_srng;
4852 	u32 ppdu_id;
4853 	u32 rx_bufs_used;
4854 	u32 ring_id;
4855 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4856 	u32	 npackets = 0;
4857 
4858 	if (ar->ab->hw_params.rxdma1_enable)
4859 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
4860 	else
4861 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
4862 
4863 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
4864 
4865 	if (!mon_dst_srng) {
4866 		ath11k_warn(ar->ab,
4867 			    "HAL Monitor Destination Ring Init Failed -- %pK",
4868 			    mon_dst_srng);
4869 		return;
4870 	}
4871 
4872 	spin_lock_bh(&pmon->mon_lock);
4873 
4874 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
4875 
4876 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
4877 	rx_bufs_used = 0;
4878 	rx_mon_stats = &pmon->rx_mon_stats;
4879 
4880 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
4881 		struct sk_buff *head_msdu, *tail_msdu;
4882 
4883 		head_msdu = NULL;
4884 		tail_msdu = NULL;
4885 
4886 		rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
4887 							  &head_msdu,
4888 							  &tail_msdu,
4889 							  &npackets, &ppdu_id);
4890 
4891 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
4892 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4893 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4894 				   "dest_rx: new ppdu_id %x != status ppdu_id %x",
4895 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id);
4896 			break;
4897 		}
4898 		if (head_msdu && tail_msdu) {
4899 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
4900 						 tail_msdu, napi);
4901 			rx_mon_stats->dest_mpdu_done++;
4902 		}
4903 
4904 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
4905 								mon_dst_srng);
4906 	}
4907 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
4908 
4909 	spin_unlock_bh(&pmon->mon_lock);
4910 
4911 	if (rx_bufs_used) {
4912 		rx_mon_stats->dest_ppdu_done++;
4913 		if (ar->ab->hw_params.rxdma1_enable)
4914 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4915 						   &dp->rxdma_mon_buf_ring,
4916 						   rx_bufs_used,
4917 						   HAL_RX_BUF_RBM_SW3_BM);
4918 		else
4919 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
4920 						   &dp->rx_refill_buf_ring,
4921 						   rx_bufs_used,
4922 						   HAL_RX_BUF_RBM_SW3_BM);
4923 	}
4924 }
4925 
ath11k_dp_rx_mon_status_process_tlv(struct ath11k * ar,int mac_id,u32 quota,struct napi_struct * napi)4926 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
4927 						int mac_id, u32 quota,
4928 						struct napi_struct *napi)
4929 {
4930 	struct ath11k_pdev_dp *dp = &ar->dp;
4931 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4932 	struct hal_rx_mon_ppdu_info *ppdu_info;
4933 	struct sk_buff *status_skb;
4934 	u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
4935 	struct ath11k_pdev_mon_stats *rx_mon_stats;
4936 
4937 	ppdu_info = &pmon->mon_ppdu_info;
4938 	rx_mon_stats = &pmon->rx_mon_stats;
4939 
4940 	if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
4941 		return;
4942 
4943 	while (!skb_queue_empty(&pmon->rx_status_q)) {
4944 		status_skb = skb_dequeue(&pmon->rx_status_q);
4945 
4946 		tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
4947 							    status_skb);
4948 		if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
4949 			rx_mon_stats->status_ppdu_done++;
4950 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
4951 			ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
4952 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4953 		}
4954 		dev_kfree_skb_any(status_skb);
4955 	}
4956 }
4957 
ath11k_dp_mon_process_rx(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4958 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
4959 				    struct napi_struct *napi, int budget)
4960 {
4961 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4962 	struct ath11k_pdev_dp *dp = &ar->dp;
4963 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4964 	int num_buffs_reaped = 0;
4965 
4966 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
4967 							     &pmon->rx_status_q);
4968 	if (num_buffs_reaped)
4969 		ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
4970 
4971 	return num_buffs_reaped;
4972 }
4973 
ath11k_dp_rx_process_mon_rings(struct ath11k_base * ab,int mac_id,struct napi_struct * napi,int budget)4974 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
4975 				   struct napi_struct *napi, int budget)
4976 {
4977 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
4978 	int ret = 0;
4979 
4980 	if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags))
4981 		ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
4982 	else
4983 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
4984 	return ret;
4985 }
4986 
ath11k_dp_rx_pdev_mon_status_attach(struct ath11k * ar)4987 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
4988 {
4989 	struct ath11k_pdev_dp *dp = &ar->dp;
4990 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4991 
4992 	skb_queue_head_init(&pmon->rx_status_q);
4993 
4994 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
4995 
4996 	memset(&pmon->rx_mon_stats, 0,
4997 	       sizeof(pmon->rx_mon_stats));
4998 	return 0;
4999 }
5000 
ath11k_dp_rx_pdev_mon_attach(struct ath11k * ar)5001 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5002 {
5003 	struct ath11k_pdev_dp *dp = &ar->dp;
5004 	struct ath11k_mon_data *pmon = &dp->mon_data;
5005 	struct hal_srng *mon_desc_srng = NULL;
5006 	struct dp_srng *dp_srng;
5007 	int ret = 0;
5008 	u32 n_link_desc = 0;
5009 
5010 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5011 	if (ret) {
5012 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5013 		return ret;
5014 	}
5015 
5016 	/* if rxdma1_enable is false, no need to setup
5017 	 * rxdma_mon_desc_ring.
5018 	 */
5019 	if (!ar->ab->hw_params.rxdma1_enable)
5020 		return 0;
5021 
5022 	dp_srng = &dp->rxdma_mon_desc_ring;
5023 	n_link_desc = dp_srng->size /
5024 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5025 	mon_desc_srng =
5026 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5027 
5028 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5029 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5030 					n_link_desc);
5031 	if (ret) {
5032 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5033 		return ret;
5034 	}
5035 	pmon->mon_last_linkdesc_paddr = 0;
5036 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5037 	spin_lock_init(&pmon->mon_lock);
5038 
5039 	return 0;
5040 }
5041 
ath11k_dp_mon_link_free(struct ath11k * ar)5042 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5043 {
5044 	struct ath11k_pdev_dp *dp = &ar->dp;
5045 	struct ath11k_mon_data *pmon = &dp->mon_data;
5046 
5047 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5048 				    HAL_RXDMA_MONITOR_DESC,
5049 				    &dp->rxdma_mon_desc_ring);
5050 	return 0;
5051 }
5052 
ath11k_dp_rx_pdev_mon_detach(struct ath11k * ar)5053 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5054 {
5055 	ath11k_dp_mon_link_free(ar);
5056 	return 0;
5057 }
5058