1 /*
2 * NXP Wireless LAN device driver: PCIE specific handling
3 *
4 * Copyright 2011-2020 NXP
5 *
6 * This software file (the "File") is distributed by NXP
7 * under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20 #include <linux/iopoll.h>
21 #include <linux/firmware.h>
22
23 #include "decl.h"
24 #include "ioctl.h"
25 #include "util.h"
26 #include "fw.h"
27 #include "main.h"
28 #include "wmm.h"
29 #include "11n.h"
30 #include "pcie.h"
31
32 #define PCIE_VERSION "1.0"
33 #define DRV_NAME "Marvell mwifiex PCIe"
34
35 static struct mwifiex_if_ops pcie_ops;
36
37 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
38 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
39 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
40 .cmd_size = PCIE_SCRATCH_2_REG,
41 .fw_status = PCIE_SCRATCH_3_REG,
42 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
43 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
44 .tx_rdptr = PCIE_SCRATCH_6_REG,
45 .tx_wrptr = PCIE_SCRATCH_7_REG,
46 .rx_rdptr = PCIE_SCRATCH_8_REG,
47 .rx_wrptr = PCIE_SCRATCH_9_REG,
48 .evt_rdptr = PCIE_SCRATCH_10_REG,
49 .evt_wrptr = PCIE_SCRATCH_11_REG,
50 .drv_rdy = PCIE_SCRATCH_12_REG,
51 .tx_start_ptr = 0,
52 .tx_mask = MWIFIEX_TXBD_MASK,
53 .tx_wrap_mask = 0,
54 .rx_mask = MWIFIEX_RXBD_MASK,
55 .rx_wrap_mask = 0,
56 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
57 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
58 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
59 .ring_flag_sop = 0,
60 .ring_flag_eop = 0,
61 .ring_flag_xs_sop = 0,
62 .ring_flag_xs_eop = 0,
63 .ring_tx_start_ptr = 0,
64 .pfu_enabled = 0,
65 .sleep_cookie = 1,
66 .msix_support = 0,
67 };
68
69 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
70 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
71 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
72 .cmd_size = PCIE_SCRATCH_2_REG,
73 .fw_status = PCIE_SCRATCH_3_REG,
74 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
75 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
76 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
77 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
78 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
79 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
80 .evt_rdptr = PCIE_SCRATCH_10_REG,
81 .evt_wrptr = PCIE_SCRATCH_11_REG,
82 .drv_rdy = PCIE_SCRATCH_12_REG,
83 .tx_start_ptr = 16,
84 .tx_mask = 0x03FF0000,
85 .tx_wrap_mask = 0x07FF0000,
86 .rx_mask = 0x000003FF,
87 .rx_wrap_mask = 0x000007FF,
88 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
89 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
90 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
91 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
92 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
93 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
94 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
95 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
96 .pfu_enabled = 1,
97 .sleep_cookie = 0,
98 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
99 .fw_dump_start = PCIE_SCRATCH_14_REG,
100 .fw_dump_end = 0xcff,
101 .fw_dump_host_ready = 0xee,
102 .fw_dump_read_done = 0xfe,
103 .msix_support = 0,
104 };
105
106 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
107 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
108 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
109 .cmd_size = PCIE_SCRATCH_2_REG,
110 .fw_status = PCIE_SCRATCH_3_REG,
111 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
112 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
113 .tx_rdptr = 0xC1A4,
114 .tx_wrptr = 0xC174,
115 .rx_rdptr = 0xC174,
116 .rx_wrptr = 0xC1A4,
117 .evt_rdptr = PCIE_SCRATCH_10_REG,
118 .evt_wrptr = PCIE_SCRATCH_11_REG,
119 .drv_rdy = PCIE_SCRATCH_12_REG,
120 .tx_start_ptr = 16,
121 .tx_mask = 0x0FFF0000,
122 .tx_wrap_mask = 0x1FFF0000,
123 .rx_mask = 0x00000FFF,
124 .rx_wrap_mask = 0x00001FFF,
125 .tx_rollover_ind = BIT(28),
126 .rx_rollover_ind = BIT(12),
127 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
128 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
129 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
130 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
131 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
132 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
133 .pfu_enabled = 1,
134 .sleep_cookie = 0,
135 .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
136 .fw_dump_start = PCIE_SCRATCH_14_REG,
137 .fw_dump_end = 0xcff,
138 .fw_dump_host_ready = 0xcc,
139 .fw_dump_read_done = 0xdd,
140 .msix_support = 0,
141 };
142
143 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
144 {"ITCM", NULL, 0, 0xF0},
145 {"DTCM", NULL, 0, 0xF1},
146 {"SQRAM", NULL, 0, 0xF2},
147 {"IRAM", NULL, 0, 0xF3},
148 {"APU", NULL, 0, 0xF4},
149 {"CIU", NULL, 0, 0xF5},
150 {"ICU", NULL, 0, 0xF6},
151 {"MAC", NULL, 0, 0xF7},
152 };
153
154 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
155 {"DUMP", NULL, 0, 0xDD},
156 };
157
158 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
159 .reg = &mwifiex_reg_8766,
160 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
161 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
162 .can_dump_fw = false,
163 .can_ext_scan = true,
164 };
165
166 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
167 .reg = &mwifiex_reg_8897,
168 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
169 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
170 .can_dump_fw = true,
171 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
172 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
173 .can_ext_scan = true,
174 };
175
176 static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
177 .reg = &mwifiex_reg_8997,
178 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
179 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
180 .can_dump_fw = true,
181 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
182 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
183 .can_ext_scan = true,
184 };
185
186 static const struct of_device_id mwifiex_pcie_of_match_table[] = {
187 { .compatible = "pci11ab,2b42" },
188 { .compatible = "pci1b4b,2b42" },
189 { }
190 };
191
mwifiex_pcie_probe_of(struct device * dev)192 static int mwifiex_pcie_probe_of(struct device *dev)
193 {
194 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
195 dev_err(dev, "required compatible string missing\n");
196 return -EINVAL;
197 }
198
199 return 0;
200 }
201
202 static void mwifiex_pcie_work(struct work_struct *work);
203
204 static int
mwifiex_map_pci_memory(struct mwifiex_adapter * adapter,struct sk_buff * skb,size_t size,int flags)205 mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
206 size_t size, int flags)
207 {
208 struct pcie_service_card *card = adapter->card;
209 struct mwifiex_dma_mapping mapping;
210
211 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags);
212 if (dma_mapping_error(&card->dev->dev, mapping.addr)) {
213 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
214 return -1;
215 }
216 mapping.len = size;
217 mwifiex_store_mapping(skb, &mapping);
218 return 0;
219 }
220
mwifiex_unmap_pci_memory(struct mwifiex_adapter * adapter,struct sk_buff * skb,int flags)221 static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
222 struct sk_buff *skb, int flags)
223 {
224 struct pcie_service_card *card = adapter->card;
225 struct mwifiex_dma_mapping mapping;
226
227 mwifiex_get_mapping(skb, &mapping);
228 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags);
229 }
230
231 /*
232 * This function writes data into PCIE card register.
233 */
mwifiex_write_reg(struct mwifiex_adapter * adapter,int reg,u32 data)234 static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
235 {
236 struct pcie_service_card *card = adapter->card;
237
238 iowrite32(data, card->pci_mmap1 + reg);
239
240 return 0;
241 }
242
243 /* This function reads data from PCIE card register.
244 */
mwifiex_read_reg(struct mwifiex_adapter * adapter,int reg,u32 * data)245 static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
246 {
247 struct pcie_service_card *card = adapter->card;
248
249 *data = ioread32(card->pci_mmap1 + reg);
250 if (*data == 0xffffffff)
251 return 0xffffffff;
252
253 return 0;
254 }
255
256 /* This function reads u8 data from PCIE card register. */
mwifiex_read_reg_byte(struct mwifiex_adapter * adapter,int reg,u8 * data)257 static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
258 int reg, u8 *data)
259 {
260 struct pcie_service_card *card = adapter->card;
261
262 *data = ioread8(card->pci_mmap1 + reg);
263
264 return 0;
265 }
266
267 /*
268 * This function reads sleep cookie and checks if FW is ready
269 */
mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter * adapter)270 static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
271 {
272 u32 cookie_value;
273 struct pcie_service_card *card = adapter->card;
274 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
275
276 if (!reg->sleep_cookie)
277 return true;
278
279 if (card->sleep_cookie_vbase) {
280 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase);
281 mwifiex_dbg(adapter, INFO,
282 "info: ACCESS_HW: sleep cookie=0x%x\n",
283 cookie_value);
284 if (cookie_value == FW_AWAKE_COOKIE)
285 return true;
286 }
287
288 return false;
289 }
290
291 #ifdef CONFIG_PM_SLEEP
292 /*
293 * Kernel needs to suspend all functions separately. Therefore all
294 * registered functions must have drivers with suspend and resume
295 * methods. Failing that the kernel simply removes the whole card.
296 *
297 * If already not suspended, this function allocates and sends a host
298 * sleep activate request to the firmware and turns off the traffic.
299 */
mwifiex_pcie_suspend(struct device * dev)300 static int mwifiex_pcie_suspend(struct device *dev)
301 {
302 struct mwifiex_adapter *adapter;
303 struct pcie_service_card *card = dev_get_drvdata(dev);
304
305
306 /* Might still be loading firmware */
307 wait_for_completion(&card->fw_done);
308
309 adapter = card->adapter;
310 if (!adapter) {
311 dev_err(dev, "adapter is not valid\n");
312 return 0;
313 }
314
315 mwifiex_enable_wake(adapter);
316
317 /* Enable the Host Sleep */
318 if (!mwifiex_enable_hs(adapter)) {
319 mwifiex_dbg(adapter, ERROR,
320 "cmd: failed to suspend\n");
321 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
322 mwifiex_disable_wake(adapter);
323 return -EFAULT;
324 }
325
326 flush_workqueue(adapter->workqueue);
327
328 /* Indicate device suspended */
329 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
330 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
331
332 return 0;
333 }
334
335 /*
336 * Kernel needs to suspend all functions separately. Therefore all
337 * registered functions must have drivers with suspend and resume
338 * methods. Failing that the kernel simply removes the whole card.
339 *
340 * If already not resumed, this function turns on the traffic and
341 * sends a host sleep cancel request to the firmware.
342 */
mwifiex_pcie_resume(struct device * dev)343 static int mwifiex_pcie_resume(struct device *dev)
344 {
345 struct mwifiex_adapter *adapter;
346 struct pcie_service_card *card = dev_get_drvdata(dev);
347
348
349 if (!card->adapter) {
350 dev_err(dev, "adapter structure is not valid\n");
351 return 0;
352 }
353
354 adapter = card->adapter;
355
356 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
357 mwifiex_dbg(adapter, WARN,
358 "Device already resumed\n");
359 return 0;
360 }
361
362 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
363
364 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
365 MWIFIEX_ASYNC_CMD);
366 mwifiex_disable_wake(adapter);
367
368 return 0;
369 }
370 #endif
371
372 /*
373 * This function probes an mwifiex device and registers it. It allocates
374 * the card structure, enables PCIE function number and initiates the
375 * device registration and initialization procedure by adding a logical
376 * interface.
377 */
mwifiex_pcie_probe(struct pci_dev * pdev,const struct pci_device_id * ent)378 static int mwifiex_pcie_probe(struct pci_dev *pdev,
379 const struct pci_device_id *ent)
380 {
381 struct pcie_service_card *card;
382 int ret;
383
384 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
385 pdev->vendor, pdev->device, pdev->revision);
386
387 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
388 if (!card)
389 return -ENOMEM;
390
391 init_completion(&card->fw_done);
392
393 card->dev = pdev;
394
395 if (ent->driver_data) {
396 struct mwifiex_pcie_device *data = (void *)ent->driver_data;
397 card->pcie.reg = data->reg;
398 card->pcie.blksz_fw_dl = data->blksz_fw_dl;
399 card->pcie.tx_buf_size = data->tx_buf_size;
400 card->pcie.can_dump_fw = data->can_dump_fw;
401 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
402 card->pcie.num_mem_types = data->num_mem_types;
403 card->pcie.can_ext_scan = data->can_ext_scan;
404 INIT_WORK(&card->work, mwifiex_pcie_work);
405 }
406
407 /* device tree node parsing and platform specific configuration*/
408 if (pdev->dev.of_node) {
409 ret = mwifiex_pcie_probe_of(&pdev->dev);
410 if (ret)
411 return ret;
412 }
413
414 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops,
415 MWIFIEX_PCIE, &pdev->dev)) {
416 pr_err("%s failed\n", __func__);
417 return -1;
418 }
419
420 return 0;
421 }
422
423 /*
424 * This function removes the interface and frees up the card structure.
425 */
mwifiex_pcie_remove(struct pci_dev * pdev)426 static void mwifiex_pcie_remove(struct pci_dev *pdev)
427 {
428 struct pcie_service_card *card;
429 struct mwifiex_adapter *adapter;
430 struct mwifiex_private *priv;
431 const struct mwifiex_pcie_card_reg *reg;
432 u32 fw_status;
433 int ret;
434
435 card = pci_get_drvdata(pdev);
436
437 wait_for_completion(&card->fw_done);
438
439 adapter = card->adapter;
440 if (!adapter || !adapter->priv_num)
441 return;
442
443 reg = card->pcie.reg;
444 if (reg)
445 ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
446 else
447 fw_status = -1;
448
449 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) {
450 mwifiex_deauthenticate_all(adapter);
451
452 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
453
454 mwifiex_disable_auto_ds(priv);
455
456 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
457 }
458
459 mwifiex_remove_card(adapter);
460 }
461
mwifiex_pcie_shutdown(struct pci_dev * pdev)462 static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
463 {
464 mwifiex_pcie_remove(pdev);
465
466 return;
467 }
468
mwifiex_pcie_coredump(struct device * dev)469 static void mwifiex_pcie_coredump(struct device *dev)
470 {
471 struct pci_dev *pdev;
472 struct pcie_service_card *card;
473
474 pdev = container_of(dev, struct pci_dev, dev);
475 card = pci_get_drvdata(pdev);
476
477 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
478 &card->work_flags))
479 schedule_work(&card->work);
480 }
481
482 static const struct pci_device_id mwifiex_ids[] = {
483 {
484 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
486 .driver_data = (unsigned long)&mwifiex_pcie8766,
487 },
488 {
489 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
491 .driver_data = (unsigned long)&mwifiex_pcie8897,
492 },
493 {
494 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
496 .driver_data = (unsigned long)&mwifiex_pcie8997,
497 },
498 {
499 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
501 .driver_data = (unsigned long)&mwifiex_pcie8997,
502 },
503 {},
504 };
505
506 MODULE_DEVICE_TABLE(pci, mwifiex_ids);
507
508 /*
509 * Cleanup all software without cleaning anything related to PCIe and HW.
510 */
mwifiex_pcie_reset_prepare(struct pci_dev * pdev)511 static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev)
512 {
513 struct pcie_service_card *card = pci_get_drvdata(pdev);
514 struct mwifiex_adapter *adapter = card->adapter;
515
516 if (!adapter) {
517 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
518 __func__);
519 return;
520 }
521
522 mwifiex_dbg(adapter, INFO,
523 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n",
524 __func__, pdev->vendor, pdev->device, pdev->revision);
525
526 mwifiex_shutdown_sw(adapter);
527 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
528 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
529 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
530
531 card->pci_reset_ongoing = true;
532 }
533
534 /*
535 * Kernel stores and restores PCIe function context before and after performing
536 * FLR respectively. Reconfigure the software and firmware including firmware
537 * redownload.
538 */
mwifiex_pcie_reset_done(struct pci_dev * pdev)539 static void mwifiex_pcie_reset_done(struct pci_dev *pdev)
540 {
541 struct pcie_service_card *card = pci_get_drvdata(pdev);
542 struct mwifiex_adapter *adapter = card->adapter;
543 int ret;
544
545 if (!adapter) {
546 dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
547 __func__);
548 return;
549 }
550
551 mwifiex_dbg(adapter, INFO,
552 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n",
553 __func__, pdev->vendor, pdev->device, pdev->revision);
554
555 ret = mwifiex_reinit_sw(adapter);
556 if (ret)
557 dev_err(&pdev->dev, "reinit failed: %d\n", ret);
558 else
559 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
560
561 card->pci_reset_ongoing = false;
562 }
563
564 static const struct pci_error_handlers mwifiex_pcie_err_handler = {
565 .reset_prepare = mwifiex_pcie_reset_prepare,
566 .reset_done = mwifiex_pcie_reset_done,
567 };
568
569 #ifdef CONFIG_PM_SLEEP
570 /* Power Management Hooks */
571 static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
572 mwifiex_pcie_resume);
573 #endif
574
575 /* PCI Device Driver */
576 static struct pci_driver __refdata mwifiex_pcie = {
577 .name = "mwifiex_pcie",
578 .id_table = mwifiex_ids,
579 .probe = mwifiex_pcie_probe,
580 .remove = mwifiex_pcie_remove,
581 .driver = {
582 .coredump = mwifiex_pcie_coredump,
583 #ifdef CONFIG_PM_SLEEP
584 .pm = &mwifiex_pcie_pm_ops,
585 #endif
586 },
587 .shutdown = mwifiex_pcie_shutdown,
588 .err_handler = &mwifiex_pcie_err_handler,
589 };
590
591 /*
592 * This function adds delay loop to ensure FW is awake before proceeding.
593 */
mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter * adapter)594 static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
595 {
596 int i = 0;
597
598 while (mwifiex_pcie_ok_to_access_hw(adapter)) {
599 i++;
600 usleep_range(10, 20);
601 /* 50ms max wait */
602 if (i == 5000)
603 break;
604 }
605
606 return;
607 }
608
mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter * adapter,u32 max_delay_loop_cnt)609 static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
610 u32 max_delay_loop_cnt)
611 {
612 struct pcie_service_card *card = adapter->card;
613 u8 *buffer;
614 u32 sleep_cookie, count;
615 struct sk_buff *cmdrsp = card->cmdrsp_buf;
616
617 for (count = 0; count < max_delay_loop_cnt; count++) {
618 dma_sync_single_for_cpu(&card->dev->dev,
619 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
620 sizeof(sleep_cookie), DMA_FROM_DEVICE);
621 buffer = cmdrsp->data;
622 sleep_cookie = get_unaligned_le32(buffer);
623
624 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
625 mwifiex_dbg(adapter, INFO,
626 "sleep cookie found at count %d\n", count);
627 break;
628 }
629 dma_sync_single_for_device(&card->dev->dev,
630 MWIFIEX_SKB_DMA_ADDR(cmdrsp),
631 sizeof(sleep_cookie),
632 DMA_FROM_DEVICE);
633 usleep_range(20, 30);
634 }
635
636 if (count >= max_delay_loop_cnt)
637 mwifiex_dbg(adapter, INFO,
638 "max count reached while accessing sleep cookie\n");
639 }
640
641 #define N_WAKEUP_TRIES_SHORT_INTERVAL 15
642 #define N_WAKEUP_TRIES_LONG_INTERVAL 35
643
644 /* This function wakes up the card by reading fw_status register. */
mwifiex_pm_wakeup_card(struct mwifiex_adapter * adapter)645 static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
646 {
647 struct pcie_service_card *card = adapter->card;
648 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
649 int retval;
650
651 mwifiex_dbg(adapter, EVENT,
652 "event: Wakeup device...\n");
653
654 if (reg->sleep_cookie)
655 mwifiex_pcie_dev_wakeup_delay(adapter);
656
657 /* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes
658 * appears to ignore or miss our wakeup request, so we continue trying
659 * until we receive an interrupt from the card.
660 */
661 if (read_poll_timeout(mwifiex_write_reg, retval,
662 READ_ONCE(adapter->int_status) != 0,
663 500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL,
664 false,
665 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
666 if (read_poll_timeout(mwifiex_write_reg, retval,
667 READ_ONCE(adapter->int_status) != 0,
668 10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL,
669 false,
670 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
671 mwifiex_dbg(adapter, ERROR,
672 "Firmware didn't wake up\n");
673 return -EIO;
674 }
675 }
676
677 if (reg->sleep_cookie) {
678 mwifiex_pcie_dev_wakeup_delay(adapter);
679 mwifiex_dbg(adapter, INFO,
680 "PCIE wakeup: Setting PS_STATE_AWAKE\n");
681 adapter->ps_state = PS_STATE_AWAKE;
682 }
683
684 return 0;
685 }
686
687 /*
688 * This function is called after the card has woken up.
689 *
690 * The card configuration register is reset.
691 */
mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter * adapter)692 static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
693 {
694 mwifiex_dbg(adapter, CMD,
695 "cmd: Wakeup device completed\n");
696
697 return 0;
698 }
699
700 /*
701 * This function disables the host interrupt.
702 *
703 * The host interrupt mask is read, the disable bit is reset and
704 * written back to the card host interrupt mask register.
705 */
mwifiex_pcie_disable_host_int(struct mwifiex_adapter * adapter)706 static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
707 {
708 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
709 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
710 0x00000000)) {
711 mwifiex_dbg(adapter, ERROR,
712 "Disable host interrupt failed\n");
713 return -1;
714 }
715 }
716
717 atomic_set(&adapter->tx_hw_pending, 0);
718 return 0;
719 }
720
mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter * adapter)721 static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
722 {
723 WARN_ON(mwifiex_pcie_disable_host_int(adapter));
724 }
725
726 /*
727 * This function enables the host interrupt.
728 *
729 * The host interrupt enable mask is written to the card
730 * host interrupt mask register.
731 */
mwifiex_pcie_enable_host_int(struct mwifiex_adapter * adapter)732 static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
733 {
734 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
735 /* Simply write the mask to the register */
736 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
737 HOST_INTR_MASK)) {
738 mwifiex_dbg(adapter, ERROR,
739 "Enable host interrupt failed\n");
740 return -1;
741 }
742 }
743
744 return 0;
745 }
746
747 /*
748 * This function initializes TX buffer ring descriptors
749 */
mwifiex_init_txq_ring(struct mwifiex_adapter * adapter)750 static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
751 {
752 struct pcie_service_card *card = adapter->card;
753 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
754 struct mwifiex_pcie_buf_desc *desc;
755 struct mwifiex_pfu_buf_desc *desc2;
756 int i;
757
758 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
759 card->tx_buf_list[i] = NULL;
760 if (reg->pfu_enabled) {
761 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
762 (sizeof(*desc2) * i);
763 desc2 = card->txbd_ring[i];
764 memset(desc2, 0, sizeof(*desc2));
765 } else {
766 card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
767 (sizeof(*desc) * i);
768 desc = card->txbd_ring[i];
769 memset(desc, 0, sizeof(*desc));
770 }
771 }
772
773 return 0;
774 }
775
776 /* This function initializes RX buffer ring descriptors. Each SKB is allocated
777 * here and after mapping PCI memory, its physical address is assigned to
778 * PCIE Rx buffer descriptor's physical address.
779 */
mwifiex_init_rxq_ring(struct mwifiex_adapter * adapter)780 static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
781 {
782 struct pcie_service_card *card = adapter->card;
783 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
784 struct sk_buff *skb;
785 struct mwifiex_pcie_buf_desc *desc;
786 struct mwifiex_pfu_buf_desc *desc2;
787 dma_addr_t buf_pa;
788 int i;
789
790 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
791 /* Allocate skb here so that firmware can DMA data from it */
792 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
793 GFP_KERNEL);
794 if (!skb) {
795 mwifiex_dbg(adapter, ERROR,
796 "Unable to allocate skb for RX ring.\n");
797 kfree(card->rxbd_ring_vbase);
798 return -ENOMEM;
799 }
800
801 if (mwifiex_map_pci_memory(adapter, skb,
802 MWIFIEX_RX_DATA_BUF_SIZE,
803 DMA_FROM_DEVICE))
804 return -1;
805
806 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
807
808 mwifiex_dbg(adapter, INFO,
809 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
810 skb, skb->len, skb->data, (u32)buf_pa,
811 (u32)((u64)buf_pa >> 32));
812
813 card->rx_buf_list[i] = skb;
814 if (reg->pfu_enabled) {
815 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
816 (sizeof(*desc2) * i);
817 desc2 = card->rxbd_ring[i];
818 desc2->paddr = buf_pa;
819 desc2->len = (u16)skb->len;
820 desc2->frag_len = (u16)skb->len;
821 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
822 desc2->offset = 0;
823 } else {
824 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
825 (sizeof(*desc) * i));
826 desc = card->rxbd_ring[i];
827 desc->paddr = buf_pa;
828 desc->len = (u16)skb->len;
829 desc->flags = 0;
830 }
831 }
832
833 return 0;
834 }
835
836 /* This function initializes event buffer ring descriptors. Each SKB is
837 * allocated here and after mapping PCI memory, its physical address is assigned
838 * to PCIE Rx buffer descriptor's physical address
839 */
mwifiex_pcie_init_evt_ring(struct mwifiex_adapter * adapter)840 static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
841 {
842 struct pcie_service_card *card = adapter->card;
843 struct mwifiex_evt_buf_desc *desc;
844 struct sk_buff *skb;
845 dma_addr_t buf_pa;
846 int i;
847
848 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
849 /* Allocate skb here so that firmware can DMA data from it */
850 skb = dev_alloc_skb(MAX_EVENT_SIZE);
851 if (!skb) {
852 mwifiex_dbg(adapter, ERROR,
853 "Unable to allocate skb for EVENT buf.\n");
854 kfree(card->evtbd_ring_vbase);
855 return -ENOMEM;
856 }
857 skb_put(skb, MAX_EVENT_SIZE);
858
859 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
860 DMA_FROM_DEVICE)) {
861 kfree_skb(skb);
862 kfree(card->evtbd_ring_vbase);
863 return -1;
864 }
865
866 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
867
868 mwifiex_dbg(adapter, EVENT,
869 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
870 skb, skb->len, skb->data, (u32)buf_pa,
871 (u32)((u64)buf_pa >> 32));
872
873 card->evt_buf_list[i] = skb;
874 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
875 (sizeof(*desc) * i));
876 desc = card->evtbd_ring[i];
877 desc->paddr = buf_pa;
878 desc->len = (u16)skb->len;
879 desc->flags = 0;
880 }
881
882 return 0;
883 }
884
885 /* This function cleans up TX buffer rings. If any of the buffer list has valid
886 * SKB address, associated SKB is freed.
887 */
mwifiex_cleanup_txq_ring(struct mwifiex_adapter * adapter)888 static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
889 {
890 struct pcie_service_card *card = adapter->card;
891 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
892 struct sk_buff *skb;
893 struct mwifiex_pcie_buf_desc *desc;
894 struct mwifiex_pfu_buf_desc *desc2;
895 int i;
896
897 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
898 if (reg->pfu_enabled) {
899 desc2 = card->txbd_ring[i];
900 if (card->tx_buf_list[i]) {
901 skb = card->tx_buf_list[i];
902 mwifiex_unmap_pci_memory(adapter, skb,
903 DMA_TO_DEVICE);
904 dev_kfree_skb_any(skb);
905 }
906 memset(desc2, 0, sizeof(*desc2));
907 } else {
908 desc = card->txbd_ring[i];
909 if (card->tx_buf_list[i]) {
910 skb = card->tx_buf_list[i];
911 mwifiex_unmap_pci_memory(adapter, skb,
912 DMA_TO_DEVICE);
913 dev_kfree_skb_any(skb);
914 }
915 memset(desc, 0, sizeof(*desc));
916 }
917 card->tx_buf_list[i] = NULL;
918 }
919
920 atomic_set(&adapter->tx_hw_pending, 0);
921 return;
922 }
923
924 /* This function cleans up RX buffer rings. If any of the buffer list has valid
925 * SKB address, associated SKB is freed.
926 */
mwifiex_cleanup_rxq_ring(struct mwifiex_adapter * adapter)927 static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
928 {
929 struct pcie_service_card *card = adapter->card;
930 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
931 struct mwifiex_pcie_buf_desc *desc;
932 struct mwifiex_pfu_buf_desc *desc2;
933 struct sk_buff *skb;
934 int i;
935
936 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
937 if (reg->pfu_enabled) {
938 desc2 = card->rxbd_ring[i];
939 if (card->rx_buf_list[i]) {
940 skb = card->rx_buf_list[i];
941 mwifiex_unmap_pci_memory(adapter, skb,
942 DMA_FROM_DEVICE);
943 dev_kfree_skb_any(skb);
944 }
945 memset(desc2, 0, sizeof(*desc2));
946 } else {
947 desc = card->rxbd_ring[i];
948 if (card->rx_buf_list[i]) {
949 skb = card->rx_buf_list[i];
950 mwifiex_unmap_pci_memory(adapter, skb,
951 DMA_FROM_DEVICE);
952 dev_kfree_skb_any(skb);
953 }
954 memset(desc, 0, sizeof(*desc));
955 }
956 card->rx_buf_list[i] = NULL;
957 }
958
959 return;
960 }
961
962 /* This function cleans up event buffer rings. If any of the buffer list has
963 * valid SKB address, associated SKB is freed.
964 */
mwifiex_cleanup_evt_ring(struct mwifiex_adapter * adapter)965 static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
966 {
967 struct pcie_service_card *card = adapter->card;
968 struct mwifiex_evt_buf_desc *desc;
969 struct sk_buff *skb;
970 int i;
971
972 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
973 desc = card->evtbd_ring[i];
974 if (card->evt_buf_list[i]) {
975 skb = card->evt_buf_list[i];
976 mwifiex_unmap_pci_memory(adapter, skb,
977 DMA_FROM_DEVICE);
978 dev_kfree_skb_any(skb);
979 }
980 card->evt_buf_list[i] = NULL;
981 memset(desc, 0, sizeof(*desc));
982 }
983
984 return;
985 }
986
987 /* This function creates buffer descriptor ring for TX
988 */
mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter * adapter)989 static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
990 {
991 struct pcie_service_card *card = adapter->card;
992 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
993
994 /*
995 * driver maintaines the write pointer and firmware maintaines the read
996 * pointer. The write pointer starts at 0 (zero) while the read pointer
997 * starts at zero with rollover bit set
998 */
999 card->txbd_wrptr = 0;
1000
1001 if (reg->pfu_enabled)
1002 card->txbd_rdptr = 0;
1003 else
1004 card->txbd_rdptr |= reg->tx_rollover_ind;
1005
1006 /* allocate shared memory for the BD ring and divide the same in to
1007 several descriptors */
1008 if (reg->pfu_enabled)
1009 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1010 MWIFIEX_MAX_TXRX_BD;
1011 else
1012 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1013 MWIFIEX_MAX_TXRX_BD;
1014
1015 mwifiex_dbg(adapter, INFO,
1016 "info: txbd_ring: Allocating %d bytes\n",
1017 card->txbd_ring_size);
1018 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1019 card->txbd_ring_size,
1020 &card->txbd_ring_pbase,
1021 GFP_KERNEL);
1022 if (!card->txbd_ring_vbase) {
1023 mwifiex_dbg(adapter, ERROR,
1024 "allocate coherent memory (%d bytes) failed!\n",
1025 card->txbd_ring_size);
1026 return -ENOMEM;
1027 }
1028
1029 mwifiex_dbg(adapter, DATA,
1030 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1031 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase,
1032 (u32)((u64)card->txbd_ring_pbase >> 32),
1033 card->txbd_ring_size);
1034
1035 return mwifiex_init_txq_ring(adapter);
1036 }
1037
mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter * adapter)1038 static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter)
1039 {
1040 struct pcie_service_card *card = adapter->card;
1041 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1042
1043 mwifiex_cleanup_txq_ring(adapter);
1044
1045 if (card->txbd_ring_vbase)
1046 dma_free_coherent(&card->dev->dev, card->txbd_ring_size,
1047 card->txbd_ring_vbase,
1048 card->txbd_ring_pbase);
1049 card->txbd_ring_size = 0;
1050 card->txbd_wrptr = 0;
1051 card->txbd_rdptr = 0 | reg->tx_rollover_ind;
1052 card->txbd_ring_vbase = NULL;
1053 card->txbd_ring_pbase = 0;
1054
1055 return 0;
1056 }
1057
1058 /*
1059 * This function creates buffer descriptor ring for RX
1060 */
mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter * adapter)1061 static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter)
1062 {
1063 struct pcie_service_card *card = adapter->card;
1064 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1065
1066 /*
1067 * driver maintaines the read pointer and firmware maintaines the write
1068 * pointer. The write pointer starts at 0 (zero) while the read pointer
1069 * starts at zero with rollover bit set
1070 */
1071 card->rxbd_wrptr = 0;
1072 card->rxbd_rdptr = reg->rx_rollover_ind;
1073
1074 if (reg->pfu_enabled)
1075 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) *
1076 MWIFIEX_MAX_TXRX_BD;
1077 else
1078 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) *
1079 MWIFIEX_MAX_TXRX_BD;
1080
1081 mwifiex_dbg(adapter, INFO,
1082 "info: rxbd_ring: Allocating %d bytes\n",
1083 card->rxbd_ring_size);
1084 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1085 card->rxbd_ring_size,
1086 &card->rxbd_ring_pbase,
1087 GFP_KERNEL);
1088 if (!card->rxbd_ring_vbase) {
1089 mwifiex_dbg(adapter, ERROR,
1090 "allocate coherent memory (%d bytes) failed!\n",
1091 card->rxbd_ring_size);
1092 return -ENOMEM;
1093 }
1094
1095 mwifiex_dbg(adapter, DATA,
1096 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n",
1097 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase,
1098 (u32)((u64)card->rxbd_ring_pbase >> 32),
1099 card->rxbd_ring_size);
1100
1101 return mwifiex_init_rxq_ring(adapter);
1102 }
1103
1104 /*
1105 * This function deletes Buffer descriptor ring for RX
1106 */
mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter * adapter)1107 static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter)
1108 {
1109 struct pcie_service_card *card = adapter->card;
1110 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1111
1112 mwifiex_cleanup_rxq_ring(adapter);
1113
1114 if (card->rxbd_ring_vbase)
1115 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size,
1116 card->rxbd_ring_vbase,
1117 card->rxbd_ring_pbase);
1118 card->rxbd_ring_size = 0;
1119 card->rxbd_wrptr = 0;
1120 card->rxbd_rdptr = 0 | reg->rx_rollover_ind;
1121 card->rxbd_ring_vbase = NULL;
1122 card->rxbd_ring_pbase = 0;
1123
1124 return 0;
1125 }
1126
1127 /*
1128 * This function creates buffer descriptor ring for Events
1129 */
mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter * adapter)1130 static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter)
1131 {
1132 struct pcie_service_card *card = adapter->card;
1133 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1134
1135 /*
1136 * driver maintaines the read pointer and firmware maintaines the write
1137 * pointer. The write pointer starts at 0 (zero) while the read pointer
1138 * starts at zero with rollover bit set
1139 */
1140 card->evtbd_wrptr = 0;
1141 card->evtbd_rdptr = reg->evt_rollover_ind;
1142
1143 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) *
1144 MWIFIEX_MAX_EVT_BD;
1145
1146 mwifiex_dbg(adapter, INFO,
1147 "info: evtbd_ring: Allocating %d bytes\n",
1148 card->evtbd_ring_size);
1149 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev,
1150 card->evtbd_ring_size,
1151 &card->evtbd_ring_pbase,
1152 GFP_KERNEL);
1153 if (!card->evtbd_ring_vbase) {
1154 mwifiex_dbg(adapter, ERROR,
1155 "allocate coherent memory (%d bytes) failed!\n",
1156 card->evtbd_ring_size);
1157 return -ENOMEM;
1158 }
1159
1160 mwifiex_dbg(adapter, EVENT,
1161 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n",
1162 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase,
1163 (u32)((u64)card->evtbd_ring_pbase >> 32),
1164 card->evtbd_ring_size);
1165
1166 return mwifiex_pcie_init_evt_ring(adapter);
1167 }
1168
1169 /*
1170 * This function deletes Buffer descriptor ring for Events
1171 */
mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter * adapter)1172 static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter)
1173 {
1174 struct pcie_service_card *card = adapter->card;
1175 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1176
1177 mwifiex_cleanup_evt_ring(adapter);
1178
1179 if (card->evtbd_ring_vbase)
1180 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size,
1181 card->evtbd_ring_vbase,
1182 card->evtbd_ring_pbase);
1183 card->evtbd_wrptr = 0;
1184 card->evtbd_rdptr = 0 | reg->evt_rollover_ind;
1185 card->evtbd_ring_size = 0;
1186 card->evtbd_ring_vbase = NULL;
1187 card->evtbd_ring_pbase = 0;
1188
1189 return 0;
1190 }
1191
1192 /*
1193 * This function allocates a buffer for CMDRSP
1194 */
mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter * adapter)1195 static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter)
1196 {
1197 struct pcie_service_card *card = adapter->card;
1198 struct sk_buff *skb;
1199
1200 /* Allocate memory for receiving command response data */
1201 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
1202 if (!skb) {
1203 mwifiex_dbg(adapter, ERROR,
1204 "Unable to allocate skb for command response data.\n");
1205 return -ENOMEM;
1206 }
1207 skb_put(skb, MWIFIEX_UPLD_SIZE);
1208 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1209 DMA_FROM_DEVICE)) {
1210 kfree_skb(skb);
1211 return -1;
1212 }
1213
1214 card->cmdrsp_buf = skb;
1215
1216 return 0;
1217 }
1218
1219 /*
1220 * This function deletes a buffer for CMDRSP
1221 */
mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter * adapter)1222 static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter)
1223 {
1224 struct pcie_service_card *card;
1225
1226 if (!adapter)
1227 return 0;
1228
1229 card = adapter->card;
1230
1231 if (card && card->cmdrsp_buf) {
1232 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf,
1233 DMA_FROM_DEVICE);
1234 dev_kfree_skb_any(card->cmdrsp_buf);
1235 card->cmdrsp_buf = NULL;
1236 }
1237
1238 if (card && card->cmd_buf) {
1239 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1240 DMA_TO_DEVICE);
1241 dev_kfree_skb_any(card->cmd_buf);
1242 card->cmd_buf = NULL;
1243 }
1244 return 0;
1245 }
1246
1247 /*
1248 * This function allocates a buffer for sleep cookie
1249 */
mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter * adapter)1250 static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1251 {
1252 struct pcie_service_card *card = adapter->card;
1253 u32 *cookie;
1254
1255 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev,
1256 sizeof(u32),
1257 &card->sleep_cookie_pbase,
1258 GFP_KERNEL);
1259 if (!card->sleep_cookie_vbase) {
1260 mwifiex_dbg(adapter, ERROR,
1261 "dma_alloc_coherent failed!\n");
1262 return -ENOMEM;
1263 }
1264 cookie = (u32 *)card->sleep_cookie_vbase;
1265 /* Init val of Sleep Cookie */
1266 *cookie = FW_AWAKE_COOKIE;
1267
1268 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie);
1269
1270 return 0;
1271 }
1272
1273 /*
1274 * This function deletes buffer for sleep cookie
1275 */
mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter * adapter)1276 static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter)
1277 {
1278 struct pcie_service_card *card;
1279
1280 if (!adapter)
1281 return 0;
1282
1283 card = adapter->card;
1284
1285 if (card && card->sleep_cookie_vbase) {
1286 dma_free_coherent(&card->dev->dev, sizeof(u32),
1287 card->sleep_cookie_vbase,
1288 card->sleep_cookie_pbase);
1289 card->sleep_cookie_vbase = NULL;
1290 }
1291
1292 return 0;
1293 }
1294
1295 /* This function flushes the TX buffer descriptor ring
1296 * This function defined as handler is also called while cleaning TXRX
1297 * during disconnect/ bss stop.
1298 */
mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter * adapter)1299 static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter)
1300 {
1301 struct pcie_service_card *card = adapter->card;
1302
1303 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) {
1304 card->txbd_flush = 1;
1305 /* write pointer already set at last send
1306 * send dnld-rdy intr again, wait for completion.
1307 */
1308 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1309 CPU_INTR_DNLD_RDY)) {
1310 mwifiex_dbg(adapter, ERROR,
1311 "failed to assert dnld-rdy interrupt.\n");
1312 return -1;
1313 }
1314 }
1315 return 0;
1316 }
1317
1318 /*
1319 * This function unmaps and frees downloaded data buffer
1320 */
mwifiex_pcie_send_data_complete(struct mwifiex_adapter * adapter)1321 static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter)
1322 {
1323 struct sk_buff *skb;
1324 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0;
1325 struct mwifiex_pcie_buf_desc *desc;
1326 struct mwifiex_pfu_buf_desc *desc2;
1327 struct pcie_service_card *card = adapter->card;
1328 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1329
1330 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1331 mwifiex_pm_wakeup_card(adapter);
1332
1333 /* Read the TX ring read pointer set by firmware */
1334 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) {
1335 mwifiex_dbg(adapter, ERROR,
1336 "SEND COMP: failed to read reg->tx_rdptr\n");
1337 return -1;
1338 }
1339
1340 mwifiex_dbg(adapter, DATA,
1341 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n",
1342 card->txbd_rdptr, rdptr);
1343
1344 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1345 /* free from previous txbd_rdptr to current txbd_rdptr */
1346 while (((card->txbd_rdptr & reg->tx_mask) !=
1347 (rdptr & reg->tx_mask)) ||
1348 ((card->txbd_rdptr & reg->tx_rollover_ind) !=
1349 (rdptr & reg->tx_rollover_ind))) {
1350 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >>
1351 reg->tx_start_ptr;
1352
1353 skb = card->tx_buf_list[wrdoneidx];
1354
1355 if (skb) {
1356 mwifiex_dbg(adapter, DATA,
1357 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n",
1358 skb, wrdoneidx);
1359 mwifiex_unmap_pci_memory(adapter, skb,
1360 DMA_TO_DEVICE);
1361
1362 unmap_count++;
1363
1364 if (card->txbd_flush)
1365 mwifiex_write_data_complete(adapter, skb, 0,
1366 -1);
1367 else
1368 mwifiex_write_data_complete(adapter, skb, 0, 0);
1369 atomic_dec(&adapter->tx_hw_pending);
1370 }
1371
1372 card->tx_buf_list[wrdoneidx] = NULL;
1373
1374 if (reg->pfu_enabled) {
1375 desc2 = card->txbd_ring[wrdoneidx];
1376 memset(desc2, 0, sizeof(*desc2));
1377 } else {
1378 desc = card->txbd_ring[wrdoneidx];
1379 memset(desc, 0, sizeof(*desc));
1380 }
1381 switch (card->dev->device) {
1382 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1383 card->txbd_rdptr++;
1384 break;
1385 case PCIE_DEVICE_ID_MARVELL_88W8897:
1386 case PCIE_DEVICE_ID_MARVELL_88W8997:
1387 card->txbd_rdptr += reg->ring_tx_start_ptr;
1388 break;
1389 }
1390
1391
1392 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs)
1393 card->txbd_rdptr = ((card->txbd_rdptr &
1394 reg->tx_rollover_ind) ^
1395 reg->tx_rollover_ind);
1396 }
1397
1398 if (unmap_count)
1399 adapter->data_sent = false;
1400
1401 if (card->txbd_flush) {
1402 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr))
1403 card->txbd_flush = 0;
1404 else
1405 mwifiex_clean_pcie_ring_buf(adapter);
1406 }
1407
1408 return 0;
1409 }
1410
1411 /* This function sends data buffer to device. First 4 bytes of payload
1412 * are filled with payload length and payload type. Then this payload
1413 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly.
1414 * Download ready interrupt to FW is deffered if Tx ring is not full and
1415 * additional payload can be accomodated.
1416 * Caller must ensure tx_param parameter to this function is not NULL.
1417 */
1418 static int
mwifiex_pcie_send_data(struct mwifiex_adapter * adapter,struct sk_buff * skb,struct mwifiex_tx_param * tx_param)1419 mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb,
1420 struct mwifiex_tx_param *tx_param)
1421 {
1422 struct pcie_service_card *card = adapter->card;
1423 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1424 u32 wrindx, num_tx_buffs, rx_val;
1425 int ret;
1426 dma_addr_t buf_pa;
1427 struct mwifiex_pcie_buf_desc *desc = NULL;
1428 struct mwifiex_pfu_buf_desc *desc2 = NULL;
1429
1430 if (!(skb->data && skb->len)) {
1431 mwifiex_dbg(adapter, ERROR,
1432 "%s(): invalid parameter <%p, %#x>\n",
1433 __func__, skb->data, skb->len);
1434 return -1;
1435 }
1436
1437 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1438 mwifiex_pm_wakeup_card(adapter);
1439
1440 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr;
1441 mwifiex_dbg(adapter, DATA,
1442 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n",
1443 card->txbd_rdptr, card->txbd_wrptr);
1444 if (mwifiex_pcie_txbd_not_full(card)) {
1445 u8 *payload;
1446
1447 adapter->data_sent = true;
1448 payload = skb->data;
1449 put_unaligned_le16((u16)skb->len, payload + 0);
1450 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2);
1451
1452 if (mwifiex_map_pci_memory(adapter, skb, skb->len,
1453 DMA_TO_DEVICE))
1454 return -1;
1455
1456 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr;
1457 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1458 card->tx_buf_list[wrindx] = skb;
1459 atomic_inc(&adapter->tx_hw_pending);
1460
1461 if (reg->pfu_enabled) {
1462 desc2 = card->txbd_ring[wrindx];
1463 desc2->paddr = buf_pa;
1464 desc2->len = (u16)skb->len;
1465 desc2->frag_len = (u16)skb->len;
1466 desc2->offset = 0;
1467 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1468 MWIFIEX_BD_FLAG_LAST_DESC;
1469 } else {
1470 desc = card->txbd_ring[wrindx];
1471 desc->paddr = buf_pa;
1472 desc->len = (u16)skb->len;
1473 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC |
1474 MWIFIEX_BD_FLAG_LAST_DESC;
1475 }
1476
1477 switch (card->dev->device) {
1478 case PCIE_DEVICE_ID_MARVELL_88W8766P:
1479 card->txbd_wrptr++;
1480 break;
1481 case PCIE_DEVICE_ID_MARVELL_88W8897:
1482 case PCIE_DEVICE_ID_MARVELL_88W8997:
1483 card->txbd_wrptr += reg->ring_tx_start_ptr;
1484 break;
1485 }
1486
1487 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs)
1488 card->txbd_wrptr = ((card->txbd_wrptr &
1489 reg->tx_rollover_ind) ^
1490 reg->tx_rollover_ind);
1491
1492 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask;
1493 /* Write the TX ring write pointer in to reg->tx_wrptr */
1494 if (mwifiex_write_reg(adapter, reg->tx_wrptr,
1495 card->txbd_wrptr | rx_val)) {
1496 mwifiex_dbg(adapter, ERROR,
1497 "SEND DATA: failed to write reg->tx_wrptr\n");
1498 ret = -1;
1499 goto done_unmap;
1500 }
1501
1502 /* The firmware (latest version 15.68.19.p21) of the 88W8897 PCIe+USB card
1503 * seems to crash randomly after setting the TX ring write pointer when
1504 * ASPM powersaving is enabled. A workaround seems to be keeping the bus
1505 * busy by reading a random register afterwards.
1506 */
1507 mwifiex_read_reg(adapter, PCI_VENDOR_ID, &rx_val);
1508
1509 if ((mwifiex_pcie_txbd_not_full(card)) &&
1510 tx_param->next_pkt_len) {
1511 /* have more packets and TxBD still can hold more */
1512 mwifiex_dbg(adapter, DATA,
1513 "SEND DATA: delay dnld-rdy interrupt.\n");
1514 adapter->data_sent = false;
1515 } else {
1516 /* Send the TX ready interrupt */
1517 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1518 CPU_INTR_DNLD_RDY)) {
1519 mwifiex_dbg(adapter, ERROR,
1520 "SEND DATA: failed to assert dnld-rdy interrupt.\n");
1521 ret = -1;
1522 goto done_unmap;
1523 }
1524 }
1525 mwifiex_dbg(adapter, DATA,
1526 "info: SEND DATA: Updated <Rd: %#x, Wr:\t"
1527 "%#x> and sent packet to firmware successfully\n",
1528 card->txbd_rdptr, card->txbd_wrptr);
1529 } else {
1530 mwifiex_dbg(adapter, DATA,
1531 "info: TX Ring full, can't send packets to fw\n");
1532 adapter->data_sent = true;
1533 /* Send the TX ready interrupt */
1534 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1535 CPU_INTR_DNLD_RDY))
1536 mwifiex_dbg(adapter, ERROR,
1537 "SEND DATA: failed to assert door-bell intr\n");
1538 return -EBUSY;
1539 }
1540
1541 return -EINPROGRESS;
1542 done_unmap:
1543 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1544 card->tx_buf_list[wrindx] = NULL;
1545 atomic_dec(&adapter->tx_hw_pending);
1546 if (reg->pfu_enabled)
1547 memset(desc2, 0, sizeof(*desc2));
1548 else
1549 memset(desc, 0, sizeof(*desc));
1550
1551 return ret;
1552 }
1553
1554 /*
1555 * This function handles received buffer ring and
1556 * dispatches packets to upper
1557 */
mwifiex_pcie_process_recv_data(struct mwifiex_adapter * adapter)1558 static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter)
1559 {
1560 struct pcie_service_card *card = adapter->card;
1561 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1562 u32 wrptr, rd_index, tx_val;
1563 dma_addr_t buf_pa;
1564 int ret = 0;
1565 struct sk_buff *skb_tmp = NULL;
1566 struct mwifiex_pcie_buf_desc *desc;
1567 struct mwifiex_pfu_buf_desc *desc2;
1568
1569 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1570 mwifiex_pm_wakeup_card(adapter);
1571
1572 /* Read the RX ring Write pointer set by firmware */
1573 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1574 mwifiex_dbg(adapter, ERROR,
1575 "RECV DATA: failed to read reg->rx_wrptr\n");
1576 ret = -1;
1577 goto done;
1578 }
1579 card->rxbd_wrptr = wrptr;
1580
1581 while (((wrptr & reg->rx_mask) !=
1582 (card->rxbd_rdptr & reg->rx_mask)) ||
1583 ((wrptr & reg->rx_rollover_ind) ==
1584 (card->rxbd_rdptr & reg->rx_rollover_ind))) {
1585 struct sk_buff *skb_data;
1586 u16 rx_len;
1587
1588 rd_index = card->rxbd_rdptr & reg->rx_mask;
1589 skb_data = card->rx_buf_list[rd_index];
1590
1591 /* If skb allocation was failed earlier for Rx packet,
1592 * rx_buf_list[rd_index] would have been left with a NULL.
1593 */
1594 if (!skb_data)
1595 return -ENOMEM;
1596
1597 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE);
1598 card->rx_buf_list[rd_index] = NULL;
1599
1600 /* Get data length from interface header -
1601 * first 2 bytes for len, next 2 bytes is for type
1602 */
1603 rx_len = get_unaligned_le16(skb_data->data);
1604 if (WARN_ON(rx_len <= adapter->intf_hdr_len ||
1605 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) {
1606 mwifiex_dbg(adapter, ERROR,
1607 "Invalid RX len %d, Rd=%#x, Wr=%#x\n",
1608 rx_len, card->rxbd_rdptr, wrptr);
1609 dev_kfree_skb_any(skb_data);
1610 } else {
1611 skb_put(skb_data, rx_len);
1612 mwifiex_dbg(adapter, DATA,
1613 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n",
1614 card->rxbd_rdptr, wrptr, rx_len);
1615 skb_pull(skb_data, adapter->intf_hdr_len);
1616 if (adapter->rx_work_enabled) {
1617 skb_queue_tail(&adapter->rx_data_q, skb_data);
1618 adapter->data_received = true;
1619 atomic_inc(&adapter->rx_pending);
1620 } else {
1621 mwifiex_handle_rx_packet(adapter, skb_data);
1622 }
1623 }
1624
1625 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
1626 GFP_KERNEL);
1627 if (!skb_tmp) {
1628 mwifiex_dbg(adapter, ERROR,
1629 "Unable to allocate skb.\n");
1630 return -ENOMEM;
1631 }
1632
1633 if (mwifiex_map_pci_memory(adapter, skb_tmp,
1634 MWIFIEX_RX_DATA_BUF_SIZE,
1635 DMA_FROM_DEVICE))
1636 return -1;
1637
1638 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp);
1639
1640 mwifiex_dbg(adapter, INFO,
1641 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n",
1642 skb_tmp, rd_index);
1643 card->rx_buf_list[rd_index] = skb_tmp;
1644
1645 if (reg->pfu_enabled) {
1646 desc2 = card->rxbd_ring[rd_index];
1647 desc2->paddr = buf_pa;
1648 desc2->len = skb_tmp->len;
1649 desc2->frag_len = skb_tmp->len;
1650 desc2->offset = 0;
1651 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop;
1652 } else {
1653 desc = card->rxbd_ring[rd_index];
1654 desc->paddr = buf_pa;
1655 desc->len = skb_tmp->len;
1656 desc->flags = 0;
1657 }
1658
1659 if ((++card->rxbd_rdptr & reg->rx_mask) ==
1660 MWIFIEX_MAX_TXRX_BD) {
1661 card->rxbd_rdptr = ((card->rxbd_rdptr &
1662 reg->rx_rollover_ind) ^
1663 reg->rx_rollover_ind);
1664 }
1665 mwifiex_dbg(adapter, DATA,
1666 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n",
1667 card->rxbd_rdptr, wrptr);
1668
1669 tx_val = card->txbd_wrptr & reg->tx_wrap_mask;
1670 /* Write the RX ring read pointer in to reg->rx_rdptr */
1671 if (mwifiex_write_reg(adapter, reg->rx_rdptr,
1672 card->rxbd_rdptr | tx_val)) {
1673 mwifiex_dbg(adapter, DATA,
1674 "RECV DATA: failed to write reg->rx_rdptr\n");
1675 ret = -1;
1676 goto done;
1677 }
1678
1679 /* Read the RX ring Write pointer set by firmware */
1680 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) {
1681 mwifiex_dbg(adapter, ERROR,
1682 "RECV DATA: failed to read reg->rx_wrptr\n");
1683 ret = -1;
1684 goto done;
1685 }
1686 mwifiex_dbg(adapter, DATA,
1687 "info: RECV DATA: Rcvd packet from fw successfully\n");
1688 card->rxbd_wrptr = wrptr;
1689 }
1690
1691 done:
1692 return ret;
1693 }
1694
1695 /*
1696 * This function downloads the boot command to device
1697 */
1698 static int
mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter * adapter,struct sk_buff * skb)1699 mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1700 {
1701 dma_addr_t buf_pa;
1702 struct pcie_service_card *card = adapter->card;
1703 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1704
1705 if (!(skb->data && skb->len)) {
1706 mwifiex_dbg(adapter, ERROR,
1707 "Invalid parameter in %s <%p. len %d>\n",
1708 __func__, skb->data, skb->len);
1709 return -1;
1710 }
1711
1712 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1713 return -1;
1714
1715 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
1716
1717 /* Write the lower 32bits of the physical address to low command
1718 * address scratch register
1719 */
1720 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) {
1721 mwifiex_dbg(adapter, ERROR,
1722 "%s: failed to write download command to boot code.\n",
1723 __func__);
1724 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1725 return -1;
1726 }
1727
1728 /* Write the upper 32bits of the physical address to high command
1729 * address scratch register
1730 */
1731 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1732 (u32)((u64)buf_pa >> 32))) {
1733 mwifiex_dbg(adapter, ERROR,
1734 "%s: failed to write download command to boot code.\n",
1735 __func__);
1736 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1737 return -1;
1738 }
1739
1740 /* Write the command length to cmd_size scratch register */
1741 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) {
1742 mwifiex_dbg(adapter, ERROR,
1743 "%s: failed to write command len to cmd_size scratch reg\n",
1744 __func__);
1745 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1746 return -1;
1747 }
1748
1749 /* Ring the door bell */
1750 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1751 CPU_INTR_DOOR_BELL)) {
1752 mwifiex_dbg(adapter, ERROR,
1753 "%s: failed to assert door-bell intr\n", __func__);
1754 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
1755 return -1;
1756 }
1757
1758 return 0;
1759 }
1760
1761 /* This function init rx port in firmware which in turn enables to receive data
1762 * from device before transmitting any packet.
1763 */
mwifiex_pcie_init_fw_port(struct mwifiex_adapter * adapter)1764 static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter)
1765 {
1766 struct pcie_service_card *card = adapter->card;
1767 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1768 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask;
1769
1770 /* Write the RX ring read pointer in to reg->rx_rdptr */
1771 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr |
1772 tx_wrap)) {
1773 mwifiex_dbg(adapter, ERROR,
1774 "RECV DATA: failed to write reg->rx_rdptr\n");
1775 return -1;
1776 }
1777 return 0;
1778 }
1779
1780 /* This function downloads commands to the device
1781 */
1782 static int
mwifiex_pcie_send_cmd(struct mwifiex_adapter * adapter,struct sk_buff * skb)1783 mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb)
1784 {
1785 struct pcie_service_card *card = adapter->card;
1786 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1787 int ret = 0;
1788 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa;
1789 u8 *payload = (u8 *)skb->data;
1790
1791 if (!(skb->data && skb->len)) {
1792 mwifiex_dbg(adapter, ERROR,
1793 "Invalid parameter in %s <%p, %#x>\n",
1794 __func__, skb->data, skb->len);
1795 return -1;
1796 }
1797
1798 /* Make sure a command response buffer is available */
1799 if (!card->cmdrsp_buf) {
1800 mwifiex_dbg(adapter, ERROR,
1801 "No response buffer available, send command failed\n");
1802 return -EBUSY;
1803 }
1804
1805 if (!mwifiex_pcie_ok_to_access_hw(adapter))
1806 mwifiex_pm_wakeup_card(adapter);
1807
1808 adapter->cmd_sent = true;
1809
1810 put_unaligned_le16((u16)skb->len, &payload[0]);
1811 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]);
1812
1813 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE))
1814 return -1;
1815
1816 card->cmd_buf = skb;
1817 /*
1818 * Need to keep a reference, since core driver might free up this
1819 * buffer before we've unmapped it.
1820 */
1821 skb_get(skb);
1822
1823 /* To send a command, the driver will:
1824 1. Write the 64bit physical address of the data buffer to
1825 cmd response address low + cmd response address high
1826 2. Ring the door bell (i.e. set the door bell interrupt)
1827
1828 In response to door bell interrupt, the firmware will perform
1829 the DMA of the command packet (first header to obtain the total
1830 length and then rest of the command).
1831 */
1832
1833 if (card->cmdrsp_buf) {
1834 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf);
1835 /* Write the lower 32bits of the cmdrsp buffer physical
1836 address */
1837 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo,
1838 (u32)cmdrsp_buf_pa)) {
1839 mwifiex_dbg(adapter, ERROR,
1840 "Failed to write download cmd to boot code.\n");
1841 ret = -1;
1842 goto done;
1843 }
1844 /* Write the upper 32bits of the cmdrsp buffer physical
1845 address */
1846 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi,
1847 (u32)((u64)cmdrsp_buf_pa >> 32))) {
1848 mwifiex_dbg(adapter, ERROR,
1849 "Failed to write download cmd to boot code.\n");
1850 ret = -1;
1851 goto done;
1852 }
1853 }
1854
1855 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf);
1856 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */
1857 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo,
1858 (u32)cmd_buf_pa)) {
1859 mwifiex_dbg(adapter, ERROR,
1860 "Failed to write download cmd to boot code.\n");
1861 ret = -1;
1862 goto done;
1863 }
1864 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */
1865 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi,
1866 (u32)((u64)cmd_buf_pa >> 32))) {
1867 mwifiex_dbg(adapter, ERROR,
1868 "Failed to write download cmd to boot code.\n");
1869 ret = -1;
1870 goto done;
1871 }
1872
1873 /* Write the command length to reg->cmd_size */
1874 if (mwifiex_write_reg(adapter, reg->cmd_size,
1875 card->cmd_buf->len)) {
1876 mwifiex_dbg(adapter, ERROR,
1877 "Failed to write cmd len to reg->cmd_size\n");
1878 ret = -1;
1879 goto done;
1880 }
1881
1882 /* Ring the door bell */
1883 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
1884 CPU_INTR_DOOR_BELL)) {
1885 mwifiex_dbg(adapter, ERROR,
1886 "Failed to assert door-bell intr\n");
1887 ret = -1;
1888 goto done;
1889 }
1890
1891 done:
1892 if (ret)
1893 adapter->cmd_sent = false;
1894
1895 return 0;
1896 }
1897
1898 /*
1899 * This function handles command complete interrupt
1900 */
mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter * adapter)1901 static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
1902 {
1903 struct pcie_service_card *card = adapter->card;
1904 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
1905 struct sk_buff *skb = card->cmdrsp_buf;
1906 int count = 0;
1907 u16 rx_len;
1908
1909 mwifiex_dbg(adapter, CMD,
1910 "info: Rx CMD Response\n");
1911
1912 if (adapter->curr_cmd)
1913 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE);
1914 else
1915 dma_sync_single_for_cpu(&card->dev->dev,
1916 MWIFIEX_SKB_DMA_ADDR(skb),
1917 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE);
1918
1919 /* Unmap the command as a response has been received. */
1920 if (card->cmd_buf) {
1921 mwifiex_unmap_pci_memory(adapter, card->cmd_buf,
1922 DMA_TO_DEVICE);
1923 dev_kfree_skb_any(card->cmd_buf);
1924 card->cmd_buf = NULL;
1925 }
1926
1927 rx_len = get_unaligned_le16(skb->data);
1928 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
1929 skb_trim(skb, rx_len);
1930
1931 if (!adapter->curr_cmd) {
1932 if (adapter->ps_state == PS_STATE_SLEEP_CFM) {
1933 dma_sync_single_for_device(&card->dev->dev,
1934 MWIFIEX_SKB_DMA_ADDR(skb),
1935 MWIFIEX_SLEEP_COOKIE_SIZE,
1936 DMA_FROM_DEVICE);
1937 if (mwifiex_write_reg(adapter,
1938 PCIE_CPU_INT_EVENT,
1939 CPU_INTR_SLEEP_CFM_DONE)) {
1940 mwifiex_dbg(adapter, ERROR,
1941 "Write register failed\n");
1942 return -1;
1943 }
1944 mwifiex_delay_for_sleep_cookie(adapter,
1945 MWIFIEX_MAX_DELAY_COUNT);
1946 mwifiex_unmap_pci_memory(adapter, skb,
1947 DMA_FROM_DEVICE);
1948 skb_pull(skb, adapter->intf_hdr_len);
1949 while (reg->sleep_cookie && (count++ < 10) &&
1950 mwifiex_pcie_ok_to_access_hw(adapter))
1951 usleep_range(50, 60);
1952 mwifiex_pcie_enable_host_int(adapter);
1953 mwifiex_process_sleep_confirm_resp(adapter, skb->data,
1954 skb->len);
1955 } else {
1956 mwifiex_dbg(adapter, ERROR,
1957 "There is no command but got cmdrsp\n");
1958 }
1959 memcpy(adapter->upld_buf, skb->data,
1960 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
1961 skb_push(skb, adapter->intf_hdr_len);
1962 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
1963 DMA_FROM_DEVICE))
1964 return -1;
1965 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) {
1966 skb_pull(skb, adapter->intf_hdr_len);
1967 adapter->curr_cmd->resp_skb = skb;
1968 adapter->cmd_resp_received = true;
1969 /* Take the pointer and set it to CMD node and will
1970 return in the response complete callback */
1971 card->cmdrsp_buf = NULL;
1972
1973 /* Clear the cmd-rsp buffer address in scratch registers. This
1974 will prevent firmware from writing to the same response
1975 buffer again. */
1976 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) {
1977 mwifiex_dbg(adapter, ERROR,
1978 "cmd_done: failed to clear cmd_rsp_addr_lo\n");
1979 return -1;
1980 }
1981 /* Write the upper 32bits of the cmdrsp buffer physical
1982 address */
1983 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) {
1984 mwifiex_dbg(adapter, ERROR,
1985 "cmd_done: failed to clear cmd_rsp_addr_hi\n");
1986 return -1;
1987 }
1988 }
1989
1990 return 0;
1991 }
1992
1993 /*
1994 * Command Response processing complete handler
1995 */
mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)1996 static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter,
1997 struct sk_buff *skb)
1998 {
1999 struct pcie_service_card *card = adapter->card;
2000
2001 if (skb) {
2002 card->cmdrsp_buf = skb;
2003 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len);
2004 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
2005 DMA_FROM_DEVICE))
2006 return -1;
2007 }
2008
2009 return 0;
2010 }
2011
2012 /*
2013 * This function handles firmware event ready interrupt
2014 */
mwifiex_pcie_process_event_ready(struct mwifiex_adapter * adapter)2015 static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
2016 {
2017 struct pcie_service_card *card = adapter->card;
2018 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2019 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2020 u32 wrptr, event;
2021 struct mwifiex_evt_buf_desc *desc;
2022
2023 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2024 mwifiex_pm_wakeup_card(adapter);
2025
2026 if (adapter->event_received) {
2027 mwifiex_dbg(adapter, EVENT,
2028 "info: Event being processed,\t"
2029 "do not process this interrupt just yet\n");
2030 return 0;
2031 }
2032
2033 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2034 mwifiex_dbg(adapter, ERROR,
2035 "info: Invalid read pointer...\n");
2036 return -1;
2037 }
2038
2039 /* Read the event ring write pointer set by firmware */
2040 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2041 mwifiex_dbg(adapter, ERROR,
2042 "EventReady: failed to read reg->evt_wrptr\n");
2043 return -1;
2044 }
2045
2046 mwifiex_dbg(adapter, EVENT,
2047 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>",
2048 card->evtbd_rdptr, wrptr);
2049 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr
2050 & MWIFIEX_EVTBD_MASK)) ||
2051 ((wrptr & reg->evt_rollover_ind) ==
2052 (card->evtbd_rdptr & reg->evt_rollover_ind))) {
2053 struct sk_buff *skb_cmd;
2054 __le16 data_len = 0;
2055 u16 evt_len;
2056
2057 mwifiex_dbg(adapter, INFO,
2058 "info: Read Index: %d\n", rdptr);
2059 skb_cmd = card->evt_buf_list[rdptr];
2060 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE);
2061
2062 /* Take the pointer and set it to event pointer in adapter
2063 and will return back after event handling callback */
2064 card->evt_buf_list[rdptr] = NULL;
2065 desc = card->evtbd_ring[rdptr];
2066 memset(desc, 0, sizeof(*desc));
2067
2068 event = get_unaligned_le32(
2069 &skb_cmd->data[adapter->intf_hdr_len]);
2070 adapter->event_cause = event;
2071 /* The first 4bytes will be the event transfer header
2072 len is 2 bytes followed by type which is 2 bytes */
2073 memcpy(&data_len, skb_cmd->data, sizeof(__le16));
2074 evt_len = le16_to_cpu(data_len);
2075 skb_trim(skb_cmd, evt_len);
2076 skb_pull(skb_cmd, adapter->intf_hdr_len);
2077 mwifiex_dbg(adapter, EVENT,
2078 "info: Event length: %d\n", evt_len);
2079
2080 if (evt_len > MWIFIEX_EVENT_HEADER_LEN &&
2081 evt_len < MAX_EVENT_SIZE)
2082 memcpy(adapter->event_body, skb_cmd->data +
2083 MWIFIEX_EVENT_HEADER_LEN, evt_len -
2084 MWIFIEX_EVENT_HEADER_LEN);
2085
2086 adapter->event_received = true;
2087 adapter->event_skb = skb_cmd;
2088
2089 /* Do not update the event read pointer here, wait till the
2090 buffer is released. This is just to make things simpler,
2091 we need to find a better method of managing these buffers.
2092 */
2093 } else {
2094 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
2095 CPU_INTR_EVENT_DONE)) {
2096 mwifiex_dbg(adapter, ERROR,
2097 "Write register failed\n");
2098 return -1;
2099 }
2100 }
2101
2102 return 0;
2103 }
2104
2105 /*
2106 * Event processing complete handler
2107 */
mwifiex_pcie_event_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)2108 static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter,
2109 struct sk_buff *skb)
2110 {
2111 struct pcie_service_card *card = adapter->card;
2112 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2113 int ret = 0;
2114 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK;
2115 u32 wrptr;
2116 struct mwifiex_evt_buf_desc *desc;
2117
2118 if (!skb)
2119 return 0;
2120
2121 if (rdptr >= MWIFIEX_MAX_EVT_BD) {
2122 mwifiex_dbg(adapter, ERROR,
2123 "event_complete: Invalid rdptr 0x%x\n",
2124 rdptr);
2125 return -EINVAL;
2126 }
2127
2128 /* Read the event ring write pointer set by firmware */
2129 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) {
2130 mwifiex_dbg(adapter, ERROR,
2131 "event_complete: failed to read reg->evt_wrptr\n");
2132 return -1;
2133 }
2134
2135 if (!card->evt_buf_list[rdptr]) {
2136 skb_push(skb, adapter->intf_hdr_len);
2137 skb_put(skb, MAX_EVENT_SIZE - skb->len);
2138 if (mwifiex_map_pci_memory(adapter, skb,
2139 MAX_EVENT_SIZE,
2140 DMA_FROM_DEVICE))
2141 return -1;
2142 card->evt_buf_list[rdptr] = skb;
2143 desc = card->evtbd_ring[rdptr];
2144 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb);
2145 desc->len = (u16)skb->len;
2146 desc->flags = 0;
2147 skb = NULL;
2148 } else {
2149 mwifiex_dbg(adapter, ERROR,
2150 "info: ERROR: buf still valid at index %d, <%p, %p>\n",
2151 rdptr, card->evt_buf_list[rdptr], skb);
2152 }
2153
2154 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) {
2155 card->evtbd_rdptr = ((card->evtbd_rdptr &
2156 reg->evt_rollover_ind) ^
2157 reg->evt_rollover_ind);
2158 }
2159
2160 mwifiex_dbg(adapter, EVENT,
2161 "info: Updated <Rd: 0x%x, Wr: 0x%x>",
2162 card->evtbd_rdptr, wrptr);
2163
2164 /* Write the event ring read pointer in to reg->evt_rdptr */
2165 if (mwifiex_write_reg(adapter, reg->evt_rdptr,
2166 card->evtbd_rdptr)) {
2167 mwifiex_dbg(adapter, ERROR,
2168 "event_complete: failed to read reg->evt_rdptr\n");
2169 return -1;
2170 }
2171
2172 mwifiex_dbg(adapter, EVENT,
2173 "info: Check Events Again\n");
2174 ret = mwifiex_pcie_process_event_ready(adapter);
2175
2176 return ret;
2177 }
2178
2179 /* Combo firmware image is a combination of
2180 * (1) combo crc heaer, start with CMD5
2181 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1.
2182 * (3) wifi image.
2183 *
2184 * This function bypass the header and bluetooth part, return
2185 * the offset of tail wifi-only part. If the image is already wifi-only,
2186 * that is start with CMD1, return 0.
2187 */
2188
mwifiex_extract_wifi_fw(struct mwifiex_adapter * adapter,const void * firmware,u32 firmware_len)2189 static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter,
2190 const void *firmware, u32 firmware_len) {
2191 const struct mwifiex_fw_data *fwdata;
2192 u32 offset = 0, data_len, dnld_cmd;
2193 int ret = 0;
2194 bool cmd7_before = false, first_cmd = false;
2195
2196 while (1) {
2197 /* Check for integer and buffer overflow */
2198 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) ||
2199 offset + sizeof(fwdata->header) >= firmware_len) {
2200 mwifiex_dbg(adapter, ERROR,
2201 "extract wifi-only fw failure!\n");
2202 ret = -1;
2203 goto done;
2204 }
2205
2206 fwdata = firmware + offset;
2207 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd);
2208 data_len = le32_to_cpu(fwdata->header.data_length);
2209
2210 /* Skip past header */
2211 offset += sizeof(fwdata->header);
2212
2213 switch (dnld_cmd) {
2214 case MWIFIEX_FW_DNLD_CMD_1:
2215 if (offset + data_len < data_len) {
2216 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2217 ret = -1;
2218 goto done;
2219 }
2220
2221 /* Image start with cmd1, already wifi-only firmware */
2222 if (!first_cmd) {
2223 mwifiex_dbg(adapter, MSG,
2224 "input wifi-only firmware\n");
2225 return 0;
2226 }
2227
2228 if (!cmd7_before) {
2229 mwifiex_dbg(adapter, ERROR,
2230 "no cmd7 before cmd1!\n");
2231 ret = -1;
2232 goto done;
2233 }
2234 offset += data_len;
2235 break;
2236 case MWIFIEX_FW_DNLD_CMD_5:
2237 first_cmd = true;
2238 /* Check for integer overflow */
2239 if (offset + data_len < data_len) {
2240 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2241 ret = -1;
2242 goto done;
2243 }
2244 offset += data_len;
2245 break;
2246 case MWIFIEX_FW_DNLD_CMD_6:
2247 first_cmd = true;
2248 /* Check for integer overflow */
2249 if (offset + data_len < data_len) {
2250 mwifiex_dbg(adapter, ERROR, "bad FW parse\n");
2251 ret = -1;
2252 goto done;
2253 }
2254 offset += data_len;
2255 if (offset >= firmware_len) {
2256 mwifiex_dbg(adapter, ERROR,
2257 "extract wifi-only fw failure!\n");
2258 ret = -1;
2259 } else {
2260 ret = offset;
2261 }
2262 goto done;
2263 case MWIFIEX_FW_DNLD_CMD_7:
2264 first_cmd = true;
2265 cmd7_before = true;
2266 break;
2267 default:
2268 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n",
2269 dnld_cmd);
2270 ret = -1;
2271 goto done;
2272 }
2273 }
2274
2275 done:
2276 return ret;
2277 }
2278
2279 /*
2280 * This function downloads the firmware to the card.
2281 *
2282 * Firmware is downloaded to the card in blocks. Every block download
2283 * is tested for CRC errors, and retried a number of times before
2284 * returning failure.
2285 */
mwifiex_prog_fw_w_helper(struct mwifiex_adapter * adapter,struct mwifiex_fw_image * fw)2286 static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter,
2287 struct mwifiex_fw_image *fw)
2288 {
2289 int ret;
2290 u8 *firmware = fw->fw_buf;
2291 u32 firmware_len = fw->fw_len;
2292 u32 offset = 0;
2293 struct sk_buff *skb;
2294 u32 txlen, tx_blocks = 0, tries, len, val;
2295 u32 block_retry_cnt = 0;
2296 struct pcie_service_card *card = adapter->card;
2297 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2298
2299 if (!firmware || !firmware_len) {
2300 mwifiex_dbg(adapter, ERROR,
2301 "No firmware image found! Terminating download\n");
2302 return -1;
2303 }
2304
2305 mwifiex_dbg(adapter, INFO,
2306 "info: Downloading FW image (%d bytes)\n",
2307 firmware_len);
2308
2309 if (mwifiex_pcie_disable_host_int(adapter)) {
2310 mwifiex_dbg(adapter, ERROR,
2311 "%s: Disabling interrupts failed.\n", __func__);
2312 return -1;
2313 }
2314
2315 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE);
2316 if (!skb) {
2317 ret = -ENOMEM;
2318 goto done;
2319 }
2320
2321 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val);
2322 if (ret) {
2323 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n");
2324 goto done;
2325 }
2326
2327 /* PCIE FLR case: extract wifi part from combo firmware*/
2328 if (val == MWIFIEX_PCIE_FLR_HAPPENS) {
2329 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len);
2330 if (ret < 0) {
2331 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n");
2332 goto done;
2333 }
2334 offset = ret;
2335 mwifiex_dbg(adapter, MSG,
2336 "info: dnld wifi firmware from %d bytes\n", offset);
2337 }
2338
2339 /* Perform firmware data transfer */
2340 do {
2341 u32 ireg_intr = 0;
2342
2343 /* More data? */
2344 if (offset >= firmware_len)
2345 break;
2346
2347 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2348 ret = mwifiex_read_reg(adapter, reg->cmd_size,
2349 &len);
2350 if (ret) {
2351 mwifiex_dbg(adapter, FATAL,
2352 "Failed reading len from boot code\n");
2353 goto done;
2354 }
2355 if (len)
2356 break;
2357 usleep_range(10, 20);
2358 }
2359
2360 if (!len) {
2361 break;
2362 } else if (len > MWIFIEX_UPLD_SIZE) {
2363 mwifiex_dbg(adapter, ERROR,
2364 "FW download failure @ %d, invalid length %d\n",
2365 offset, len);
2366 ret = -1;
2367 goto done;
2368 }
2369
2370 txlen = len;
2371
2372 if (len & BIT(0)) {
2373 block_retry_cnt++;
2374 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) {
2375 mwifiex_dbg(adapter, ERROR,
2376 "FW download failure @ %d, over max\t"
2377 "retry count\n", offset);
2378 ret = -1;
2379 goto done;
2380 }
2381 mwifiex_dbg(adapter, ERROR,
2382 "FW CRC error indicated by the\t"
2383 "helper: len = 0x%04X, txlen = %d\n",
2384 len, txlen);
2385 len &= ~BIT(0);
2386 /* Setting this to 0 to resend from same offset */
2387 txlen = 0;
2388 } else {
2389 block_retry_cnt = 0;
2390 /* Set blocksize to transfer - checking for
2391 last block */
2392 if (firmware_len - offset < txlen)
2393 txlen = firmware_len - offset;
2394
2395 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) /
2396 card->pcie.blksz_fw_dl;
2397
2398 /* Copy payload to buffer */
2399 memmove(skb->data, &firmware[offset], txlen);
2400 }
2401
2402 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len);
2403 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl);
2404
2405 /* Send the boot command to device */
2406 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) {
2407 mwifiex_dbg(adapter, ERROR,
2408 "Failed to send firmware download command\n");
2409 ret = -1;
2410 goto done;
2411 }
2412
2413 /* Wait for the command done interrupt */
2414 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2415 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS,
2416 &ireg_intr)) {
2417 mwifiex_dbg(adapter, ERROR,
2418 "%s: Failed to read\t"
2419 "interrupt status during fw dnld.\n",
2420 __func__);
2421 mwifiex_unmap_pci_memory(adapter, skb,
2422 DMA_TO_DEVICE);
2423 ret = -1;
2424 goto done;
2425 }
2426 if (!(ireg_intr & CPU_INTR_DOOR_BELL))
2427 break;
2428 usleep_range(10, 20);
2429 }
2430 if (ireg_intr & CPU_INTR_DOOR_BELL) {
2431 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n",
2432 __func__);
2433 mwifiex_unmap_pci_memory(adapter, skb,
2434 DMA_TO_DEVICE);
2435 ret = -1;
2436 goto done;
2437 }
2438
2439 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE);
2440
2441 offset += txlen;
2442 } while (true);
2443
2444 mwifiex_dbg(adapter, MSG,
2445 "info: FW download over, size %d bytes\n", offset);
2446
2447 ret = 0;
2448
2449 done:
2450 dev_kfree_skb_any(skb);
2451 return ret;
2452 }
2453
2454 /*
2455 * This function checks the firmware status in card.
2456 */
2457 static int
mwifiex_check_fw_status(struct mwifiex_adapter * adapter,u32 poll_num)2458 mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num)
2459 {
2460 int ret = 0;
2461 u32 firmware_stat;
2462 struct pcie_service_card *card = adapter->card;
2463 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2464 u32 tries;
2465
2466 /* Mask spurios interrupts */
2467 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK,
2468 HOST_INTR_MASK)) {
2469 mwifiex_dbg(adapter, ERROR,
2470 "Write register failed\n");
2471 return -1;
2472 }
2473
2474 mwifiex_dbg(adapter, INFO,
2475 "Setting driver ready signature\n");
2476 if (mwifiex_write_reg(adapter, reg->drv_rdy,
2477 FIRMWARE_READY_PCIE)) {
2478 mwifiex_dbg(adapter, ERROR,
2479 "Failed to write driver ready signature\n");
2480 return -1;
2481 }
2482
2483 /* Wait for firmware initialization event */
2484 for (tries = 0; tries < poll_num; tries++) {
2485 if (mwifiex_read_reg(adapter, reg->fw_status,
2486 &firmware_stat))
2487 ret = -1;
2488 else
2489 ret = 0;
2490
2491 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>",
2492 tries, ret, firmware_stat);
2493
2494 if (ret)
2495 continue;
2496 if (firmware_stat == FIRMWARE_READY_PCIE) {
2497 ret = 0;
2498 break;
2499 } else {
2500 msleep(100);
2501 ret = -1;
2502 }
2503 }
2504
2505 return ret;
2506 }
2507
2508 /* This function checks if WLAN is the winner.
2509 */
2510 static int
mwifiex_check_winner_status(struct mwifiex_adapter * adapter)2511 mwifiex_check_winner_status(struct mwifiex_adapter *adapter)
2512 {
2513 u32 winner = 0;
2514 int ret = 0;
2515 struct pcie_service_card *card = adapter->card;
2516 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2517
2518 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) {
2519 ret = -1;
2520 } else if (!winner) {
2521 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n");
2522 adapter->winner = 1;
2523 } else {
2524 mwifiex_dbg(adapter, ERROR,
2525 "PCI-E is not the winner <%#x>", winner);
2526 }
2527
2528 return ret;
2529 }
2530
2531 /*
2532 * This function reads the interrupt status from card.
2533 */
mwifiex_interrupt_status(struct mwifiex_adapter * adapter,int msg_id)2534 static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter,
2535 int msg_id)
2536 {
2537 u32 pcie_ireg;
2538 unsigned long flags;
2539 struct pcie_service_card *card = adapter->card;
2540
2541 if (card->msi_enable) {
2542 spin_lock_irqsave(&adapter->int_lock, flags);
2543 adapter->int_status = 1;
2544 spin_unlock_irqrestore(&adapter->int_lock, flags);
2545 return;
2546 }
2547
2548 if (!mwifiex_pcie_ok_to_access_hw(adapter))
2549 return;
2550
2551 if (card->msix_enable && msg_id >= 0) {
2552 pcie_ireg = BIT(msg_id);
2553 } else {
2554 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2555 &pcie_ireg)) {
2556 mwifiex_dbg(adapter, ERROR, "Read register failed\n");
2557 return;
2558 }
2559
2560 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg)
2561 return;
2562
2563
2564 mwifiex_pcie_disable_host_int(adapter);
2565
2566 /* Clear the pending interrupts */
2567 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS,
2568 ~pcie_ireg)) {
2569 mwifiex_dbg(adapter, ERROR,
2570 "Write register failed\n");
2571 return;
2572 }
2573 }
2574
2575 if (!adapter->pps_uapsd_mode &&
2576 adapter->ps_state == PS_STATE_SLEEP &&
2577 mwifiex_pcie_ok_to_access_hw(adapter)) {
2578 /* Potentially for PCIe we could get other
2579 * interrupts like shared. Don't change power
2580 * state until cookie is set
2581 */
2582 adapter->ps_state = PS_STATE_AWAKE;
2583 adapter->pm_wakeup_fw_try = false;
2584 del_timer(&adapter->wakeup_timer);
2585 }
2586
2587 spin_lock_irqsave(&adapter->int_lock, flags);
2588 adapter->int_status |= pcie_ireg;
2589 spin_unlock_irqrestore(&adapter->int_lock, flags);
2590 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg);
2591 }
2592
2593 /*
2594 * Interrupt handler for PCIe root port
2595 *
2596 * This function reads the interrupt status from firmware and assigns
2597 * the main process in workqueue which will handle the interrupt.
2598 */
mwifiex_pcie_interrupt(int irq,void * context)2599 static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context)
2600 {
2601 struct mwifiex_msix_context *ctx = context;
2602 struct pci_dev *pdev = ctx->dev;
2603 struct pcie_service_card *card;
2604 struct mwifiex_adapter *adapter;
2605
2606 card = pci_get_drvdata(pdev);
2607
2608 if (!card->adapter) {
2609 pr_err("info: %s: card=%p adapter=%p\n", __func__, card,
2610 card ? card->adapter : NULL);
2611 goto exit;
2612 }
2613 adapter = card->adapter;
2614
2615 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags))
2616 goto exit;
2617
2618 if (card->msix_enable)
2619 mwifiex_interrupt_status(adapter, ctx->msg_id);
2620 else
2621 mwifiex_interrupt_status(adapter, -1);
2622
2623 mwifiex_queue_main_work(adapter);
2624
2625 exit:
2626 return IRQ_HANDLED;
2627 }
2628
2629 /*
2630 * This function checks the current interrupt status.
2631 *
2632 * The following interrupts are checked and handled by this function -
2633 * - Data sent
2634 * - Command sent
2635 * - Command received
2636 * - Packets received
2637 * - Events received
2638 *
2639 * In case of Rx packets received, the packets are uploaded from card to
2640 * host and processed accordingly.
2641 */
mwifiex_process_int_status(struct mwifiex_adapter * adapter)2642 static int mwifiex_process_int_status(struct mwifiex_adapter *adapter)
2643 {
2644 int ret;
2645 u32 pcie_ireg = 0;
2646 unsigned long flags;
2647 struct pcie_service_card *card = adapter->card;
2648
2649 spin_lock_irqsave(&adapter->int_lock, flags);
2650 if (!card->msi_enable) {
2651 /* Clear out unused interrupts */
2652 pcie_ireg = adapter->int_status;
2653 }
2654 adapter->int_status = 0;
2655 spin_unlock_irqrestore(&adapter->int_lock, flags);
2656
2657 if (card->msi_enable) {
2658 if (mwifiex_pcie_ok_to_access_hw(adapter)) {
2659 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS,
2660 &pcie_ireg)) {
2661 mwifiex_dbg(adapter, ERROR,
2662 "Read register failed\n");
2663 return -1;
2664 }
2665
2666 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) {
2667 if (mwifiex_write_reg(adapter,
2668 PCIE_HOST_INT_STATUS,
2669 ~pcie_ireg)) {
2670 mwifiex_dbg(adapter, ERROR,
2671 "Write register failed\n");
2672 return -1;
2673 }
2674 if (!adapter->pps_uapsd_mode &&
2675 adapter->ps_state == PS_STATE_SLEEP) {
2676 adapter->ps_state = PS_STATE_AWAKE;
2677 adapter->pm_wakeup_fw_try = false;
2678 del_timer(&adapter->wakeup_timer);
2679 }
2680 }
2681 }
2682 }
2683
2684 if (pcie_ireg & HOST_INTR_DNLD_DONE) {
2685 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n");
2686 ret = mwifiex_pcie_send_data_complete(adapter);
2687 if (ret)
2688 return ret;
2689 }
2690 if (pcie_ireg & HOST_INTR_UPLD_RDY) {
2691 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n");
2692 ret = mwifiex_pcie_process_recv_data(adapter);
2693 if (ret)
2694 return ret;
2695 }
2696 if (pcie_ireg & HOST_INTR_EVENT_RDY) {
2697 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n");
2698 ret = mwifiex_pcie_process_event_ready(adapter);
2699 if (ret)
2700 return ret;
2701 }
2702 if (pcie_ireg & HOST_INTR_CMD_DONE) {
2703 if (adapter->cmd_sent) {
2704 mwifiex_dbg(adapter, INTR,
2705 "info: CMD sent Interrupt\n");
2706 adapter->cmd_sent = false;
2707 }
2708 /* Handle command response */
2709 ret = mwifiex_pcie_process_cmd_complete(adapter);
2710 if (ret)
2711 return ret;
2712 }
2713
2714 mwifiex_dbg(adapter, INTR,
2715 "info: cmd_sent=%d data_sent=%d\n",
2716 adapter->cmd_sent, adapter->data_sent);
2717 if (!card->msi_enable && !card->msix_enable &&
2718 adapter->ps_state != PS_STATE_SLEEP)
2719 mwifiex_pcie_enable_host_int(adapter);
2720
2721 return 0;
2722 }
2723
2724 /*
2725 * This function downloads data from driver to card.
2726 *
2727 * Both commands and data packets are transferred to the card by this
2728 * function.
2729 *
2730 * This function adds the PCIE specific header to the front of the buffer
2731 * before transferring. The header contains the length of the packet and
2732 * the type. The firmware handles the packets based upon this set type.
2733 */
mwifiex_pcie_host_to_card(struct mwifiex_adapter * adapter,u8 type,struct sk_buff * skb,struct mwifiex_tx_param * tx_param)2734 static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type,
2735 struct sk_buff *skb,
2736 struct mwifiex_tx_param *tx_param)
2737 {
2738 if (!skb) {
2739 mwifiex_dbg(adapter, ERROR,
2740 "Passed NULL skb to %s\n", __func__);
2741 return -1;
2742 }
2743
2744 if (type == MWIFIEX_TYPE_DATA)
2745 return mwifiex_pcie_send_data(adapter, skb, tx_param);
2746 else if (type == MWIFIEX_TYPE_CMD)
2747 return mwifiex_pcie_send_cmd(adapter, skb);
2748
2749 return 0;
2750 }
2751
2752 /* Function to dump PCIE scratch registers in case of FW crash
2753 */
2754 static int
mwifiex_pcie_reg_dump(struct mwifiex_adapter * adapter,char * drv_buf)2755 mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf)
2756 {
2757 char *p = drv_buf;
2758 char buf[256], *ptr;
2759 int i;
2760 u32 value;
2761 struct pcie_service_card *card = adapter->card;
2762 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2763 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG,
2764 PCIE_SCRATCH_14_REG,
2765 PCIE_SCRATCH_15_REG};
2766
2767 if (!p)
2768 return 0;
2769
2770 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n");
2771
2772 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) {
2773 mwifiex_dbg(adapter, ERROR, "failed to read firmware status");
2774 return 0;
2775 }
2776
2777 ptr = buf;
2778 mwifiex_dbg(adapter, MSG, "pcie scratch register:");
2779 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) {
2780 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value);
2781 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n",
2782 pcie_scratch_reg[i], value);
2783 }
2784
2785 mwifiex_dbg(adapter, MSG, "%s\n", buf);
2786 p += sprintf(p, "%s\n", buf);
2787
2788 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n");
2789
2790 return p - drv_buf;
2791 }
2792
2793 /* This function read/write firmware */
2794 static enum rdwr_status
mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter * adapter,u8 doneflag)2795 mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag)
2796 {
2797 int ret, tries;
2798 u8 ctrl_data;
2799 u32 fw_status;
2800 struct pcie_service_card *card = adapter->card;
2801 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
2802
2803 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status))
2804 return RDWR_STATUS_FAILURE;
2805
2806 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2807 reg->fw_dump_host_ready);
2808 if (ret) {
2809 mwifiex_dbg(adapter, ERROR,
2810 "PCIE write err\n");
2811 return RDWR_STATUS_FAILURE;
2812 }
2813
2814 for (tries = 0; tries < MAX_POLL_TRIES; tries++) {
2815 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data);
2816 if (ctrl_data == FW_DUMP_DONE)
2817 return RDWR_STATUS_SUCCESS;
2818 if (doneflag && ctrl_data == doneflag)
2819 return RDWR_STATUS_DONE;
2820 if (ctrl_data != reg->fw_dump_host_ready) {
2821 mwifiex_dbg(adapter, WARN,
2822 "The ctrl reg was changed, re-try again!\n");
2823 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl,
2824 reg->fw_dump_host_ready);
2825 if (ret) {
2826 mwifiex_dbg(adapter, ERROR,
2827 "PCIE write err\n");
2828 return RDWR_STATUS_FAILURE;
2829 }
2830 }
2831 usleep_range(100, 200);
2832 }
2833
2834 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n");
2835 return RDWR_STATUS_FAILURE;
2836 }
2837
2838 /* This function dump firmware memory to file */
mwifiex_pcie_fw_dump(struct mwifiex_adapter * adapter)2839 static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter)
2840 {
2841 struct pcie_service_card *card = adapter->card;
2842 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg;
2843 unsigned int reg, reg_start, reg_end;
2844 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num;
2845 u8 idx, i, read_reg, doneflag = 0;
2846 enum rdwr_status stat;
2847 u32 memory_size;
2848 int ret;
2849
2850 if (!card->pcie.can_dump_fw)
2851 return;
2852
2853 for (idx = 0; idx < adapter->num_mem_types; idx++) {
2854 struct memory_type_mapping *entry =
2855 &adapter->mem_type_mapping_tbl[idx];
2856
2857 if (entry->mem_ptr) {
2858 vfree(entry->mem_ptr);
2859 entry->mem_ptr = NULL;
2860 }
2861 entry->mem_size = 0;
2862 }
2863
2864 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n");
2865
2866 /* Read the number of the memories which will dump */
2867 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2868 if (stat == RDWR_STATUS_FAILURE)
2869 return;
2870
2871 reg = creg->fw_dump_start;
2872 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num);
2873
2874 /* W8997 chipset firmware dump will be restore in single region*/
2875 if (fw_dump_num == 0)
2876 dump_num = 1;
2877 else
2878 dump_num = fw_dump_num;
2879
2880 /* Read the length of every memory which will dump */
2881 for (idx = 0; idx < dump_num; idx++) {
2882 struct memory_type_mapping *entry =
2883 &adapter->mem_type_mapping_tbl[idx];
2884 memory_size = 0;
2885 if (fw_dump_num != 0) {
2886 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2887 if (stat == RDWR_STATUS_FAILURE)
2888 return;
2889
2890 reg = creg->fw_dump_start;
2891 for (i = 0; i < 4; i++) {
2892 mwifiex_read_reg_byte(adapter, reg, &read_reg);
2893 memory_size |= (read_reg << (i * 8));
2894 reg++;
2895 }
2896 } else {
2897 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE;
2898 }
2899
2900 if (memory_size == 0) {
2901 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n");
2902 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl,
2903 creg->fw_dump_read_done);
2904 if (ret) {
2905 mwifiex_dbg(adapter, ERROR, "PCIE write err\n");
2906 return;
2907 }
2908 break;
2909 }
2910
2911 mwifiex_dbg(adapter, DUMP,
2912 "%s_SIZE=0x%x\n", entry->mem_name, memory_size);
2913 entry->mem_ptr = vmalloc(memory_size + 1);
2914 entry->mem_size = memory_size;
2915 if (!entry->mem_ptr) {
2916 mwifiex_dbg(adapter, ERROR,
2917 "Vmalloc %s failed\n", entry->mem_name);
2918 return;
2919 }
2920 dbg_ptr = entry->mem_ptr;
2921 end_ptr = dbg_ptr + memory_size;
2922
2923 doneflag = entry->done_flag;
2924 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n",
2925 entry->mem_name);
2926
2927 do {
2928 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag);
2929 if (RDWR_STATUS_FAILURE == stat)
2930 return;
2931
2932 reg_start = creg->fw_dump_start;
2933 reg_end = creg->fw_dump_end;
2934 for (reg = reg_start; reg <= reg_end; reg++) {
2935 mwifiex_read_reg_byte(adapter, reg, dbg_ptr);
2936 if (dbg_ptr < end_ptr) {
2937 dbg_ptr++;
2938 continue;
2939 }
2940 mwifiex_dbg(adapter, ERROR,
2941 "pre-allocated buf not enough\n");
2942 tmp_ptr =
2943 vzalloc(memory_size + MWIFIEX_SIZE_4K);
2944 if (!tmp_ptr)
2945 return;
2946 memcpy(tmp_ptr, entry->mem_ptr, memory_size);
2947 vfree(entry->mem_ptr);
2948 entry->mem_ptr = tmp_ptr;
2949 tmp_ptr = NULL;
2950 dbg_ptr = entry->mem_ptr + memory_size;
2951 memory_size += MWIFIEX_SIZE_4K;
2952 end_ptr = entry->mem_ptr + memory_size;
2953 }
2954
2955 if (stat != RDWR_STATUS_DONE)
2956 continue;
2957
2958 mwifiex_dbg(adapter, DUMP,
2959 "%s done: size=0x%tx\n",
2960 entry->mem_name, dbg_ptr - entry->mem_ptr);
2961 break;
2962 } while (true);
2963 }
2964 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n");
2965 }
2966
mwifiex_pcie_device_dump_work(struct mwifiex_adapter * adapter)2967 static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter)
2968 {
2969 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE);
2970 if (!adapter->devdump_data) {
2971 mwifiex_dbg(adapter, ERROR,
2972 "vzalloc devdump data failure!\n");
2973 return;
2974 }
2975
2976 mwifiex_drv_info_dump(adapter);
2977 mwifiex_pcie_fw_dump(adapter);
2978 mwifiex_prepare_fw_dump_info(adapter);
2979 mwifiex_upload_device_dump(adapter);
2980 }
2981
mwifiex_pcie_card_reset_work(struct mwifiex_adapter * adapter)2982 static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter)
2983 {
2984 struct pcie_service_card *card = adapter->card;
2985
2986 /* We can't afford to wait here; remove() might be waiting on us. If we
2987 * can't grab the device lock, maybe we'll get another chance later.
2988 */
2989 pci_try_reset_function(card->dev);
2990 }
2991
mwifiex_pcie_work(struct work_struct * work)2992 static void mwifiex_pcie_work(struct work_struct *work)
2993 {
2994 struct pcie_service_card *card =
2995 container_of(work, struct pcie_service_card, work);
2996
2997 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
2998 &card->work_flags))
2999 mwifiex_pcie_device_dump_work(card->adapter);
3000 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET,
3001 &card->work_flags))
3002 mwifiex_pcie_card_reset_work(card->adapter);
3003 }
3004
3005 /* This function dumps FW information */
mwifiex_pcie_device_dump(struct mwifiex_adapter * adapter)3006 static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter)
3007 {
3008 struct pcie_service_card *card = adapter->card;
3009
3010 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
3011 &card->work_flags))
3012 schedule_work(&card->work);
3013 }
3014
mwifiex_pcie_card_reset(struct mwifiex_adapter * adapter)3015 static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter)
3016 {
3017 struct pcie_service_card *card = adapter->card;
3018
3019 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags))
3020 schedule_work(&card->work);
3021 }
3022
mwifiex_pcie_alloc_buffers(struct mwifiex_adapter * adapter)3023 static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter)
3024 {
3025 struct pcie_service_card *card = adapter->card;
3026 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3027 int ret;
3028
3029 card->cmdrsp_buf = NULL;
3030 ret = mwifiex_pcie_create_txbd_ring(adapter);
3031 if (ret) {
3032 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n");
3033 goto err_cre_txbd;
3034 }
3035
3036 ret = mwifiex_pcie_create_rxbd_ring(adapter);
3037 if (ret) {
3038 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n");
3039 goto err_cre_rxbd;
3040 }
3041
3042 ret = mwifiex_pcie_create_evtbd_ring(adapter);
3043 if (ret) {
3044 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n");
3045 goto err_cre_evtbd;
3046 }
3047
3048 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter);
3049 if (ret) {
3050 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n");
3051 goto err_alloc_cmdbuf;
3052 }
3053
3054 if (reg->sleep_cookie) {
3055 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter);
3056 if (ret) {
3057 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n");
3058 goto err_alloc_cookie;
3059 }
3060 } else {
3061 card->sleep_cookie_vbase = NULL;
3062 }
3063
3064 return 0;
3065
3066 err_alloc_cookie:
3067 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3068 err_alloc_cmdbuf:
3069 mwifiex_pcie_delete_evtbd_ring(adapter);
3070 err_cre_evtbd:
3071 mwifiex_pcie_delete_rxbd_ring(adapter);
3072 err_cre_rxbd:
3073 mwifiex_pcie_delete_txbd_ring(adapter);
3074 err_cre_txbd:
3075 return ret;
3076 }
3077
mwifiex_pcie_free_buffers(struct mwifiex_adapter * adapter)3078 static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter)
3079 {
3080 struct pcie_service_card *card = adapter->card;
3081 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3082
3083 if (reg->sleep_cookie)
3084 mwifiex_pcie_delete_sleep_cookie_buf(adapter);
3085
3086 mwifiex_pcie_delete_cmdrsp_buf(adapter);
3087 mwifiex_pcie_delete_evtbd_ring(adapter);
3088 mwifiex_pcie_delete_rxbd_ring(adapter);
3089 mwifiex_pcie_delete_txbd_ring(adapter);
3090 }
3091
3092 /*
3093 * This function initializes the PCI-E host memory space, WCB rings, etc.
3094 */
mwifiex_init_pcie(struct mwifiex_adapter * adapter)3095 static int mwifiex_init_pcie(struct mwifiex_adapter *adapter)
3096 {
3097 struct pcie_service_card *card = adapter->card;
3098 int ret;
3099 struct pci_dev *pdev = card->dev;
3100
3101 pci_set_drvdata(pdev, card);
3102
3103 ret = pci_enable_device(pdev);
3104 if (ret)
3105 goto err_enable_dev;
3106
3107 pci_set_master(pdev);
3108
3109 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3110 if (ret) {
3111 pr_err("dma_set_mask(32) failed: %d\n", ret);
3112 goto err_set_dma_mask;
3113 }
3114
3115 ret = pci_request_region(pdev, 0, DRV_NAME);
3116 if (ret) {
3117 pr_err("req_reg(0) error\n");
3118 goto err_req_region0;
3119 }
3120 card->pci_mmap = pci_iomap(pdev, 0, 0);
3121 if (!card->pci_mmap) {
3122 pr_err("iomap(0) error\n");
3123 ret = -EIO;
3124 goto err_iomap0;
3125 }
3126 ret = pci_request_region(pdev, 2, DRV_NAME);
3127 if (ret) {
3128 pr_err("req_reg(2) error\n");
3129 goto err_req_region2;
3130 }
3131 card->pci_mmap1 = pci_iomap(pdev, 2, 0);
3132 if (!card->pci_mmap1) {
3133 pr_err("iomap(2) error\n");
3134 ret = -EIO;
3135 goto err_iomap2;
3136 }
3137
3138 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n",
3139 card->pci_mmap, card->pci_mmap1);
3140
3141 ret = mwifiex_pcie_alloc_buffers(adapter);
3142 if (ret)
3143 goto err_alloc_buffers;
3144
3145 if (pdev->device == PCIE_DEVICE_ID_MARVELL_88W8897)
3146 adapter->ignore_btcoex_events = true;
3147
3148 return 0;
3149
3150 err_alloc_buffers:
3151 pci_iounmap(pdev, card->pci_mmap1);
3152 err_iomap2:
3153 pci_release_region(pdev, 2);
3154 err_req_region2:
3155 pci_iounmap(pdev, card->pci_mmap);
3156 err_iomap0:
3157 pci_release_region(pdev, 0);
3158 err_req_region0:
3159 err_set_dma_mask:
3160 pci_disable_device(pdev);
3161 err_enable_dev:
3162 return ret;
3163 }
3164
3165 /*
3166 * This function cleans up the allocated card buffers.
3167 */
mwifiex_cleanup_pcie(struct mwifiex_adapter * adapter)3168 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter)
3169 {
3170 struct pcie_service_card *card = adapter->card;
3171 struct pci_dev *pdev = card->dev;
3172 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3173 int ret;
3174 u32 fw_status;
3175
3176 /* Perform the cancel_work_sync() only when we're not resetting
3177 * the card. It's because that function never returns if we're
3178 * in reset path. If we're here when resetting the card, it means
3179 * that we failed to reset the card (reset failure path).
3180 */
3181 if (!card->pci_reset_ongoing) {
3182 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n");
3183 cancel_work_sync(&card->work);
3184 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n");
3185 } else {
3186 mwifiex_dbg(adapter, MSG,
3187 "skipped cancel_work_sync() because we're in card reset failure path\n");
3188 }
3189
3190 ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
3191 if (fw_status == FIRMWARE_READY_PCIE) {
3192 mwifiex_dbg(adapter, INFO,
3193 "Clearing driver ready signature\n");
3194 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3195 mwifiex_dbg(adapter, ERROR,
3196 "Failed to write driver not-ready signature\n");
3197 }
3198
3199 pci_disable_device(pdev);
3200
3201 pci_iounmap(pdev, card->pci_mmap);
3202 pci_iounmap(pdev, card->pci_mmap1);
3203 pci_release_region(pdev, 2);
3204 pci_release_region(pdev, 0);
3205
3206 mwifiex_pcie_free_buffers(adapter);
3207 }
3208
mwifiex_pcie_request_irq(struct mwifiex_adapter * adapter)3209 static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter)
3210 {
3211 int ret, i, j;
3212 struct pcie_service_card *card = adapter->card;
3213 struct pci_dev *pdev = card->dev;
3214
3215 if (card->pcie.reg->msix_support) {
3216 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3217 card->msix_entries[i].entry = i;
3218 ret = pci_enable_msix_exact(pdev, card->msix_entries,
3219 MWIFIEX_NUM_MSIX_VECTORS);
3220 if (!ret) {
3221 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) {
3222 card->msix_ctx[i].dev = pdev;
3223 card->msix_ctx[i].msg_id = i;
3224
3225 ret = request_irq(card->msix_entries[i].vector,
3226 mwifiex_pcie_interrupt, 0,
3227 "MWIFIEX_PCIE_MSIX",
3228 &card->msix_ctx[i]);
3229 if (ret)
3230 break;
3231 }
3232
3233 if (ret) {
3234 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n",
3235 ret);
3236 for (j = 0; j < i; j++)
3237 free_irq(card->msix_entries[j].vector,
3238 &card->msix_ctx[i]);
3239 pci_disable_msix(pdev);
3240 } else {
3241 mwifiex_dbg(adapter, MSG, "MSIx enabled!");
3242 card->msix_enable = 1;
3243 return 0;
3244 }
3245 }
3246 }
3247
3248 if (pci_enable_msi(pdev) != 0)
3249 pci_disable_msi(pdev);
3250 else
3251 card->msi_enable = 1;
3252
3253 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable);
3254
3255 card->share_irq_ctx.dev = pdev;
3256 card->share_irq_ctx.msg_id = -1;
3257 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED,
3258 "MRVL_PCIE", &card->share_irq_ctx);
3259 if (ret) {
3260 pr_err("request_irq failed: ret=%d\n", ret);
3261 return -1;
3262 }
3263
3264 return 0;
3265 }
3266
3267 /*
3268 * This function gets the firmware name for downloading by revision id
3269 *
3270 * Read revision id register to get revision id
3271 */
mwifiex_pcie_get_fw_name(struct mwifiex_adapter * adapter)3272 static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter)
3273 {
3274 int revision_id = 0;
3275 int version, magic;
3276 struct pcie_service_card *card = adapter->card;
3277
3278 switch (card->dev->device) {
3279 case PCIE_DEVICE_ID_MARVELL_88W8766P:
3280 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME);
3281 break;
3282 case PCIE_DEVICE_ID_MARVELL_88W8897:
3283 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000);
3284 mwifiex_read_reg(adapter, 0x0c58, &revision_id);
3285 revision_id &= 0xff00;
3286 switch (revision_id) {
3287 case PCIE8897_A0:
3288 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME);
3289 break;
3290 case PCIE8897_B0:
3291 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME);
3292 break;
3293 default:
3294 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME);
3295
3296 break;
3297 }
3298 break;
3299 case PCIE_DEVICE_ID_MARVELL_88W8997:
3300 mwifiex_read_reg(adapter, 0x8, &revision_id);
3301 mwifiex_read_reg(adapter, 0x0cd0, &version);
3302 mwifiex_read_reg(adapter, 0x0cd4, &magic);
3303 revision_id &= 0xff;
3304 version &= 0x7;
3305 magic &= 0xff;
3306 if (revision_id == PCIE8997_A1 &&
3307 magic == CHIP_MAGIC_VALUE &&
3308 version == CHIP_VER_PCIEUART)
3309 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4);
3310 else
3311 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4);
3312 break;
3313 default:
3314 break;
3315 }
3316 }
3317
3318 /*
3319 * This function registers the PCIE device.
3320 *
3321 * PCIE IRQ is claimed, block size is set and driver data is initialized.
3322 */
mwifiex_register_dev(struct mwifiex_adapter * adapter)3323 static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
3324 {
3325 struct pcie_service_card *card = adapter->card;
3326
3327 /* save adapter pointer in card */
3328 card->adapter = adapter;
3329
3330 if (mwifiex_pcie_request_irq(adapter))
3331 return -1;
3332
3333 adapter->tx_buf_size = card->pcie.tx_buf_size;
3334 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl;
3335 adapter->num_mem_types = card->pcie.num_mem_types;
3336 adapter->ext_scan = card->pcie.can_ext_scan;
3337 mwifiex_pcie_get_fw_name(adapter);
3338
3339 return 0;
3340 }
3341
3342 /*
3343 * This function unregisters the PCIE device.
3344 *
3345 * The PCIE IRQ is released, the function is disabled and driver
3346 * data is set to null.
3347 */
mwifiex_unregister_dev(struct mwifiex_adapter * adapter)3348 static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter)
3349 {
3350 struct pcie_service_card *card = adapter->card;
3351 struct pci_dev *pdev = card->dev;
3352 int i;
3353
3354 if (card->msix_enable) {
3355 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3356 synchronize_irq(card->msix_entries[i].vector);
3357
3358 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++)
3359 free_irq(card->msix_entries[i].vector,
3360 &card->msix_ctx[i]);
3361
3362 card->msix_enable = 0;
3363 pci_disable_msix(pdev);
3364 } else {
3365 mwifiex_dbg(adapter, INFO,
3366 "%s(): calling free_irq()\n", __func__);
3367 free_irq(card->dev->irq, &card->share_irq_ctx);
3368
3369 if (card->msi_enable)
3370 pci_disable_msi(pdev);
3371 }
3372 card->adapter = NULL;
3373 }
3374
3375 /*
3376 * This function initializes the PCI-E host memory space, WCB rings, etc.,
3377 * similar to mwifiex_init_pcie(), but without resetting PCI-E state.
3378 */
mwifiex_pcie_up_dev(struct mwifiex_adapter * adapter)3379 static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter)
3380 {
3381 struct pcie_service_card *card = adapter->card;
3382 struct pci_dev *pdev = card->dev;
3383
3384 /* tx_buf_size might be changed to 3584 by firmware during
3385 * data transfer, we should reset it to default size.
3386 */
3387 adapter->tx_buf_size = card->pcie.tx_buf_size;
3388
3389 mwifiex_pcie_alloc_buffers(adapter);
3390
3391 pci_set_master(pdev);
3392 }
3393
3394 /* This function cleans up the PCI-E host memory space. */
mwifiex_pcie_down_dev(struct mwifiex_adapter * adapter)3395 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter)
3396 {
3397 struct pcie_service_card *card = adapter->card;
3398 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
3399 struct pci_dev *pdev = card->dev;
3400
3401 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000))
3402 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n");
3403
3404 pci_clear_master(pdev);
3405
3406 adapter->seq_num = 0;
3407
3408 mwifiex_pcie_free_buffers(adapter);
3409 }
3410
3411 static struct mwifiex_if_ops pcie_ops = {
3412 .init_if = mwifiex_init_pcie,
3413 .cleanup_if = mwifiex_cleanup_pcie,
3414 .check_fw_status = mwifiex_check_fw_status,
3415 .check_winner_status = mwifiex_check_winner_status,
3416 .prog_fw = mwifiex_prog_fw_w_helper,
3417 .register_dev = mwifiex_register_dev,
3418 .unregister_dev = mwifiex_unregister_dev,
3419 .enable_int = mwifiex_pcie_enable_host_int,
3420 .disable_int = mwifiex_pcie_disable_host_int_noerr,
3421 .process_int_status = mwifiex_process_int_status,
3422 .host_to_card = mwifiex_pcie_host_to_card,
3423 .wakeup = mwifiex_pm_wakeup_card,
3424 .wakeup_complete = mwifiex_pm_wakeup_card_complete,
3425
3426 /* PCIE specific */
3427 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete,
3428 .event_complete = mwifiex_pcie_event_complete,
3429 .update_mp_end_port = NULL,
3430 .cleanup_mpa_buf = NULL,
3431 .init_fw_port = mwifiex_pcie_init_fw_port,
3432 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf,
3433 .card_reset = mwifiex_pcie_card_reset,
3434 .reg_dump = mwifiex_pcie_reg_dump,
3435 .device_dump = mwifiex_pcie_device_dump,
3436 .down_dev = mwifiex_pcie_down_dev,
3437 .up_dev = mwifiex_pcie_up_dev,
3438 };
3439
3440 module_pci_driver(mwifiex_pcie);
3441
3442 MODULE_AUTHOR("Marvell International Ltd.");
3443 MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION);
3444 MODULE_VERSION(PCIE_VERSION);
3445 MODULE_LICENSE("GPL v2");
3446