1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
4 */
5
6 #include <linux/clk.h>
7 #include <linux/device.h>
8 #include <linux/io.h>
9 #include <linux/iopoll.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/nvmem-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/regulator/consumer.h>
16
17 /* Blow timer clock frequency in Mhz */
18 #define QFPROM_BLOW_TIMER_OFFSET 0x03c
19
20 /* Amount of time required to hold charge to blow fuse in micro-seconds */
21 #define QFPROM_FUSE_BLOW_POLL_US 100
22 #define QFPROM_FUSE_BLOW_TIMEOUT_US 1000
23
24 #define QFPROM_BLOW_STATUS_OFFSET 0x048
25 #define QFPROM_BLOW_STATUS_BUSY 0x1
26 #define QFPROM_BLOW_STATUS_READY 0x0
27
28 #define QFPROM_ACCEL_OFFSET 0x044
29
30 #define QFPROM_VERSION_OFFSET 0x0
31 #define QFPROM_MAJOR_VERSION_SHIFT 28
32 #define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT)
33 #define QFPROM_MINOR_VERSION_SHIFT 16
34 #define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT)
35
36 static bool read_raw_data;
37 module_param(read_raw_data, bool, 0644);
38 MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data");
39
40 /**
41 * struct qfprom_soc_data - config that varies from SoC to SoC.
42 *
43 * @accel_value: Should contain qfprom accel value.
44 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
45 * @qfprom_blow_set_freq: The frequency required to set when we start the
46 * fuse blowing.
47 */
48 struct qfprom_soc_data {
49 u32 accel_value;
50 u32 qfprom_blow_timer_value;
51 u32 qfprom_blow_set_freq;
52 };
53
54 /**
55 * struct qfprom_priv - structure holding qfprom attributes
56 *
57 * @qfpraw: iomapped memory space for qfprom-efuse raw address space.
58 * @qfpconf: iomapped memory space for qfprom-efuse configuration address
59 * space.
60 * @qfpcorrected: iomapped memory space for qfprom corrected address space.
61 * @qfpsecurity: iomapped memory space for qfprom security control space.
62 * @dev: qfprom device structure.
63 * @secclk: Clock supply.
64 * @vcc: Regulator supply.
65 * @soc_data: Data that for things that varies from SoC to SoC.
66 */
67 struct qfprom_priv {
68 void __iomem *qfpraw;
69 void __iomem *qfpconf;
70 void __iomem *qfpcorrected;
71 void __iomem *qfpsecurity;
72 struct device *dev;
73 struct clk *secclk;
74 struct regulator *vcc;
75 const struct qfprom_soc_data *soc_data;
76 };
77
78 /**
79 * struct qfprom_touched_values - saved values to restore after blowing
80 *
81 * @clk_rate: The rate the clock was at before blowing.
82 * @accel_val: The value of the accel reg before blowing.
83 * @timer_val: The value of the timer before blowing.
84 */
85 struct qfprom_touched_values {
86 unsigned long clk_rate;
87 u32 accel_val;
88 u32 timer_val;
89 };
90
91 /**
92 * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
93 * @priv: Our driver data.
94 * @old: The data that was stashed from before fuse blowing.
95 *
96 * Resets the value of the blow timer, accel register and the clock
97 * and voltage settings.
98 *
99 * Prints messages if there are errors but doesn't return an error code
100 * since there's not much we can do upon failure.
101 */
qfprom_disable_fuse_blowing(const struct qfprom_priv * priv,const struct qfprom_touched_values * old)102 static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv,
103 const struct qfprom_touched_values *old)
104 {
105 int ret;
106
107 writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
108 writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
109
110 /*
111 * This may be a shared rail and may be able to run at a lower rate
112 * when we're not blowing fuses. At the moment, the regulator framework
113 * applies voltage constraints even on disabled rails, so remove our
114 * constraints and allow the rail to be adjusted by other users.
115 */
116 ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
117 if (ret)
118 dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");
119
120 ret = regulator_disable(priv->vcc);
121 if (ret)
122 dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n");
123
124 ret = clk_set_rate(priv->secclk, old->clk_rate);
125 if (ret)
126 dev_warn(priv->dev,
127 "Failed to set clock rate for disable (ignoring)\n");
128
129 clk_disable_unprepare(priv->secclk);
130 }
131
132 /**
133 * qfprom_enable_fuse_blowing() - Enable fuse blowing.
134 * @priv: Our driver data.
135 * @old: We'll stash stuff here to use when disabling.
136 *
137 * Sets the value of the blow timer, accel register and the clock
138 * and voltage settings.
139 *
140 * Prints messages if there are errors so caller doesn't need to.
141 *
142 * Return: 0 or -err.
143 */
qfprom_enable_fuse_blowing(const struct qfprom_priv * priv,struct qfprom_touched_values * old)144 static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv,
145 struct qfprom_touched_values *old)
146 {
147 int ret;
148
149 ret = clk_prepare_enable(priv->secclk);
150 if (ret) {
151 dev_err(priv->dev, "Failed to enable clock\n");
152 return ret;
153 }
154
155 old->clk_rate = clk_get_rate(priv->secclk);
156 ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq);
157 if (ret) {
158 dev_err(priv->dev, "Failed to set clock rate for enable\n");
159 goto err_clk_prepared;
160 }
161
162 /*
163 * Hardware requires 1.8V min for fuse blowing; this may be
164 * a rail shared do don't specify a max--regulator constraints
165 * will handle.
166 */
167 ret = regulator_set_voltage(priv->vcc, 1800000, INT_MAX);
168 if (ret) {
169 dev_err(priv->dev, "Failed to set 1.8 voltage\n");
170 goto err_clk_rate_set;
171 }
172
173 ret = regulator_enable(priv->vcc);
174 if (ret) {
175 dev_err(priv->dev, "Failed to enable regulator\n");
176 goto err_clk_rate_set;
177 }
178
179 old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
180 old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET);
181 writel(priv->soc_data->qfprom_blow_timer_value,
182 priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
183 writel(priv->soc_data->accel_value,
184 priv->qfpconf + QFPROM_ACCEL_OFFSET);
185
186 return 0;
187
188 err_clk_rate_set:
189 clk_set_rate(priv->secclk, old->clk_rate);
190 err_clk_prepared:
191 clk_disable_unprepare(priv->secclk);
192 return ret;
193 }
194
195 /**
196 * qfprom_efuse_reg_write() - Write to fuses.
197 * @context: Our driver data.
198 * @reg: The offset to write at.
199 * @_val: Pointer to data to write.
200 * @bytes: The number of bytes to write.
201 *
202 * Writes to fuses. WARNING: THIS IS PERMANENT.
203 *
204 * Return: 0 or -err.
205 */
qfprom_reg_write(void * context,unsigned int reg,void * _val,size_t bytes)206 static int qfprom_reg_write(void *context, unsigned int reg, void *_val,
207 size_t bytes)
208 {
209 struct qfprom_priv *priv = context;
210 struct qfprom_touched_values old;
211 int words = bytes / 4;
212 u32 *value = _val;
213 u32 blow_status;
214 int ret;
215 int i;
216
217 dev_dbg(priv->dev,
218 "Writing to raw qfprom region : %#010x of size: %zu\n",
219 reg, bytes);
220
221 /*
222 * The hardware only allows us to write word at a time, but we can
223 * read byte at a time. Until the nvmem framework allows a separate
224 * word_size and stride for reading vs. writing, we'll enforce here.
225 */
226 if (bytes % 4) {
227 dev_err(priv->dev,
228 "%zu is not an integral number of words\n", bytes);
229 return -EINVAL;
230 }
231 if (reg % 4) {
232 dev_err(priv->dev,
233 "Invalid offset: %#x. Must be word aligned\n", reg);
234 return -EINVAL;
235 }
236
237 ret = qfprom_enable_fuse_blowing(priv, &old);
238 if (ret)
239 return ret;
240
241 ret = readl_relaxed_poll_timeout(
242 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
243 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
244 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
245
246 if (ret) {
247 dev_err(priv->dev,
248 "Timeout waiting for initial ready; aborting.\n");
249 goto exit_enabled_fuse_blowing;
250 }
251
252 for (i = 0; i < words; i++)
253 writel(value[i], priv->qfpraw + reg + (i * 4));
254
255 ret = readl_relaxed_poll_timeout(
256 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET,
257 blow_status, blow_status == QFPROM_BLOW_STATUS_READY,
258 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US);
259
260 /* Give an error, but not much we can do in this case */
261 if (ret)
262 dev_err(priv->dev, "Timeout waiting for finish.\n");
263
264 exit_enabled_fuse_blowing:
265 qfprom_disable_fuse_blowing(priv, &old);
266
267 return ret;
268 }
269
qfprom_reg_read(void * context,unsigned int reg,void * _val,size_t bytes)270 static int qfprom_reg_read(void *context,
271 unsigned int reg, void *_val, size_t bytes)
272 {
273 struct qfprom_priv *priv = context;
274 u8 *val = _val;
275 int i = 0, words = bytes;
276 void __iomem *base = priv->qfpcorrected;
277
278 if (read_raw_data && priv->qfpraw)
279 base = priv->qfpraw;
280
281 while (words--)
282 *val++ = readb(base + reg + i++);
283
284 return 0;
285 }
286
287 static const struct qfprom_soc_data qfprom_7_8_data = {
288 .accel_value = 0xD10,
289 .qfprom_blow_timer_value = 25,
290 .qfprom_blow_set_freq = 4800000,
291 };
292
qfprom_probe(struct platform_device * pdev)293 static int qfprom_probe(struct platform_device *pdev)
294 {
295 struct nvmem_config econfig = {
296 .name = "qfprom",
297 .stride = 1,
298 .word_size = 1,
299 .id = NVMEM_DEVID_AUTO,
300 .reg_read = qfprom_reg_read,
301 };
302 struct device *dev = &pdev->dev;
303 struct resource *res;
304 struct nvmem_device *nvmem;
305 struct qfprom_priv *priv;
306 int ret;
307
308 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
309 if (!priv)
310 return -ENOMEM;
311
312 /* The corrected section is always provided */
313 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
314 priv->qfpcorrected = devm_ioremap_resource(dev, res);
315 if (IS_ERR(priv->qfpcorrected))
316 return PTR_ERR(priv->qfpcorrected);
317
318 econfig.size = resource_size(res);
319 econfig.dev = dev;
320 econfig.priv = priv;
321
322 priv->dev = dev;
323
324 /*
325 * If more than one region is provided then the OS has the ability
326 * to write.
327 */
328 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
329 if (res) {
330 u32 version;
331 int major_version, minor_version;
332
333 priv->qfpraw = devm_ioremap_resource(dev, res);
334 if (IS_ERR(priv->qfpraw))
335 return PTR_ERR(priv->qfpraw);
336 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
337 priv->qfpconf = devm_ioremap_resource(dev, res);
338 if (IS_ERR(priv->qfpconf))
339 return PTR_ERR(priv->qfpconf);
340 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
341 priv->qfpsecurity = devm_ioremap_resource(dev, res);
342 if (IS_ERR(priv->qfpsecurity))
343 return PTR_ERR(priv->qfpsecurity);
344
345 version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET);
346 major_version = (version & QFPROM_MAJOR_VERSION_MASK) >>
347 QFPROM_MAJOR_VERSION_SHIFT;
348 minor_version = (version & QFPROM_MINOR_VERSION_MASK) >>
349 QFPROM_MINOR_VERSION_SHIFT;
350
351 if (major_version == 7 && minor_version == 8)
352 priv->soc_data = &qfprom_7_8_data;
353
354 priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
355 if (IS_ERR(priv->vcc))
356 return PTR_ERR(priv->vcc);
357
358 priv->secclk = devm_clk_get(dev, "core");
359 if (IS_ERR(priv->secclk)) {
360 ret = PTR_ERR(priv->secclk);
361 if (ret != -EPROBE_DEFER)
362 dev_err(dev, "Error getting clock: %d\n", ret);
363 return ret;
364 }
365
366 /* Only enable writing if we have SoC data. */
367 if (priv->soc_data)
368 econfig.reg_write = qfprom_reg_write;
369 }
370
371 nvmem = devm_nvmem_register(dev, &econfig);
372
373 return PTR_ERR_OR_ZERO(nvmem);
374 }
375
376 static const struct of_device_id qfprom_of_match[] = {
377 { .compatible = "qcom,qfprom",},
378 {/* sentinel */},
379 };
380 MODULE_DEVICE_TABLE(of, qfprom_of_match);
381
382 static struct platform_driver qfprom_driver = {
383 .probe = qfprom_probe,
384 .driver = {
385 .name = "qcom,qfprom",
386 .of_match_table = qfprom_of_match,
387 },
388 };
389 module_platform_driver(qfprom_driver);
390 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
391 MODULE_DESCRIPTION("Qualcomm QFPROM driver");
392 MODULE_LICENSE("GPL v2");
393