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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4  *
5  * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6  *
7  * This driver is inspired by:
8  * pinctrl-nomadik.c, please see original file for copyright information
9  * pinctrl-tegra.c, please see original file for copyright information
10  */
11 
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
38 
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS  3
44 
45 /* GPIO register offsets */
46 #define GPFSEL0		0x0	/* Function Select */
47 #define GPSET0		0x1c	/* Pin Output Set */
48 #define GPCLR0		0x28	/* Pin Output Clear */
49 #define GPLEV0		0x34	/* Pin Level */
50 #define GPEDS0		0x40	/* Pin Event Detect Status */
51 #define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
52 #define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
53 #define GPHEN0		0x64	/* Pin High Detect Enable */
54 #define GPLEN0		0x70	/* Pin Low Detect Enable */
55 #define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
56 #define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
57 #define GPPUD		0x94	/* Pin Pull-up/down Enable */
58 #define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
60 
61 #define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p)		(((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p)	((p) / 32)
64 #define GPIO_REG_SHIFT(p)	((p) % 32)
65 
66 #define PUD_2711_MASK		0x3
67 #define PUD_2711_REG_OFFSET(p)	((p) / 16)
68 #define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
69 
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
72 
73 #define BCM2711_PULL_NONE	0x0
74 #define BCM2711_PULL_UP		0x1
75 #define BCM2711_PULL_DOWN	0x2
76 
77 struct bcm2835_pinctrl {
78 	struct device *dev;
79 	void __iomem *base;
80 	int *wake_irq;
81 
82 	/* note: locking assumes each bank will have its own unsigned long */
83 	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 	unsigned int irq_type[BCM2711_NUM_GPIOS];
85 
86 	struct pinctrl_dev *pctl_dev;
87 	struct gpio_chip gpio_chip;
88 	struct pinctrl_desc pctl_desc;
89 	struct pinctrl_gpio_range gpio_range;
90 
91 	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
92 };
93 
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
97 	BCM2835_GPIO_PIN(0),
98 	BCM2835_GPIO_PIN(1),
99 	BCM2835_GPIO_PIN(2),
100 	BCM2835_GPIO_PIN(3),
101 	BCM2835_GPIO_PIN(4),
102 	BCM2835_GPIO_PIN(5),
103 	BCM2835_GPIO_PIN(6),
104 	BCM2835_GPIO_PIN(7),
105 	BCM2835_GPIO_PIN(8),
106 	BCM2835_GPIO_PIN(9),
107 	BCM2835_GPIO_PIN(10),
108 	BCM2835_GPIO_PIN(11),
109 	BCM2835_GPIO_PIN(12),
110 	BCM2835_GPIO_PIN(13),
111 	BCM2835_GPIO_PIN(14),
112 	BCM2835_GPIO_PIN(15),
113 	BCM2835_GPIO_PIN(16),
114 	BCM2835_GPIO_PIN(17),
115 	BCM2835_GPIO_PIN(18),
116 	BCM2835_GPIO_PIN(19),
117 	BCM2835_GPIO_PIN(20),
118 	BCM2835_GPIO_PIN(21),
119 	BCM2835_GPIO_PIN(22),
120 	BCM2835_GPIO_PIN(23),
121 	BCM2835_GPIO_PIN(24),
122 	BCM2835_GPIO_PIN(25),
123 	BCM2835_GPIO_PIN(26),
124 	BCM2835_GPIO_PIN(27),
125 	BCM2835_GPIO_PIN(28),
126 	BCM2835_GPIO_PIN(29),
127 	BCM2835_GPIO_PIN(30),
128 	BCM2835_GPIO_PIN(31),
129 	BCM2835_GPIO_PIN(32),
130 	BCM2835_GPIO_PIN(33),
131 	BCM2835_GPIO_PIN(34),
132 	BCM2835_GPIO_PIN(35),
133 	BCM2835_GPIO_PIN(36),
134 	BCM2835_GPIO_PIN(37),
135 	BCM2835_GPIO_PIN(38),
136 	BCM2835_GPIO_PIN(39),
137 	BCM2835_GPIO_PIN(40),
138 	BCM2835_GPIO_PIN(41),
139 	BCM2835_GPIO_PIN(42),
140 	BCM2835_GPIO_PIN(43),
141 	BCM2835_GPIO_PIN(44),
142 	BCM2835_GPIO_PIN(45),
143 	BCM2835_GPIO_PIN(46),
144 	BCM2835_GPIO_PIN(47),
145 	BCM2835_GPIO_PIN(48),
146 	BCM2835_GPIO_PIN(49),
147 	BCM2835_GPIO_PIN(50),
148 	BCM2835_GPIO_PIN(51),
149 	BCM2835_GPIO_PIN(52),
150 	BCM2835_GPIO_PIN(53),
151 	BCM2835_GPIO_PIN(54),
152 	BCM2835_GPIO_PIN(55),
153 	BCM2835_GPIO_PIN(56),
154 	BCM2835_GPIO_PIN(57),
155 };
156 
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
159 	"gpio0",
160 	"gpio1",
161 	"gpio2",
162 	"gpio3",
163 	"gpio4",
164 	"gpio5",
165 	"gpio6",
166 	"gpio7",
167 	"gpio8",
168 	"gpio9",
169 	"gpio10",
170 	"gpio11",
171 	"gpio12",
172 	"gpio13",
173 	"gpio14",
174 	"gpio15",
175 	"gpio16",
176 	"gpio17",
177 	"gpio18",
178 	"gpio19",
179 	"gpio20",
180 	"gpio21",
181 	"gpio22",
182 	"gpio23",
183 	"gpio24",
184 	"gpio25",
185 	"gpio26",
186 	"gpio27",
187 	"gpio28",
188 	"gpio29",
189 	"gpio30",
190 	"gpio31",
191 	"gpio32",
192 	"gpio33",
193 	"gpio34",
194 	"gpio35",
195 	"gpio36",
196 	"gpio37",
197 	"gpio38",
198 	"gpio39",
199 	"gpio40",
200 	"gpio41",
201 	"gpio42",
202 	"gpio43",
203 	"gpio44",
204 	"gpio45",
205 	"gpio46",
206 	"gpio47",
207 	"gpio48",
208 	"gpio49",
209 	"gpio50",
210 	"gpio51",
211 	"gpio52",
212 	"gpio53",
213 	"gpio54",
214 	"gpio55",
215 	"gpio56",
216 	"gpio57",
217 };
218 
219 enum bcm2835_fsel {
220 	BCM2835_FSEL_COUNT = 8,
221 	BCM2835_FSEL_MASK = 0x7,
222 };
223 
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 	[BCM2835_FSEL_ALT0] = "alt0",
228 	[BCM2835_FSEL_ALT1] = "alt1",
229 	[BCM2835_FSEL_ALT2] = "alt2",
230 	[BCM2835_FSEL_ALT3] = "alt3",
231 	[BCM2835_FSEL_ALT4] = "alt4",
232 	[BCM2835_FSEL_ALT5] = "alt5",
233 };
234 
235 static const char * const irq_type_names[] = {
236 	[IRQ_TYPE_NONE] = "none",
237 	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 	[IRQ_TYPE_LEVEL_LOW] = "level-low",
242 };
243 
bcm2835_gpio_rd(struct bcm2835_pinctrl * pc,unsigned reg)244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
245 {
246 	return readl(pc->base + reg);
247 }
248 
bcm2835_gpio_wr(struct bcm2835_pinctrl * pc,unsigned reg,u32 val)249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
250 		u32 val)
251 {
252 	writel(val, pc->base + reg);
253 }
254 
bcm2835_gpio_get_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
256 		unsigned bit)
257 {
258 	reg += GPIO_REG_OFFSET(bit) * 4;
259 	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
260 }
261 
262 /* note NOT a read/modify/write cycle */
bcm2835_gpio_set_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 		unsigned reg, unsigned bit)
265 {
266 	reg += GPIO_REG_OFFSET(bit) * 4;
267 	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
268 }
269 
bcm2835_pinctrl_fsel_get(struct bcm2835_pinctrl * pc,unsigned pin)270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 		struct bcm2835_pinctrl *pc, unsigned pin)
272 {
273 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
275 
276 	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 			bcm2835_functions[status]);
278 
279 	return status;
280 }
281 
bcm2835_pinctrl_fsel_set(struct bcm2835_pinctrl * pc,unsigned pin,enum bcm2835_fsel fsel)282 static inline void bcm2835_pinctrl_fsel_set(
283 		struct bcm2835_pinctrl *pc, unsigned pin,
284 		enum bcm2835_fsel fsel)
285 {
286 	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
288 
289 	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 			bcm2835_functions[cur]);
291 
292 	if (cur == fsel)
293 		return;
294 
295 	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 		/* always transition through GPIO_IN */
297 		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
299 
300 		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
303 	}
304 
305 	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 	val |= fsel << FSEL_SHIFT(pin);
307 
308 	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 			bcm2835_functions[fsel]);
310 	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
311 }
312 
bcm2835_gpio_direction_input(struct gpio_chip * chip,unsigned offset)313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
314 {
315 	return pinctrl_gpio_direction_input(chip->base + offset);
316 }
317 
bcm2835_gpio_get(struct gpio_chip * chip,unsigned offset)318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
319 {
320 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
321 
322 	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
323 }
324 
bcm2835_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
326 {
327 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
329 
330 	/* Alternative function doesn't clearly provide a direction */
331 	if (fsel > BCM2835_FSEL_GPIO_OUT)
332 		return -EINVAL;
333 
334 	if (fsel == BCM2835_FSEL_GPIO_IN)
335 		return GPIO_LINE_DIRECTION_IN;
336 
337 	return GPIO_LINE_DIRECTION_OUT;
338 }
339 
bcm2835_gpio_set(struct gpio_chip * chip,unsigned offset,int value)340 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
341 {
342 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
343 
344 	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
345 }
346 
bcm2835_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)347 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
348 		unsigned offset, int value)
349 {
350 	bcm2835_gpio_set(chip, offset, value);
351 	return pinctrl_gpio_direction_output(chip->base + offset);
352 }
353 
bcm2835_of_gpio_ranges_fallback(struct gpio_chip * gc,struct device_node * np)354 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
355 					   struct device_node *np)
356 {
357 	struct pinctrl_dev *pctldev = of_pinctrl_get(np);
358 
359 	of_node_put(np);
360 
361 	if (!pctldev)
362 		return 0;
363 
364 	gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
365 			       gc->ngpio);
366 
367 	return 0;
368 }
369 
370 static const struct gpio_chip bcm2835_gpio_chip = {
371 	.label = MODULE_NAME,
372 	.owner = THIS_MODULE,
373 	.request = gpiochip_generic_request,
374 	.free = gpiochip_generic_free,
375 	.direction_input = bcm2835_gpio_direction_input,
376 	.direction_output = bcm2835_gpio_direction_output,
377 	.get_direction = bcm2835_gpio_get_direction,
378 	.get = bcm2835_gpio_get,
379 	.set = bcm2835_gpio_set,
380 	.set_config = gpiochip_generic_config,
381 	.base = -1,
382 	.ngpio = BCM2835_NUM_GPIOS,
383 	.can_sleep = false,
384 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
385 };
386 
387 static const struct gpio_chip bcm2711_gpio_chip = {
388 	.label = "pinctrl-bcm2711",
389 	.owner = THIS_MODULE,
390 	.request = gpiochip_generic_request,
391 	.free = gpiochip_generic_free,
392 	.direction_input = bcm2835_gpio_direction_input,
393 	.direction_output = bcm2835_gpio_direction_output,
394 	.get_direction = bcm2835_gpio_get_direction,
395 	.get = bcm2835_gpio_get,
396 	.set = bcm2835_gpio_set,
397 	.set_config = gpiochip_generic_config,
398 	.base = -1,
399 	.ngpio = BCM2711_NUM_GPIOS,
400 	.can_sleep = false,
401 	.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
402 };
403 
bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl * pc,unsigned int bank,u32 mask)404 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
405 					 unsigned int bank, u32 mask)
406 {
407 	unsigned long events;
408 	unsigned offset;
409 	unsigned gpio;
410 
411 	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
412 	events &= mask;
413 	events &= pc->enabled_irq_map[bank];
414 	for_each_set_bit(offset, &events, 32) {
415 		gpio = (32 * bank) + offset;
416 		generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
417 						     gpio));
418 	}
419 }
420 
bcm2835_gpio_irq_handler(struct irq_desc * desc)421 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
422 {
423 	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
424 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
425 	struct irq_chip *host_chip = irq_desc_get_chip(desc);
426 	int irq = irq_desc_get_irq(desc);
427 	int group;
428 	int i;
429 
430 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
431 		if (chip->irq.parents[i] == irq) {
432 			group = i;
433 			break;
434 		}
435 	}
436 	/* This should not happen, every IRQ has a bank */
437 	if (i == BCM2835_NUM_IRQS)
438 		BUG();
439 
440 	chained_irq_enter(host_chip, desc);
441 
442 	switch (group) {
443 	case 0: /* IRQ0 covers GPIOs 0-27 */
444 		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
445 		break;
446 	case 1: /* IRQ1 covers GPIOs 28-45 */
447 		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
448 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
449 		break;
450 	case 2: /* IRQ2 covers GPIOs 46-57 */
451 		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
452 		break;
453 	}
454 
455 	chained_irq_exit(host_chip, desc);
456 }
457 
bcm2835_gpio_wake_irq_handler(int irq,void * dev_id)458 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
459 {
460 	return IRQ_HANDLED;
461 }
462 
__bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned reg,unsigned offset,bool enable)463 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
464 	unsigned reg, unsigned offset, bool enable)
465 {
466 	u32 value;
467 	reg += GPIO_REG_OFFSET(offset) * 4;
468 	value = bcm2835_gpio_rd(pc, reg);
469 	if (enable)
470 		value |= BIT(GPIO_REG_SHIFT(offset));
471 	else
472 		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
473 	bcm2835_gpio_wr(pc, reg, value);
474 }
475 
476 /* fast path for IRQ handler */
bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned offset,bool enable)477 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
478 	unsigned offset, bool enable)
479 {
480 	switch (pc->irq_type[offset]) {
481 	case IRQ_TYPE_EDGE_RISING:
482 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
483 		break;
484 
485 	case IRQ_TYPE_EDGE_FALLING:
486 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
487 		break;
488 
489 	case IRQ_TYPE_EDGE_BOTH:
490 		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
491 		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
492 		break;
493 
494 	case IRQ_TYPE_LEVEL_HIGH:
495 		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
496 		break;
497 
498 	case IRQ_TYPE_LEVEL_LOW:
499 		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
500 		break;
501 	}
502 }
503 
bcm2835_gpio_irq_enable(struct irq_data * data)504 static void bcm2835_gpio_irq_enable(struct irq_data *data)
505 {
506 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
507 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
508 	unsigned gpio = irqd_to_hwirq(data);
509 	unsigned offset = GPIO_REG_SHIFT(gpio);
510 	unsigned bank = GPIO_REG_OFFSET(gpio);
511 	unsigned long flags;
512 
513 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
514 	set_bit(offset, &pc->enabled_irq_map[bank]);
515 	bcm2835_gpio_irq_config(pc, gpio, true);
516 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
517 }
518 
bcm2835_gpio_irq_disable(struct irq_data * data)519 static void bcm2835_gpio_irq_disable(struct irq_data *data)
520 {
521 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
522 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
523 	unsigned gpio = irqd_to_hwirq(data);
524 	unsigned offset = GPIO_REG_SHIFT(gpio);
525 	unsigned bank = GPIO_REG_OFFSET(gpio);
526 	unsigned long flags;
527 
528 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
529 	bcm2835_gpio_irq_config(pc, gpio, false);
530 	/* Clear events that were latched prior to clearing event sources */
531 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
532 	clear_bit(offset, &pc->enabled_irq_map[bank]);
533 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
534 }
535 
__bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)536 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
537 	unsigned offset, unsigned int type)
538 {
539 	switch (type) {
540 	case IRQ_TYPE_NONE:
541 	case IRQ_TYPE_EDGE_RISING:
542 	case IRQ_TYPE_EDGE_FALLING:
543 	case IRQ_TYPE_EDGE_BOTH:
544 	case IRQ_TYPE_LEVEL_HIGH:
545 	case IRQ_TYPE_LEVEL_LOW:
546 		pc->irq_type[offset] = type;
547 		break;
548 
549 	default:
550 		return -EINVAL;
551 	}
552 	return 0;
553 }
554 
555 /* slower path for reconfiguring IRQ type */
__bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)556 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
557 	unsigned offset, unsigned int type)
558 {
559 	switch (type) {
560 	case IRQ_TYPE_NONE:
561 		if (pc->irq_type[offset] != type) {
562 			bcm2835_gpio_irq_config(pc, offset, false);
563 			pc->irq_type[offset] = type;
564 		}
565 		break;
566 
567 	case IRQ_TYPE_EDGE_RISING:
568 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
569 			/* RISING already enabled, disable FALLING */
570 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
571 			bcm2835_gpio_irq_config(pc, offset, false);
572 			pc->irq_type[offset] = type;
573 		} else if (pc->irq_type[offset] != type) {
574 			bcm2835_gpio_irq_config(pc, offset, false);
575 			pc->irq_type[offset] = type;
576 			bcm2835_gpio_irq_config(pc, offset, true);
577 		}
578 		break;
579 
580 	case IRQ_TYPE_EDGE_FALLING:
581 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
582 			/* FALLING already enabled, disable RISING */
583 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
584 			bcm2835_gpio_irq_config(pc, offset, false);
585 			pc->irq_type[offset] = type;
586 		} else if (pc->irq_type[offset] != type) {
587 			bcm2835_gpio_irq_config(pc, offset, false);
588 			pc->irq_type[offset] = type;
589 			bcm2835_gpio_irq_config(pc, offset, true);
590 		}
591 		break;
592 
593 	case IRQ_TYPE_EDGE_BOTH:
594 		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
595 			/* RISING already enabled, enable FALLING too */
596 			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
597 			bcm2835_gpio_irq_config(pc, offset, true);
598 			pc->irq_type[offset] = type;
599 		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
600 			/* FALLING already enabled, enable RISING too */
601 			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
602 			bcm2835_gpio_irq_config(pc, offset, true);
603 			pc->irq_type[offset] = type;
604 		} else if (pc->irq_type[offset] != type) {
605 			bcm2835_gpio_irq_config(pc, offset, false);
606 			pc->irq_type[offset] = type;
607 			bcm2835_gpio_irq_config(pc, offset, true);
608 		}
609 		break;
610 
611 	case IRQ_TYPE_LEVEL_HIGH:
612 	case IRQ_TYPE_LEVEL_LOW:
613 		if (pc->irq_type[offset] != type) {
614 			bcm2835_gpio_irq_config(pc, offset, false);
615 			pc->irq_type[offset] = type;
616 			bcm2835_gpio_irq_config(pc, offset, true);
617 		}
618 		break;
619 
620 	default:
621 		return -EINVAL;
622 	}
623 	return 0;
624 }
625 
bcm2835_gpio_irq_set_type(struct irq_data * data,unsigned int type)626 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
627 {
628 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
629 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
630 	unsigned gpio = irqd_to_hwirq(data);
631 	unsigned offset = GPIO_REG_SHIFT(gpio);
632 	unsigned bank = GPIO_REG_OFFSET(gpio);
633 	unsigned long flags;
634 	int ret;
635 
636 	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
637 
638 	if (test_bit(offset, &pc->enabled_irq_map[bank]))
639 		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
640 	else
641 		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
642 
643 	if (type & IRQ_TYPE_EDGE_BOTH)
644 		irq_set_handler_locked(data, handle_edge_irq);
645 	else
646 		irq_set_handler_locked(data, handle_level_irq);
647 
648 	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
649 
650 	return ret;
651 }
652 
bcm2835_gpio_irq_ack(struct irq_data * data)653 static void bcm2835_gpio_irq_ack(struct irq_data *data)
654 {
655 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
656 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
657 	unsigned gpio = irqd_to_hwirq(data);
658 
659 	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
660 }
661 
bcm2835_gpio_irq_set_wake(struct irq_data * data,unsigned int on)662 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
663 {
664 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
665 	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
666 	unsigned gpio = irqd_to_hwirq(data);
667 	unsigned int irqgroup;
668 	int ret = -EINVAL;
669 
670 	if (!pc->wake_irq)
671 		return ret;
672 
673 	if (gpio <= 27)
674 		irqgroup = 0;
675 	else if (gpio >= 28 && gpio <= 45)
676 		irqgroup = 1;
677 	else if (gpio >= 46 && gpio <= 57)
678 		irqgroup = 2;
679 	else
680 		return ret;
681 
682 	if (on)
683 		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
684 	else
685 		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
686 
687 	return ret;
688 }
689 
690 static struct irq_chip bcm2835_gpio_irq_chip = {
691 	.name = MODULE_NAME,
692 	.irq_enable = bcm2835_gpio_irq_enable,
693 	.irq_disable = bcm2835_gpio_irq_disable,
694 	.irq_set_type = bcm2835_gpio_irq_set_type,
695 	.irq_ack = bcm2835_gpio_irq_ack,
696 	.irq_mask = bcm2835_gpio_irq_disable,
697 	.irq_unmask = bcm2835_gpio_irq_enable,
698 	.irq_set_wake = bcm2835_gpio_irq_set_wake,
699 	.flags = IRQCHIP_MASK_ON_SUSPEND,
700 };
701 
bcm2835_pctl_get_groups_count(struct pinctrl_dev * pctldev)702 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
703 {
704 	return BCM2835_NUM_GPIOS;
705 }
706 
bcm2835_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)707 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
708 		unsigned selector)
709 {
710 	return bcm2835_gpio_groups[selector];
711 }
712 
bcm2835_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * num_pins)713 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
714 		unsigned selector,
715 		const unsigned **pins,
716 		unsigned *num_pins)
717 {
718 	*pins = &bcm2835_gpio_pins[selector].number;
719 	*num_pins = 1;
720 
721 	return 0;
722 }
723 
bcm2835_pctl_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)724 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
725 		struct seq_file *s,
726 		unsigned offset)
727 {
728 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
729 	struct gpio_chip *chip = &pc->gpio_chip;
730 	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
731 	const char *fname = bcm2835_functions[fsel];
732 	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
733 	int irq = irq_find_mapping(chip->irq.domain, offset);
734 
735 	seq_printf(s, "function %s in %s; irq %d (%s)",
736 		fname, value ? "hi" : "lo",
737 		irq, irq_type_names[pc->irq_type[offset]]);
738 }
739 
bcm2835_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * maps,unsigned num_maps)740 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
741 		struct pinctrl_map *maps, unsigned num_maps)
742 {
743 	int i;
744 
745 	for (i = 0; i < num_maps; i++)
746 		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
747 			kfree(maps[i].data.configs.configs);
748 
749 	kfree(maps);
750 }
751 
bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 fnum,struct pinctrl_map ** maps)752 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
753 		struct device_node *np, u32 pin, u32 fnum,
754 		struct pinctrl_map **maps)
755 {
756 	struct pinctrl_map *map = *maps;
757 
758 	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
759 		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
760 		return -EINVAL;
761 	}
762 
763 	map->type = PIN_MAP_TYPE_MUX_GROUP;
764 	map->data.mux.group = bcm2835_gpio_groups[pin];
765 	map->data.mux.function = bcm2835_functions[fnum];
766 	(*maps)++;
767 
768 	return 0;
769 }
770 
bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 pull,struct pinctrl_map ** maps)771 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
772 		struct device_node *np, u32 pin, u32 pull,
773 		struct pinctrl_map **maps)
774 {
775 	struct pinctrl_map *map = *maps;
776 	unsigned long *configs;
777 
778 	if (pull > 2) {
779 		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
780 		return -EINVAL;
781 	}
782 
783 	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
784 	if (!configs)
785 		return -ENOMEM;
786 	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
787 
788 	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
789 	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
790 	map->data.configs.configs = configs;
791 	map->data.configs.num_configs = 1;
792 	(*maps)++;
793 
794 	return 0;
795 }
796 
bcm2835_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)797 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
798 		struct device_node *np,
799 		struct pinctrl_map **map, unsigned int *num_maps)
800 {
801 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
802 	struct property *pins, *funcs, *pulls;
803 	int num_pins, num_funcs, num_pulls, maps_per_pin;
804 	struct pinctrl_map *maps, *cur_map;
805 	int i, err;
806 	u32 pin, func, pull;
807 
808 	/* Check for generic binding in this node */
809 	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
810 	if (err || *num_maps)
811 		return err;
812 
813 	/* Generic binding did not find anything continue with legacy parse */
814 	pins = of_find_property(np, "brcm,pins", NULL);
815 	if (!pins) {
816 		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
817 		return -EINVAL;
818 	}
819 
820 	funcs = of_find_property(np, "brcm,function", NULL);
821 	pulls = of_find_property(np, "brcm,pull", NULL);
822 
823 	if (!funcs && !pulls) {
824 		dev_err(pc->dev,
825 			"%pOF: neither brcm,function nor brcm,pull specified\n",
826 			np);
827 		return -EINVAL;
828 	}
829 
830 	num_pins = pins->length / 4;
831 	num_funcs = funcs ? (funcs->length / 4) : 0;
832 	num_pulls = pulls ? (pulls->length / 4) : 0;
833 
834 	if (num_funcs > 1 && num_funcs != num_pins) {
835 		dev_err(pc->dev,
836 			"%pOF: brcm,function must have 1 or %d entries\n",
837 			np, num_pins);
838 		return -EINVAL;
839 	}
840 
841 	if (num_pulls > 1 && num_pulls != num_pins) {
842 		dev_err(pc->dev,
843 			"%pOF: brcm,pull must have 1 or %d entries\n",
844 			np, num_pins);
845 		return -EINVAL;
846 	}
847 
848 	maps_per_pin = 0;
849 	if (num_funcs)
850 		maps_per_pin++;
851 	if (num_pulls)
852 		maps_per_pin++;
853 	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
854 				 GFP_KERNEL);
855 	if (!maps)
856 		return -ENOMEM;
857 
858 	for (i = 0; i < num_pins; i++) {
859 		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
860 		if (err)
861 			goto out;
862 		if (pin >= pc->pctl_desc.npins) {
863 			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
864 				np, pin);
865 			err = -EINVAL;
866 			goto out;
867 		}
868 
869 		if (num_funcs) {
870 			err = of_property_read_u32_index(np, "brcm,function",
871 					(num_funcs > 1) ? i : 0, &func);
872 			if (err)
873 				goto out;
874 			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
875 							func, &cur_map);
876 			if (err)
877 				goto out;
878 		}
879 		if (num_pulls) {
880 			err = of_property_read_u32_index(np, "brcm,pull",
881 					(num_pulls > 1) ? i : 0, &pull);
882 			if (err)
883 				goto out;
884 			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
885 							pull, &cur_map);
886 			if (err)
887 				goto out;
888 		}
889 	}
890 
891 	*map = maps;
892 	*num_maps = num_pins * maps_per_pin;
893 
894 	return 0;
895 
896 out:
897 	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
898 	return err;
899 }
900 
901 static const struct pinctrl_ops bcm2835_pctl_ops = {
902 	.get_groups_count = bcm2835_pctl_get_groups_count,
903 	.get_group_name = bcm2835_pctl_get_group_name,
904 	.get_group_pins = bcm2835_pctl_get_group_pins,
905 	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
906 	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
907 	.dt_free_map = bcm2835_pctl_dt_free_map,
908 };
909 
bcm2835_pmx_free(struct pinctrl_dev * pctldev,unsigned offset)910 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
911 		unsigned offset)
912 {
913 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
914 
915 	/* disable by setting to GPIO_IN */
916 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
917 	return 0;
918 }
919 
bcm2835_pmx_get_functions_count(struct pinctrl_dev * pctldev)920 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
921 {
922 	return BCM2835_FSEL_COUNT;
923 }
924 
bcm2835_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned selector)925 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
926 		unsigned selector)
927 {
928 	return bcm2835_functions[selector];
929 }
930 
bcm2835_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)931 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
932 		unsigned selector,
933 		const char * const **groups,
934 		unsigned * const num_groups)
935 {
936 	/* every pin can do every function */
937 	*groups = bcm2835_gpio_groups;
938 	*num_groups = BCM2835_NUM_GPIOS;
939 
940 	return 0;
941 }
942 
bcm2835_pmx_set(struct pinctrl_dev * pctldev,unsigned func_selector,unsigned group_selector)943 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
944 		unsigned func_selector,
945 		unsigned group_selector)
946 {
947 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
948 
949 	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
950 
951 	return 0;
952 }
953 
bcm2835_pmx_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)954 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
955 		struct pinctrl_gpio_range *range,
956 		unsigned offset)
957 {
958 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
959 
960 	/* disable by setting to GPIO_IN */
961 	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
962 }
963 
bcm2835_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)964 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
965 		struct pinctrl_gpio_range *range,
966 		unsigned offset,
967 		bool input)
968 {
969 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
970 	enum bcm2835_fsel fsel = input ?
971 		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
972 
973 	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
974 
975 	return 0;
976 }
977 
978 static const struct pinmux_ops bcm2835_pmx_ops = {
979 	.free = bcm2835_pmx_free,
980 	.get_functions_count = bcm2835_pmx_get_functions_count,
981 	.get_function_name = bcm2835_pmx_get_function_name,
982 	.get_function_groups = bcm2835_pmx_get_function_groups,
983 	.set_mux = bcm2835_pmx_set,
984 	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
985 	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
986 };
987 
bcm2835_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)988 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
989 			unsigned pin, unsigned long *config)
990 {
991 	/* No way to read back config in HW */
992 	return -ENOTSUPP;
993 }
994 
bcm2835_pull_config_set(struct bcm2835_pinctrl * pc,unsigned int pin,unsigned int arg)995 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
996 		unsigned int pin, unsigned int arg)
997 {
998 	u32 off, bit;
999 
1000 	off = GPIO_REG_OFFSET(pin);
1001 	bit = GPIO_REG_SHIFT(pin);
1002 
1003 	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1004 	/*
1005 	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1006 	 * But the VideoCore firmware delay for this operation
1007 	 * based nearly on the same amount of VPU cycles and this clock
1008 	 * runs at 250 MHz.
1009 	 */
1010 	udelay(1);
1011 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1012 	udelay(1);
1013 	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1014 }
1015 
bcm2835_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1016 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1017 			unsigned int pin, unsigned long *configs,
1018 			unsigned int num_configs)
1019 {
1020 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1021 	u32 param, arg;
1022 	int i;
1023 
1024 	for (i = 0; i < num_configs; i++) {
1025 		param = pinconf_to_config_param(configs[i]);
1026 		arg = pinconf_to_config_argument(configs[i]);
1027 
1028 		switch (param) {
1029 		/* Set legacy brcm,pull */
1030 		case BCM2835_PINCONF_PARAM_PULL:
1031 			bcm2835_pull_config_set(pc, pin, arg);
1032 			break;
1033 
1034 		/* Set pull generic bindings */
1035 		case PIN_CONFIG_BIAS_DISABLE:
1036 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1037 			break;
1038 
1039 		case PIN_CONFIG_BIAS_PULL_DOWN:
1040 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1041 			break;
1042 
1043 		case PIN_CONFIG_BIAS_PULL_UP:
1044 			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1045 			break;
1046 
1047 		/* Set output-high or output-low */
1048 		case PIN_CONFIG_OUTPUT:
1049 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1050 			break;
1051 
1052 		default:
1053 			return -ENOTSUPP;
1054 
1055 		} /* switch param type */
1056 	} /* for each config */
1057 
1058 	return 0;
1059 }
1060 
1061 static const struct pinconf_ops bcm2835_pinconf_ops = {
1062 	.is_generic = true,
1063 	.pin_config_get = bcm2835_pinconf_get,
1064 	.pin_config_set = bcm2835_pinconf_set,
1065 };
1066 
bcm2711_pull_config_set(struct bcm2835_pinctrl * pc,unsigned int pin,unsigned int arg)1067 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1068 				    unsigned int pin, unsigned int arg)
1069 {
1070 	u32 shifter;
1071 	u32 value;
1072 	u32 off;
1073 
1074 	off = PUD_2711_REG_OFFSET(pin);
1075 	shifter = PUD_2711_REG_SHIFT(pin);
1076 
1077 	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1078 	value &= ~(PUD_2711_MASK << shifter);
1079 	value |= (arg << shifter);
1080 	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1081 }
1082 
bcm2711_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1083 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1084 			       unsigned int pin, unsigned long *configs,
1085 			       unsigned int num_configs)
1086 {
1087 	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1088 	u32 param, arg;
1089 	int i;
1090 
1091 	for (i = 0; i < num_configs; i++) {
1092 		param = pinconf_to_config_param(configs[i]);
1093 		arg = pinconf_to_config_argument(configs[i]);
1094 
1095 		switch (param) {
1096 		/* convert legacy brcm,pull */
1097 		case BCM2835_PINCONF_PARAM_PULL:
1098 			if (arg == BCM2835_PUD_UP)
1099 				arg = BCM2711_PULL_UP;
1100 			else if (arg == BCM2835_PUD_DOWN)
1101 				arg = BCM2711_PULL_DOWN;
1102 			else
1103 				arg = BCM2711_PULL_NONE;
1104 
1105 			bcm2711_pull_config_set(pc, pin, arg);
1106 			break;
1107 
1108 		/* Set pull generic bindings */
1109 		case PIN_CONFIG_BIAS_DISABLE:
1110 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1111 			break;
1112 		case PIN_CONFIG_BIAS_PULL_DOWN:
1113 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1114 			break;
1115 		case PIN_CONFIG_BIAS_PULL_UP:
1116 			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1117 			break;
1118 
1119 		/* Set output-high or output-low */
1120 		case PIN_CONFIG_OUTPUT:
1121 			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1122 			break;
1123 
1124 		default:
1125 			return -ENOTSUPP;
1126 		}
1127 	} /* for each config */
1128 
1129 	return 0;
1130 }
1131 
1132 static const struct pinconf_ops bcm2711_pinconf_ops = {
1133 	.is_generic = true,
1134 	.pin_config_get = bcm2835_pinconf_get,
1135 	.pin_config_set = bcm2711_pinconf_set,
1136 };
1137 
1138 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1139 	.name = MODULE_NAME,
1140 	.pins = bcm2835_gpio_pins,
1141 	.npins = BCM2835_NUM_GPIOS,
1142 	.pctlops = &bcm2835_pctl_ops,
1143 	.pmxops = &bcm2835_pmx_ops,
1144 	.confops = &bcm2835_pinconf_ops,
1145 	.owner = THIS_MODULE,
1146 };
1147 
1148 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1149 	.name = "pinctrl-bcm2711",
1150 	.pins = bcm2835_gpio_pins,
1151 	.npins = BCM2711_NUM_GPIOS,
1152 	.pctlops = &bcm2835_pctl_ops,
1153 	.pmxops = &bcm2835_pmx_ops,
1154 	.confops = &bcm2711_pinconf_ops,
1155 	.owner = THIS_MODULE,
1156 };
1157 
1158 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1159 	.name = MODULE_NAME,
1160 	.npins = BCM2835_NUM_GPIOS,
1161 };
1162 
1163 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1164 	.name = "pinctrl-bcm2711",
1165 	.npins = BCM2711_NUM_GPIOS,
1166 };
1167 
1168 struct bcm_plat_data {
1169 	const struct gpio_chip *gpio_chip;
1170 	const struct pinctrl_desc *pctl_desc;
1171 	const struct pinctrl_gpio_range *gpio_range;
1172 };
1173 
1174 static const struct bcm_plat_data bcm2835_plat_data = {
1175 	.gpio_chip = &bcm2835_gpio_chip,
1176 	.pctl_desc = &bcm2835_pinctrl_desc,
1177 	.gpio_range = &bcm2835_pinctrl_gpio_range,
1178 };
1179 
1180 static const struct bcm_plat_data bcm2711_plat_data = {
1181 	.gpio_chip = &bcm2711_gpio_chip,
1182 	.pctl_desc = &bcm2711_pinctrl_desc,
1183 	.gpio_range = &bcm2711_pinctrl_gpio_range,
1184 };
1185 
1186 static const struct of_device_id bcm2835_pinctrl_match[] = {
1187 	{
1188 		.compatible = "brcm,bcm2835-gpio",
1189 		.data = &bcm2835_plat_data,
1190 	},
1191 	{
1192 		.compatible = "brcm,bcm2711-gpio",
1193 		.data = &bcm2711_plat_data,
1194 	},
1195 	{
1196 		.compatible = "brcm,bcm7211-gpio",
1197 		.data = &bcm2711_plat_data,
1198 	},
1199 	{}
1200 };
1201 
bcm2835_pinctrl_probe(struct platform_device * pdev)1202 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1203 {
1204 	struct device *dev = &pdev->dev;
1205 	struct device_node *np = dev->of_node;
1206 	const struct bcm_plat_data *pdata;
1207 	struct bcm2835_pinctrl *pc;
1208 	struct gpio_irq_chip *girq;
1209 	struct resource iomem;
1210 	int err, i;
1211 	const struct of_device_id *match;
1212 	int is_7211 = 0;
1213 
1214 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1215 	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1216 
1217 	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1218 	if (!pc)
1219 		return -ENOMEM;
1220 
1221 	platform_set_drvdata(pdev, pc);
1222 	pc->dev = dev;
1223 
1224 	err = of_address_to_resource(np, 0, &iomem);
1225 	if (err) {
1226 		dev_err(dev, "could not get IO memory\n");
1227 		return err;
1228 	}
1229 
1230 	pc->base = devm_ioremap_resource(dev, &iomem);
1231 	if (IS_ERR(pc->base))
1232 		return PTR_ERR(pc->base);
1233 
1234 	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1235 	if (!match)
1236 		return -EINVAL;
1237 
1238 	pdata = match->data;
1239 	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1240 
1241 	pc->gpio_chip = *pdata->gpio_chip;
1242 	pc->gpio_chip.parent = dev;
1243 	pc->gpio_chip.of_node = np;
1244 
1245 	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1246 		unsigned long events;
1247 		unsigned offset;
1248 
1249 		/* clear event detection flags */
1250 		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1251 		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1252 		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1253 		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1254 		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1255 		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1256 
1257 		/* clear all the events */
1258 		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1259 		for_each_set_bit(offset, &events, 32)
1260 			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1261 
1262 		raw_spin_lock_init(&pc->irq_lock[i]);
1263 	}
1264 
1265 	pc->pctl_desc = *pdata->pctl_desc;
1266 	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1267 	if (IS_ERR(pc->pctl_dev)) {
1268 		gpiochip_remove(&pc->gpio_chip);
1269 		return PTR_ERR(pc->pctl_dev);
1270 	}
1271 
1272 	pc->gpio_range = *pdata->gpio_range;
1273 	pc->gpio_range.base = pc->gpio_chip.base;
1274 	pc->gpio_range.gc = &pc->gpio_chip;
1275 	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1276 
1277 	girq = &pc->gpio_chip.irq;
1278 	girq->chip = &bcm2835_gpio_irq_chip;
1279 	girq->parent_handler = bcm2835_gpio_irq_handler;
1280 	girq->num_parents = BCM2835_NUM_IRQS;
1281 	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1282 				     sizeof(*girq->parents),
1283 				     GFP_KERNEL);
1284 	if (!girq->parents) {
1285 		err = -ENOMEM;
1286 		goto out_remove;
1287 	}
1288 
1289 	if (is_7211) {
1290 		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1291 					    sizeof(*pc->wake_irq),
1292 					    GFP_KERNEL);
1293 		if (!pc->wake_irq) {
1294 			err = -ENOMEM;
1295 			goto out_remove;
1296 		}
1297 	}
1298 
1299 	/*
1300 	 * Use the same handler for all groups: this is necessary
1301 	 * since we use one gpiochip to cover all lines - the
1302 	 * irq handler then needs to figure out which group and
1303 	 * bank that was firing the IRQ and look up the per-group
1304 	 * and bank data.
1305 	 */
1306 	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1307 		int len;
1308 		char *name;
1309 
1310 		girq->parents[i] = irq_of_parse_and_map(np, i);
1311 		if (!is_7211)
1312 			continue;
1313 
1314 		/* Skip over the all banks interrupts */
1315 		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1316 						       BCM2835_NUM_IRQS + 1);
1317 
1318 		len = strlen(dev_name(pc->dev)) + 16;
1319 		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1320 		if (!name) {
1321 			err = -ENOMEM;
1322 			goto out_remove;
1323 		}
1324 
1325 		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1326 
1327 		/* These are optional interrupts */
1328 		err = devm_request_irq(dev, pc->wake_irq[i],
1329 				       bcm2835_gpio_wake_irq_handler,
1330 				       IRQF_SHARED, name, pc);
1331 		if (err)
1332 			dev_warn(dev, "unable to request wake IRQ %d\n",
1333 				 pc->wake_irq[i]);
1334 	}
1335 
1336 	girq->default_type = IRQ_TYPE_NONE;
1337 	girq->handler = handle_level_irq;
1338 
1339 	err = gpiochip_add_data(&pc->gpio_chip, pc);
1340 	if (err) {
1341 		dev_err(dev, "could not add GPIO chip\n");
1342 		goto out_remove;
1343 	}
1344 
1345 	return 0;
1346 
1347 out_remove:
1348 	pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1349 	return err;
1350 }
1351 
1352 static struct platform_driver bcm2835_pinctrl_driver = {
1353 	.probe = bcm2835_pinctrl_probe,
1354 	.driver = {
1355 		.name = MODULE_NAME,
1356 		.of_match_table = bcm2835_pinctrl_match,
1357 		.suppress_bind_attrs = true,
1358 	},
1359 };
1360 builtin_platform_driver(bcm2835_pinctrl_driver);
1361