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1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ATH79
26	bool "AR71xx Reset Driver" if COMPILE_TEST
27	default ATH79
28	help
29	  This enables the ATH79 reset controller driver that supports the
30	  AR71xx SoC reset controller.
31
32config RESET_AXS10X
33	bool "AXS10x Reset Driver" if COMPILE_TEST
34	default ARC_PLAT_AXS10X
35	help
36	  This enables the reset controller driver for AXS10x.
37
38config RESET_BERLIN
39	bool "Berlin Reset Driver" if COMPILE_TEST
40	default ARCH_BERLIN
41	help
42	  This enables the reset controller driver for Marvell Berlin SoCs.
43
44config RESET_BRCMSTB
45	tristate "Broadcom STB reset controller"
46	depends on ARCH_BRCMSTB || COMPILE_TEST
47	default ARCH_BRCMSTB
48	help
49	  This enables the reset controller driver for Broadcom STB SoCs using
50	  a SUN_TOP_CTRL_SW_INIT style controller.
51
52config RESET_BRCMSTB_RESCAL
53	bool "Broadcom STB RESCAL reset controller"
54	depends on HAS_IOMEM
55	depends on ARCH_BRCMSTB || COMPILE_TEST
56	default ARCH_BRCMSTB
57	help
58	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
59	  BCM7216.
60
61config RESET_HSDK
62	bool "Synopsys HSDK Reset Driver"
63	depends on HAS_IOMEM
64	depends on ARC_SOC_HSDK || COMPILE_TEST
65	help
66	  This enables the reset controller driver for HSDK board.
67
68config RESET_IMX7
69	tristate "i.MX7/8 Reset Driver"
70	depends on HAS_IOMEM
71	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
72	default y if SOC_IMX7D
73	select MFD_SYSCON
74	help
75	  This enables the reset controller driver for i.MX7 SoCs.
76
77config RESET_INTEL_GW
78	bool "Intel Reset Controller Driver"
79	depends on X86 || COMPILE_TEST
80	depends on OF && HAS_IOMEM
81	select REGMAP_MMIO
82	help
83	  This enables the reset controller driver for Intel Gateway SoCs.
84	  Say Y to control the reset signals provided by reset controller.
85	  Otherwise, say N.
86
87config RESET_LANTIQ
88	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
89	default SOC_TYPE_XWAY
90	help
91	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
92
93config RESET_LPC18XX
94	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
95	default ARCH_LPC18XX
96	help
97	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
98
99config RESET_MESON
100	bool "Meson Reset Driver" if COMPILE_TEST
101	default ARCH_MESON
102	help
103	  This enables the reset driver for Amlogic Meson SoCs.
104
105config RESET_MESON_AUDIO_ARB
106	tristate "Meson Audio Memory Arbiter Reset Driver"
107	depends on ARCH_MESON || COMPILE_TEST
108	help
109	  This enables the reset driver for Audio Memory Arbiter of
110	  Amlogic's A113 based SoCs
111
112config RESET_NPCM
113	bool "NPCM BMC Reset Driver" if COMPILE_TEST
114	default ARCH_NPCM
115	help
116	  This enables the reset controller driver for Nuvoton NPCM
117	  BMC SoCs.
118
119config RESET_OXNAS
120	bool
121
122config RESET_PISTACHIO
123	bool "Pistachio Reset Driver" if COMPILE_TEST
124	default MACH_PISTACHIO
125	help
126	  This enables the reset driver for ImgTec Pistachio SoCs.
127
128config RESET_QCOM_AOSS
129	tristate "Qcom AOSS Reset Driver"
130	depends on ARCH_QCOM || COMPILE_TEST
131	help
132	  This enables the AOSS (always on subsystem) reset driver
133	  for Qualcomm SDM845 SoCs. Say Y if you want to control
134	  reset signals provided by AOSS for Modem, Venus, ADSP,
135	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
136
137config RESET_QCOM_PDC
138	tristate "Qualcomm PDC Reset Driver"
139	depends on ARCH_QCOM || COMPILE_TEST
140	help
141	  This enables the PDC (Power Domain Controller) reset driver
142	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
143	  to control reset signals provided by PDC for Modem, Compute,
144	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
145
146config RESET_RASPBERRYPI
147	tristate "Raspberry Pi 4 Firmware Reset Driver"
148	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
149	default USB_XHCI_PCI
150	help
151	  Raspberry Pi 4's co-processor controls some of the board's HW
152	  initialization process, but it's up to Linux to trigger it when
153	  relevant. This driver provides a reset controller capable of
154	  interfacing with RPi4's co-processor and model these firmware
155	  initialization routines as reset lines.
156
157config RESET_SCMI
158	tristate "Reset driver controlled via ARM SCMI interface"
159	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
160	default ARM_SCMI_PROTOCOL
161	help
162	  This driver provides support for reset signal/domains that are
163	  controlled by firmware that implements the SCMI interface.
164
165	  This driver uses SCMI Message Protocol to interact with the
166	  firmware controlling all the reset signals.
167
168config RESET_SIMPLE
169	bool "Simple Reset Controller Driver" if COMPILE_TEST
170	default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
171	help
172	  This enables a simple reset controller driver for reset lines that
173	  that can be asserted and deasserted by toggling bits in a contiguous,
174	  exclusive register space.
175
176	  Currently this driver supports:
177	   - Altera SoCFPGAs
178	   - ASPEED BMC SoCs
179	   - Bitmain BM1880 SoC
180	   - Realtek SoCs
181	   - RCC reset controller in STM32 MCUs
182	   - Allwinner SoCs
183	   - ZTE's zx2967 family
184
185config RESET_STM32MP157
186	bool "STM32MP157 Reset Driver" if COMPILE_TEST
187	default MACH_STM32MP157
188	help
189	  This enables the RCC reset controller driver for STM32 MPUs.
190
191config RESET_SOCFPGA
192	bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
193	default ARCH_SOCFPGA
194	select RESET_SIMPLE
195	help
196	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
197	  driver gets initialized early during platform init calls.
198
199config RESET_SUNXI
200	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
201	default ARCH_SUNXI
202	select RESET_SIMPLE
203	help
204	  This enables the reset driver for Allwinner SoCs.
205
206config RESET_TI_SCI
207	tristate "TI System Control Interface (TI-SCI) reset driver"
208	depends on TI_SCI_PROTOCOL
209	help
210	  This enables the reset driver support over TI System Control Interface
211	  available on some new TI's SoCs. If you wish to use reset resources
212	  managed by the TI System Controller, say Y here. Otherwise, say N.
213
214config RESET_TI_SYSCON
215	tristate "TI SYSCON Reset Driver"
216	depends on HAS_IOMEM
217	select MFD_SYSCON
218	help
219	  This enables the reset driver support for TI devices with
220	  memory-mapped reset registers as part of a syscon device node. If
221	  you wish to use the reset framework for such memory-mapped devices,
222	  say Y here. Otherwise, say N.
223
224config RESET_UNIPHIER
225	tristate "Reset controller driver for UniPhier SoCs"
226	depends on ARCH_UNIPHIER || COMPILE_TEST
227	depends on OF && MFD_SYSCON
228	default ARCH_UNIPHIER
229	help
230	  Support for reset controllers on UniPhier SoCs.
231	  Say Y if you want to control reset signals provided by System Control
232	  block, Media I/O block, Peripheral Block.
233
234config RESET_UNIPHIER_GLUE
235	tristate "Reset driver in glue layer for UniPhier SoCs"
236	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
237	default ARCH_UNIPHIER
238	select RESET_SIMPLE
239	help
240	  Support for peripheral core reset included in its own glue layer
241	  on UniPhier SoCs. Say Y if you want to control reset signals
242	  provided by the glue layer.
243
244config RESET_ZYNQ
245	bool "ZYNQ Reset Driver" if COMPILE_TEST
246	default ARCH_ZYNQ
247	help
248	  This enables the reset controller driver for Xilinx Zynq SoCs.
249
250source "drivers/reset/sti/Kconfig"
251source "drivers/reset/hisilicon/Kconfig"
252source "drivers/reset/tegra/Kconfig"
253
254endif
255