1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/device.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/serial.h>
31 #include <linux/clk.h>
32 #include <linux/slab.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/scatterlist.h>
36 #include <linux/delay.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
42 #include <linux/io.h>
43 #include <linux/acpi.h>
44
45 #include "amba-pl011.h"
46
47 #define UART_NR 14
48
49 #define SERIAL_AMBA_MAJOR 204
50 #define SERIAL_AMBA_MINOR 64
51 #define SERIAL_AMBA_NR UART_NR
52
53 #define AMBA_ISR_PASS_LIMIT 256
54
55 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
56 #define UART_DUMMY_DR_RX (1 << 16)
57
58 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
59 [REG_DR] = UART01x_DR,
60 [REG_FR] = UART01x_FR,
61 [REG_LCRH_RX] = UART011_LCRH,
62 [REG_LCRH_TX] = UART011_LCRH,
63 [REG_IBRD] = UART011_IBRD,
64 [REG_FBRD] = UART011_FBRD,
65 [REG_CR] = UART011_CR,
66 [REG_IFLS] = UART011_IFLS,
67 [REG_IMSC] = UART011_IMSC,
68 [REG_RIS] = UART011_RIS,
69 [REG_MIS] = UART011_MIS,
70 [REG_ICR] = UART011_ICR,
71 [REG_DMACR] = UART011_DMACR,
72 };
73
74 /* There is by now at least one vendor with differing details, so handle it */
75 struct vendor_data {
76 const u16 *reg_offset;
77 unsigned int ifls;
78 unsigned int fr_busy;
79 unsigned int fr_dsr;
80 unsigned int fr_cts;
81 unsigned int fr_ri;
82 unsigned int inv_fr;
83 bool access_32b;
84 bool oversampling;
85 bool dma_threshold;
86 bool cts_event_workaround;
87 bool always_enabled;
88 bool fixed_options;
89
90 unsigned int (*get_fifosize)(struct amba_device *dev);
91 };
92
get_fifosize_arm(struct amba_device * dev)93 static unsigned int get_fifosize_arm(struct amba_device *dev)
94 {
95 return amba_rev(dev) < 3 ? 16 : 32;
96 }
97
98 static struct vendor_data vendor_arm = {
99 .reg_offset = pl011_std_offsets,
100 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
101 .fr_busy = UART01x_FR_BUSY,
102 .fr_dsr = UART01x_FR_DSR,
103 .fr_cts = UART01x_FR_CTS,
104 .fr_ri = UART011_FR_RI,
105 .oversampling = false,
106 .dma_threshold = false,
107 .cts_event_workaround = false,
108 .always_enabled = false,
109 .fixed_options = false,
110 .get_fifosize = get_fifosize_arm,
111 };
112
113 static const struct vendor_data vendor_sbsa = {
114 .reg_offset = pl011_std_offsets,
115 .fr_busy = UART01x_FR_BUSY,
116 .fr_dsr = UART01x_FR_DSR,
117 .fr_cts = UART01x_FR_CTS,
118 .fr_ri = UART011_FR_RI,
119 .access_32b = true,
120 .oversampling = false,
121 .dma_threshold = false,
122 .cts_event_workaround = false,
123 .always_enabled = true,
124 .fixed_options = true,
125 };
126
127 #ifdef CONFIG_ACPI_SPCR_TABLE
128 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
129 .reg_offset = pl011_std_offsets,
130 .fr_busy = UART011_FR_TXFE,
131 .fr_dsr = UART01x_FR_DSR,
132 .fr_cts = UART01x_FR_CTS,
133 .fr_ri = UART011_FR_RI,
134 .inv_fr = UART011_FR_TXFE,
135 .access_32b = true,
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
141 };
142 #endif
143
144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169 };
170
get_fifosize_st(struct amba_device * dev)171 static unsigned int get_fifosize_st(struct amba_device *dev)
172 {
173 return 64;
174 }
175
176 static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
189 };
190
191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205 };
206
get_fifosize_zte(struct amba_device * dev)207 static unsigned int get_fifosize_zte(struct amba_device *dev)
208 {
209 return 16;
210 }
211
212 static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
221 };
222
223 /* Deals with DMA transactions */
224
225 struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228 };
229
230 struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
244 };
245
246 struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251 };
252
253 /*
254 * We wrap our port structure around the generic uart_port.
255 */
256 struct uart_amba_port {
257 struct uart_port port;
258 const u16 *reg_offset;
259 struct clk *clk;
260 const struct vendor_data *vendor;
261 unsigned int dmacr; /* dma control reg */
262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
264 unsigned int fifosize; /* vendor-specific */
265 unsigned int old_cr; /* state during shutdown */
266 unsigned int fixed_baud; /* vendor-set fixed baud rate */
267 char type[12];
268 #ifdef CONFIG_DMA_ENGINE
269 /* DMA stuff */
270 bool using_tx_dma;
271 bool using_rx_dma;
272 struct pl011_dmarx_data dmarx;
273 struct pl011_dmatx_data dmatx;
274 bool dma_probed;
275 #endif
276 };
277
pl011_reg_to_offset(const struct uart_amba_port * uap,unsigned int reg)278 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
279 unsigned int reg)
280 {
281 return uap->reg_offset[reg];
282 }
283
pl011_read(const struct uart_amba_port * uap,unsigned int reg)284 static unsigned int pl011_read(const struct uart_amba_port *uap,
285 unsigned int reg)
286 {
287 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
288
289 return (uap->port.iotype == UPIO_MEM32) ?
290 readl_relaxed(addr) : readw_relaxed(addr);
291 }
292
pl011_write(unsigned int val,const struct uart_amba_port * uap,unsigned int reg)293 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
294 unsigned int reg)
295 {
296 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
297
298 if (uap->port.iotype == UPIO_MEM32)
299 writel_relaxed(val, addr);
300 else
301 writew_relaxed(val, addr);
302 }
303
304 /*
305 * Reads up to 256 characters from the FIFO or until it's empty and
306 * inserts them into the TTY layer. Returns the number of characters
307 * read from the FIFO.
308 */
pl011_fifo_to_tty(struct uart_amba_port * uap)309 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
310 {
311 unsigned int ch, flag, fifotaken;
312 int sysrq;
313 u16 status;
314
315 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
316 status = pl011_read(uap, REG_FR);
317 if (status & UART01x_FR_RXFE)
318 break;
319
320 /* Take chars from the FIFO and update status */
321 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
322 flag = TTY_NORMAL;
323 uap->port.icount.rx++;
324
325 if (unlikely(ch & UART_DR_ERROR)) {
326 if (ch & UART011_DR_BE) {
327 ch &= ~(UART011_DR_FE | UART011_DR_PE);
328 uap->port.icount.brk++;
329 if (uart_handle_break(&uap->port))
330 continue;
331 } else if (ch & UART011_DR_PE)
332 uap->port.icount.parity++;
333 else if (ch & UART011_DR_FE)
334 uap->port.icount.frame++;
335 if (ch & UART011_DR_OE)
336 uap->port.icount.overrun++;
337
338 ch &= uap->port.read_status_mask;
339
340 if (ch & UART011_DR_BE)
341 flag = TTY_BREAK;
342 else if (ch & UART011_DR_PE)
343 flag = TTY_PARITY;
344 else if (ch & UART011_DR_FE)
345 flag = TTY_FRAME;
346 }
347
348 spin_unlock(&uap->port.lock);
349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
350 spin_lock(&uap->port.lock);
351
352 if (!sysrq)
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
354 }
355
356 return fifotaken;
357 }
358
359
360 /*
361 * All the DMA operation mode stuff goes inside this ifdef.
362 * This assumes that you have a generic DMA device interface,
363 * no custom DMA interfaces are supported.
364 */
365 #ifdef CONFIG_DMA_ENGINE
366
367 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
368
pl011_sgbuf_init(struct dma_chan * chan,struct pl011_sgbuf * sg,enum dma_data_direction dir)369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
370 enum dma_data_direction dir)
371 {
372 dma_addr_t dma_addr;
373
374 sg->buf = dma_alloc_coherent(chan->device->dev,
375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
376 if (!sg->buf)
377 return -ENOMEM;
378
379 sg_init_table(&sg->sg, 1);
380 sg_set_page(&sg->sg, phys_to_page(dma_addr),
381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
382 sg_dma_address(&sg->sg) = dma_addr;
383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
384
385 return 0;
386 }
387
pl011_sgbuf_free(struct dma_chan * chan,struct pl011_sgbuf * sg,enum dma_data_direction dir)388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
389 enum dma_data_direction dir)
390 {
391 if (sg->buf) {
392 dma_free_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, sg->buf,
394 sg_dma_address(&sg->sg));
395 }
396 }
397
pl011_dma_probe(struct uart_amba_port * uap)398 static void pl011_dma_probe(struct uart_amba_port *uap)
399 {
400 /* DMA is the sole user of the platform data right now */
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
402 struct device *dev = uap->port.dev;
403 struct dma_slave_config tx_conf = {
404 .dst_addr = uap->port.mapbase +
405 pl011_reg_to_offset(uap, REG_DR),
406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
407 .direction = DMA_MEM_TO_DEV,
408 .dst_maxburst = uap->fifosize >> 1,
409 .device_fc = false,
410 };
411 struct dma_chan *chan;
412 dma_cap_mask_t mask;
413
414 uap->dma_probed = true;
415 chan = dma_request_chan(dev, "tx");
416 if (IS_ERR(chan)) {
417 if (PTR_ERR(chan) == -EPROBE_DEFER) {
418 uap->dma_probed = false;
419 return;
420 }
421
422 /* We need platform data */
423 if (!plat || !plat->dma_filter) {
424 dev_info(uap->port.dev, "no DMA platform data\n");
425 return;
426 }
427
428 /* Try to acquire a generic DMA engine slave TX channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 chan = dma_request_channel(mask, plat->dma_filter,
433 plat->dma_tx_param);
434 if (!chan) {
435 dev_err(uap->port.dev, "no TX DMA channel!\n");
436 return;
437 }
438 }
439
440 dmaengine_slave_config(chan, &tx_conf);
441 uap->dmatx.chan = chan;
442
443 dev_info(uap->port.dev, "DMA channel TX %s\n",
444 dma_chan_name(uap->dmatx.chan));
445
446 /* Optionally make use of an RX channel as well */
447 chan = dma_request_slave_channel(dev, "rx");
448
449 if (!chan && plat && plat->dma_rx_param) {
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
451
452 if (!chan) {
453 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 return;
455 }
456 }
457
458 if (chan) {
459 struct dma_slave_config rx_conf = {
460 .src_addr = uap->port.mapbase +
461 pl011_reg_to_offset(uap, REG_DR),
462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
463 .direction = DMA_DEV_TO_MEM,
464 .src_maxburst = uap->fifosize >> 2,
465 .device_fc = false,
466 };
467 struct dma_slave_caps caps;
468
469 /*
470 * Some DMA controllers provide information on their capabilities.
471 * If the controller does, check for suitable residue processing
472 * otherwise assime all is well.
473 */
474 if (0 == dma_get_slave_caps(chan, &caps)) {
475 if (caps.residue_granularity ==
476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
477 dma_release_channel(chan);
478 dev_info(uap->port.dev,
479 "RX DMA disabled - no residue processing\n");
480 return;
481 }
482 }
483 dmaengine_slave_config(chan, &rx_conf);
484 uap->dmarx.chan = chan;
485
486 uap->dmarx.auto_poll_rate = false;
487 if (plat && plat->dma_rx_poll_enable) {
488 /* Set poll rate if specified. */
489 if (plat->dma_rx_poll_rate) {
490 uap->dmarx.auto_poll_rate = false;
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 } else {
493 /*
494 * 100 ms defaults to poll rate if not
495 * specified. This will be adjusted with
496 * the baud rate at set_termios.
497 */
498 uap->dmarx.auto_poll_rate = true;
499 uap->dmarx.poll_rate = 100;
500 }
501 /* 3 secs defaults poll_timeout if not specified. */
502 if (plat->dma_rx_poll_timeout)
503 uap->dmarx.poll_timeout =
504 plat->dma_rx_poll_timeout;
505 else
506 uap->dmarx.poll_timeout = 3000;
507 } else if (!plat && dev->of_node) {
508 uap->dmarx.auto_poll_rate = of_property_read_bool(
509 dev->of_node, "auto-poll");
510 if (uap->dmarx.auto_poll_rate) {
511 u32 x;
512
513 if (0 == of_property_read_u32(dev->of_node,
514 "poll-rate-ms", &x))
515 uap->dmarx.poll_rate = x;
516 else
517 uap->dmarx.poll_rate = 100;
518 if (0 == of_property_read_u32(dev->of_node,
519 "poll-timeout-ms", &x))
520 uap->dmarx.poll_timeout = x;
521 else
522 uap->dmarx.poll_timeout = 3000;
523 }
524 }
525 dev_info(uap->port.dev, "DMA channel RX %s\n",
526 dma_chan_name(uap->dmarx.chan));
527 }
528 }
529
pl011_dma_remove(struct uart_amba_port * uap)530 static void pl011_dma_remove(struct uart_amba_port *uap)
531 {
532 if (uap->dmatx.chan)
533 dma_release_channel(uap->dmatx.chan);
534 if (uap->dmarx.chan)
535 dma_release_channel(uap->dmarx.chan);
536 }
537
538 /* Forward declare these for the refill routine */
539 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
540 static void pl011_start_tx_pio(struct uart_amba_port *uap);
541
542 /*
543 * The current DMA TX buffer has been sent.
544 * Try to queue up another DMA buffer.
545 */
pl011_dma_tx_callback(void * data)546 static void pl011_dma_tx_callback(void *data)
547 {
548 struct uart_amba_port *uap = data;
549 struct pl011_dmatx_data *dmatx = &uap->dmatx;
550 unsigned long flags;
551 u16 dmacr;
552
553 spin_lock_irqsave(&uap->port.lock, flags);
554 if (uap->dmatx.queued)
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
556 DMA_TO_DEVICE);
557
558 dmacr = uap->dmacr;
559 uap->dmacr = dmacr & ~UART011_TXDMAE;
560 pl011_write(uap->dmacr, uap, REG_DMACR);
561
562 /*
563 * If TX DMA was disabled, it means that we've stopped the DMA for
564 * some reason (eg, XOFF received, or we want to send an X-char.)
565 *
566 * Note: we need to be careful here of a potential race between DMA
567 * and the rest of the driver - if the driver disables TX DMA while
568 * a TX buffer completing, we must update the tx queued status to
569 * get further refills (hence we check dmacr).
570 */
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
572 uart_circ_empty(&uap->port.state->xmit)) {
573 uap->dmatx.queued = false;
574 spin_unlock_irqrestore(&uap->port.lock, flags);
575 return;
576 }
577
578 if (pl011_dma_tx_refill(uap) <= 0)
579 /*
580 * We didn't queue a DMA buffer for some reason, but we
581 * have data pending to be sent. Re-enable the TX IRQ.
582 */
583 pl011_start_tx_pio(uap);
584
585 spin_unlock_irqrestore(&uap->port.lock, flags);
586 }
587
588 /*
589 * Try to refill the TX DMA buffer.
590 * Locking: called with port lock held and IRQs disabled.
591 * Returns:
592 * 1 if we queued up a TX DMA buffer.
593 * 0 if we didn't want to handle this by DMA
594 * <0 on error
595 */
pl011_dma_tx_refill(struct uart_amba_port * uap)596 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
597 {
598 struct pl011_dmatx_data *dmatx = &uap->dmatx;
599 struct dma_chan *chan = dmatx->chan;
600 struct dma_device *dma_dev = chan->device;
601 struct dma_async_tx_descriptor *desc;
602 struct circ_buf *xmit = &uap->port.state->xmit;
603 unsigned int count;
604
605 /*
606 * Try to avoid the overhead involved in using DMA if the
607 * transaction fits in the first half of the FIFO, by using
608 * the standard interrupt handling. This ensures that we
609 * issue a uart_write_wakeup() at the appropriate time.
610 */
611 count = uart_circ_chars_pending(xmit);
612 if (count < (uap->fifosize >> 1)) {
613 uap->dmatx.queued = false;
614 return 0;
615 }
616
617 /*
618 * Bodge: don't send the last character by DMA, as this
619 * will prevent XON from notifying us to restart DMA.
620 */
621 count -= 1;
622
623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
624 if (count > PL011_DMA_BUFFER_SIZE)
625 count = PL011_DMA_BUFFER_SIZE;
626
627 if (xmit->tail < xmit->head)
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
629 else {
630 size_t first = UART_XMIT_SIZE - xmit->tail;
631 size_t second;
632
633 if (first > count)
634 first = count;
635 second = count - first;
636
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
638 if (second)
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
640 }
641
642 dmatx->sg.length = count;
643
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
645 uap->dmatx.queued = false;
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
647 return -EBUSY;
648 }
649
650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
652 if (!desc) {
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
654 uap->dmatx.queued = false;
655 /*
656 * If DMA cannot be used right now, we complete this
657 * transaction via IRQ and let the TTY layer retry.
658 */
659 dev_dbg(uap->port.dev, "TX DMA busy\n");
660 return -EBUSY;
661 }
662
663 /* Some data to go along to the callback */
664 desc->callback = pl011_dma_tx_callback;
665 desc->callback_param = uap;
666
667 /* All errors should happen at prepare time */
668 dmaengine_submit(desc);
669
670 /* Fire the DMA transaction */
671 dma_dev->device_issue_pending(chan);
672
673 uap->dmacr |= UART011_TXDMAE;
674 pl011_write(uap->dmacr, uap, REG_DMACR);
675 uap->dmatx.queued = true;
676
677 /*
678 * Now we know that DMA will fire, so advance the ring buffer
679 * with the stuff we just dispatched.
680 */
681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
682 uap->port.icount.tx += count;
683
684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
685 uart_write_wakeup(&uap->port);
686
687 return 1;
688 }
689
690 /*
691 * We received a transmit interrupt without a pending X-char but with
692 * pending characters.
693 * Locking: called with port lock held and IRQs disabled.
694 * Returns:
695 * false if we want to use PIO to transmit
696 * true if we queued a DMA buffer
697 */
pl011_dma_tx_irq(struct uart_amba_port * uap)698 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
699 {
700 if (!uap->using_tx_dma)
701 return false;
702
703 /*
704 * If we already have a TX buffer queued, but received a
705 * TX interrupt, it will be because we've just sent an X-char.
706 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
707 */
708 if (uap->dmatx.queued) {
709 uap->dmacr |= UART011_TXDMAE;
710 pl011_write(uap->dmacr, uap, REG_DMACR);
711 uap->im &= ~UART011_TXIM;
712 pl011_write(uap->im, uap, REG_IMSC);
713 return true;
714 }
715
716 /*
717 * We don't have a TX buffer queued, so try to queue one.
718 * If we successfully queued a buffer, mask the TX IRQ.
719 */
720 if (pl011_dma_tx_refill(uap) > 0) {
721 uap->im &= ~UART011_TXIM;
722 pl011_write(uap->im, uap, REG_IMSC);
723 return true;
724 }
725 return false;
726 }
727
728 /*
729 * Stop the DMA transmit (eg, due to received XOFF).
730 * Locking: called with port lock held and IRQs disabled.
731 */
pl011_dma_tx_stop(struct uart_amba_port * uap)732 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
733 {
734 if (uap->dmatx.queued) {
735 uap->dmacr &= ~UART011_TXDMAE;
736 pl011_write(uap->dmacr, uap, REG_DMACR);
737 }
738 }
739
740 /*
741 * Try to start a DMA transmit, or in the case of an XON/OFF
742 * character queued for send, try to get that character out ASAP.
743 * Locking: called with port lock held and IRQs disabled.
744 * Returns:
745 * false if we want the TX IRQ to be enabled
746 * true if we have a buffer queued
747 */
pl011_dma_tx_start(struct uart_amba_port * uap)748 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
749 {
750 u16 dmacr;
751
752 if (!uap->using_tx_dma)
753 return false;
754
755 if (!uap->port.x_char) {
756 /* no X-char, try to push chars out in DMA mode */
757 bool ret = true;
758
759 if (!uap->dmatx.queued) {
760 if (pl011_dma_tx_refill(uap) > 0) {
761 uap->im &= ~UART011_TXIM;
762 pl011_write(uap->im, uap, REG_IMSC);
763 } else
764 ret = false;
765 } else if (!(uap->dmacr & UART011_TXDMAE)) {
766 uap->dmacr |= UART011_TXDMAE;
767 pl011_write(uap->dmacr, uap, REG_DMACR);
768 }
769 return ret;
770 }
771
772 /*
773 * We have an X-char to send. Disable DMA to prevent it loading
774 * the TX fifo, and then see if we can stuff it into the FIFO.
775 */
776 dmacr = uap->dmacr;
777 uap->dmacr &= ~UART011_TXDMAE;
778 pl011_write(uap->dmacr, uap, REG_DMACR);
779
780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
781 /*
782 * No space in the FIFO, so enable the transmit interrupt
783 * so we know when there is space. Note that once we've
784 * loaded the character, we should just re-enable DMA.
785 */
786 return false;
787 }
788
789 pl011_write(uap->port.x_char, uap, REG_DR);
790 uap->port.icount.tx++;
791 uap->port.x_char = 0;
792
793 /* Success - restore the DMA state */
794 uap->dmacr = dmacr;
795 pl011_write(dmacr, uap, REG_DMACR);
796
797 return true;
798 }
799
800 /*
801 * Flush the transmit buffer.
802 * Locking: called with port lock held and IRQs disabled.
803 */
pl011_dma_flush_buffer(struct uart_port * port)804 static void pl011_dma_flush_buffer(struct uart_port *port)
805 __releases(&uap->port.lock)
806 __acquires(&uap->port.lock)
807 {
808 struct uart_amba_port *uap =
809 container_of(port, struct uart_amba_port, port);
810
811 if (!uap->using_tx_dma)
812 return;
813
814 dmaengine_terminate_async(uap->dmatx.chan);
815
816 if (uap->dmatx.queued) {
817 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
818 DMA_TO_DEVICE);
819 uap->dmatx.queued = false;
820 uap->dmacr &= ~UART011_TXDMAE;
821 pl011_write(uap->dmacr, uap, REG_DMACR);
822 }
823 }
824
825 static void pl011_dma_rx_callback(void *data);
826
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)827 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
828 {
829 struct dma_chan *rxchan = uap->dmarx.chan;
830 struct pl011_dmarx_data *dmarx = &uap->dmarx;
831 struct dma_async_tx_descriptor *desc;
832 struct pl011_sgbuf *sgbuf;
833
834 if (!rxchan)
835 return -EIO;
836
837 /* Start the RX DMA job */
838 sgbuf = uap->dmarx.use_buf_b ?
839 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
840 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
841 DMA_DEV_TO_MEM,
842 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
843 /*
844 * If the DMA engine is busy and cannot prepare a
845 * channel, no big deal, the driver will fall back
846 * to interrupt mode as a result of this error code.
847 */
848 if (!desc) {
849 uap->dmarx.running = false;
850 dmaengine_terminate_all(rxchan);
851 return -EBUSY;
852 }
853
854 /* Some data to go along to the callback */
855 desc->callback = pl011_dma_rx_callback;
856 desc->callback_param = uap;
857 dmarx->cookie = dmaengine_submit(desc);
858 dma_async_issue_pending(rxchan);
859
860 uap->dmacr |= UART011_RXDMAE;
861 pl011_write(uap->dmacr, uap, REG_DMACR);
862 uap->dmarx.running = true;
863
864 uap->im &= ~UART011_RXIM;
865 pl011_write(uap->im, uap, REG_IMSC);
866
867 return 0;
868 }
869
870 /*
871 * This is called when either the DMA job is complete, or
872 * the FIFO timeout interrupt occurred. This must be called
873 * with the port spinlock uap->port.lock held.
874 */
pl011_dma_rx_chars(struct uart_amba_port * uap,u32 pending,bool use_buf_b,bool readfifo)875 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
876 u32 pending, bool use_buf_b,
877 bool readfifo)
878 {
879 struct tty_port *port = &uap->port.state->port;
880 struct pl011_sgbuf *sgbuf = use_buf_b ?
881 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
882 int dma_count = 0;
883 u32 fifotaken = 0; /* only used for vdbg() */
884
885 struct pl011_dmarx_data *dmarx = &uap->dmarx;
886 int dmataken = 0;
887
888 if (uap->dmarx.poll_rate) {
889 /* The data can be taken by polling */
890 dmataken = sgbuf->sg.length - dmarx->last_residue;
891 /* Recalculate the pending size */
892 if (pending >= dmataken)
893 pending -= dmataken;
894 }
895
896 /* Pick the remain data from the DMA */
897 if (pending) {
898
899 /*
900 * First take all chars in the DMA pipe, then look in the FIFO.
901 * Note that tty_insert_flip_buf() tries to take as many chars
902 * as it can.
903 */
904 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
905 pending);
906
907 uap->port.icount.rx += dma_count;
908 if (dma_count < pending)
909 dev_warn(uap->port.dev,
910 "couldn't insert all characters (TTY is full?)\n");
911 }
912
913 /* Reset the last_residue for Rx DMA poll */
914 if (uap->dmarx.poll_rate)
915 dmarx->last_residue = sgbuf->sg.length;
916
917 /*
918 * Only continue with trying to read the FIFO if all DMA chars have
919 * been taken first.
920 */
921 if (dma_count == pending && readfifo) {
922 /* Clear any error flags */
923 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
924 UART011_FEIS, uap, REG_ICR);
925
926 /*
927 * If we read all the DMA'd characters, and we had an
928 * incomplete buffer, that could be due to an rx error, or
929 * maybe we just timed out. Read any pending chars and check
930 * the error status.
931 *
932 * Error conditions will only occur in the FIFO, these will
933 * trigger an immediate interrupt and stop the DMA job, so we
934 * will always find the error in the FIFO, never in the DMA
935 * buffer.
936 */
937 fifotaken = pl011_fifo_to_tty(uap);
938 }
939
940 spin_unlock(&uap->port.lock);
941 dev_vdbg(uap->port.dev,
942 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
943 dma_count, fifotaken);
944 tty_flip_buffer_push(port);
945 spin_lock(&uap->port.lock);
946 }
947
pl011_dma_rx_irq(struct uart_amba_port * uap)948 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
949 {
950 struct pl011_dmarx_data *dmarx = &uap->dmarx;
951 struct dma_chan *rxchan = dmarx->chan;
952 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
953 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
954 size_t pending;
955 struct dma_tx_state state;
956 enum dma_status dmastat;
957
958 /*
959 * Pause the transfer so we can trust the current counter,
960 * do this before we pause the PL011 block, else we may
961 * overflow the FIFO.
962 */
963 if (dmaengine_pause(rxchan))
964 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
965 dmastat = rxchan->device->device_tx_status(rxchan,
966 dmarx->cookie, &state);
967 if (dmastat != DMA_PAUSED)
968 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
969
970 /* Disable RX DMA - incoming data will wait in the FIFO */
971 uap->dmacr &= ~UART011_RXDMAE;
972 pl011_write(uap->dmacr, uap, REG_DMACR);
973 uap->dmarx.running = false;
974
975 pending = sgbuf->sg.length - state.residue;
976 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
977 /* Then we terminate the transfer - we now know our residue */
978 dmaengine_terminate_all(rxchan);
979
980 /*
981 * This will take the chars we have so far and insert
982 * into the framework.
983 */
984 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
985
986 /* Switch buffer & re-trigger DMA job */
987 dmarx->use_buf_b = !dmarx->use_buf_b;
988 if (pl011_dma_rx_trigger_dma(uap)) {
989 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
990 "fall back to interrupt mode\n");
991 uap->im |= UART011_RXIM;
992 pl011_write(uap->im, uap, REG_IMSC);
993 }
994 }
995
pl011_dma_rx_callback(void * data)996 static void pl011_dma_rx_callback(void *data)
997 {
998 struct uart_amba_port *uap = data;
999 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1000 struct dma_chan *rxchan = dmarx->chan;
1001 bool lastbuf = dmarx->use_buf_b;
1002 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1003 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1004 size_t pending;
1005 struct dma_tx_state state;
1006 int ret;
1007
1008 /*
1009 * This completion interrupt occurs typically when the
1010 * RX buffer is totally stuffed but no timeout has yet
1011 * occurred. When that happens, we just want the RX
1012 * routine to flush out the secondary DMA buffer while
1013 * we immediately trigger the next DMA job.
1014 */
1015 spin_lock_irq(&uap->port.lock);
1016 /*
1017 * Rx data can be taken by the UART interrupts during
1018 * the DMA irq handler. So we check the residue here.
1019 */
1020 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1021 pending = sgbuf->sg.length - state.residue;
1022 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1023 /* Then we terminate the transfer - we now know our residue */
1024 dmaengine_terminate_all(rxchan);
1025
1026 uap->dmarx.running = false;
1027 dmarx->use_buf_b = !lastbuf;
1028 ret = pl011_dma_rx_trigger_dma(uap);
1029
1030 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1031 spin_unlock_irq(&uap->port.lock);
1032 /*
1033 * Do this check after we picked the DMA chars so we don't
1034 * get some IRQ immediately from RX.
1035 */
1036 if (ret) {
1037 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1038 "fall back to interrupt mode\n");
1039 uap->im |= UART011_RXIM;
1040 pl011_write(uap->im, uap, REG_IMSC);
1041 }
1042 }
1043
1044 /*
1045 * Stop accepting received characters, when we're shutting down or
1046 * suspending this port.
1047 * Locking: called with port lock held and IRQs disabled.
1048 */
pl011_dma_rx_stop(struct uart_amba_port * uap)1049 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1050 {
1051 if (!uap->using_rx_dma)
1052 return;
1053
1054 /* FIXME. Just disable the DMA enable */
1055 uap->dmacr &= ~UART011_RXDMAE;
1056 pl011_write(uap->dmacr, uap, REG_DMACR);
1057 }
1058
1059 /*
1060 * Timer handler for Rx DMA polling.
1061 * Every polling, It checks the residue in the dma buffer and transfer
1062 * data to the tty. Also, last_residue is updated for the next polling.
1063 */
pl011_dma_rx_poll(struct timer_list * t)1064 static void pl011_dma_rx_poll(struct timer_list *t)
1065 {
1066 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1067 struct tty_port *port = &uap->port.state->port;
1068 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1069 struct dma_chan *rxchan = uap->dmarx.chan;
1070 unsigned long flags = 0;
1071 unsigned int dmataken = 0;
1072 unsigned int size = 0;
1073 struct pl011_sgbuf *sgbuf;
1074 int dma_count;
1075 struct dma_tx_state state;
1076
1077 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1078 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1079 if (likely(state.residue < dmarx->last_residue)) {
1080 dmataken = sgbuf->sg.length - dmarx->last_residue;
1081 size = dmarx->last_residue - state.residue;
1082 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1083 size);
1084 if (dma_count == size)
1085 dmarx->last_residue = state.residue;
1086 dmarx->last_jiffies = jiffies;
1087 }
1088 tty_flip_buffer_push(port);
1089
1090 /*
1091 * If no data is received in poll_timeout, the driver will fall back
1092 * to interrupt mode. We will retrigger DMA at the first interrupt.
1093 */
1094 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1095 > uap->dmarx.poll_timeout) {
1096
1097 spin_lock_irqsave(&uap->port.lock, flags);
1098 pl011_dma_rx_stop(uap);
1099 uap->im |= UART011_RXIM;
1100 pl011_write(uap->im, uap, REG_IMSC);
1101 spin_unlock_irqrestore(&uap->port.lock, flags);
1102
1103 uap->dmarx.running = false;
1104 dmaengine_terminate_all(rxchan);
1105 del_timer(&uap->dmarx.timer);
1106 } else {
1107 mod_timer(&uap->dmarx.timer,
1108 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1109 }
1110 }
1111
pl011_dma_startup(struct uart_amba_port * uap)1112 static void pl011_dma_startup(struct uart_amba_port *uap)
1113 {
1114 int ret;
1115
1116 if (!uap->dma_probed)
1117 pl011_dma_probe(uap);
1118
1119 if (!uap->dmatx.chan)
1120 return;
1121
1122 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1123 if (!uap->dmatx.buf) {
1124 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1125 uap->port.fifosize = uap->fifosize;
1126 return;
1127 }
1128
1129 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1130
1131 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1132 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1133 uap->using_tx_dma = true;
1134
1135 if (!uap->dmarx.chan)
1136 goto skip_rx;
1137
1138 /* Allocate and map DMA RX buffers */
1139 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1140 DMA_FROM_DEVICE);
1141 if (ret) {
1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1143 "RX buffer A", ret);
1144 goto skip_rx;
1145 }
1146
1147 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1148 DMA_FROM_DEVICE);
1149 if (ret) {
1150 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1151 "RX buffer B", ret);
1152 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1153 DMA_FROM_DEVICE);
1154 goto skip_rx;
1155 }
1156
1157 uap->using_rx_dma = true;
1158
1159 skip_rx:
1160 /* Turn on DMA error (RX/TX will be enabled on demand) */
1161 uap->dmacr |= UART011_DMAONERR;
1162 pl011_write(uap->dmacr, uap, REG_DMACR);
1163
1164 /*
1165 * ST Micro variants has some specific dma burst threshold
1166 * compensation. Set this to 16 bytes, so burst will only
1167 * be issued above/below 16 bytes.
1168 */
1169 if (uap->vendor->dma_threshold)
1170 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1171 uap, REG_ST_DMAWM);
1172
1173 if (uap->using_rx_dma) {
1174 if (pl011_dma_rx_trigger_dma(uap))
1175 dev_dbg(uap->port.dev, "could not trigger initial "
1176 "RX DMA job, fall back to interrupt mode\n");
1177 if (uap->dmarx.poll_rate) {
1178 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1179 mod_timer(&uap->dmarx.timer,
1180 jiffies +
1181 msecs_to_jiffies(uap->dmarx.poll_rate));
1182 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1183 uap->dmarx.last_jiffies = jiffies;
1184 }
1185 }
1186 }
1187
pl011_dma_shutdown(struct uart_amba_port * uap)1188 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1189 {
1190 if (!(uap->using_tx_dma || uap->using_rx_dma))
1191 return;
1192
1193 /* Disable RX and TX DMA */
1194 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1195 cpu_relax();
1196
1197 spin_lock_irq(&uap->port.lock);
1198 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1199 pl011_write(uap->dmacr, uap, REG_DMACR);
1200 spin_unlock_irq(&uap->port.lock);
1201
1202 if (uap->using_tx_dma) {
1203 /* In theory, this should already be done by pl011_dma_flush_buffer */
1204 dmaengine_terminate_all(uap->dmatx.chan);
1205 if (uap->dmatx.queued) {
1206 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1207 DMA_TO_DEVICE);
1208 uap->dmatx.queued = false;
1209 }
1210
1211 kfree(uap->dmatx.buf);
1212 uap->using_tx_dma = false;
1213 }
1214
1215 if (uap->using_rx_dma) {
1216 dmaengine_terminate_all(uap->dmarx.chan);
1217 /* Clean up the RX DMA */
1218 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1220 if (uap->dmarx.poll_rate)
1221 del_timer_sync(&uap->dmarx.timer);
1222 uap->using_rx_dma = false;
1223 }
1224 }
1225
pl011_dma_rx_available(struct uart_amba_port * uap)1226 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1227 {
1228 return uap->using_rx_dma;
1229 }
1230
pl011_dma_rx_running(struct uart_amba_port * uap)1231 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1232 {
1233 return uap->using_rx_dma && uap->dmarx.running;
1234 }
1235
1236 #else
1237 /* Blank functions if the DMA engine is not available */
pl011_dma_remove(struct uart_amba_port * uap)1238 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1239 {
1240 }
1241
pl011_dma_startup(struct uart_amba_port * uap)1242 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1243 {
1244 }
1245
pl011_dma_shutdown(struct uart_amba_port * uap)1246 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1247 {
1248 }
1249
pl011_dma_tx_irq(struct uart_amba_port * uap)1250 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1251 {
1252 return false;
1253 }
1254
pl011_dma_tx_stop(struct uart_amba_port * uap)1255 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1256 {
1257 }
1258
pl011_dma_tx_start(struct uart_amba_port * uap)1259 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1260 {
1261 return false;
1262 }
1263
pl011_dma_rx_irq(struct uart_amba_port * uap)1264 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1265 {
1266 }
1267
pl011_dma_rx_stop(struct uart_amba_port * uap)1268 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1269 {
1270 }
1271
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)1272 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1273 {
1274 return -EIO;
1275 }
1276
pl011_dma_rx_available(struct uart_amba_port * uap)1277 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1278 {
1279 return false;
1280 }
1281
pl011_dma_rx_running(struct uart_amba_port * uap)1282 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1283 {
1284 return false;
1285 }
1286
1287 #define pl011_dma_flush_buffer NULL
1288 #endif
1289
pl011_stop_tx(struct uart_port * port)1290 static void pl011_stop_tx(struct uart_port *port)
1291 {
1292 struct uart_amba_port *uap =
1293 container_of(port, struct uart_amba_port, port);
1294
1295 uap->im &= ~UART011_TXIM;
1296 pl011_write(uap->im, uap, REG_IMSC);
1297 pl011_dma_tx_stop(uap);
1298 }
1299
1300 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1301
1302 /* Start TX with programmed I/O only (no DMA) */
pl011_start_tx_pio(struct uart_amba_port * uap)1303 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1304 {
1305 if (pl011_tx_chars(uap, false)) {
1306 uap->im |= UART011_TXIM;
1307 pl011_write(uap->im, uap, REG_IMSC);
1308 }
1309 }
1310
pl011_start_tx(struct uart_port * port)1311 static void pl011_start_tx(struct uart_port *port)
1312 {
1313 struct uart_amba_port *uap =
1314 container_of(port, struct uart_amba_port, port);
1315
1316 if (!pl011_dma_tx_start(uap))
1317 pl011_start_tx_pio(uap);
1318 }
1319
pl011_stop_rx(struct uart_port * port)1320 static void pl011_stop_rx(struct uart_port *port)
1321 {
1322 struct uart_amba_port *uap =
1323 container_of(port, struct uart_amba_port, port);
1324
1325 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1326 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1327 pl011_write(uap->im, uap, REG_IMSC);
1328
1329 pl011_dma_rx_stop(uap);
1330 }
1331
pl011_throttle_rx(struct uart_port * port)1332 static void pl011_throttle_rx(struct uart_port *port)
1333 {
1334 unsigned long flags;
1335
1336 spin_lock_irqsave(&port->lock, flags);
1337 pl011_stop_rx(port);
1338 spin_unlock_irqrestore(&port->lock, flags);
1339 }
1340
pl011_enable_ms(struct uart_port * port)1341 static void pl011_enable_ms(struct uart_port *port)
1342 {
1343 struct uart_amba_port *uap =
1344 container_of(port, struct uart_amba_port, port);
1345
1346 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1347 pl011_write(uap->im, uap, REG_IMSC);
1348 }
1349
pl011_rx_chars(struct uart_amba_port * uap)1350 static void pl011_rx_chars(struct uart_amba_port *uap)
1351 __releases(&uap->port.lock)
1352 __acquires(&uap->port.lock)
1353 {
1354 pl011_fifo_to_tty(uap);
1355
1356 spin_unlock(&uap->port.lock);
1357 tty_flip_buffer_push(&uap->port.state->port);
1358 /*
1359 * If we were temporarily out of DMA mode for a while,
1360 * attempt to switch back to DMA mode again.
1361 */
1362 if (pl011_dma_rx_available(uap)) {
1363 if (pl011_dma_rx_trigger_dma(uap)) {
1364 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1365 "fall back to interrupt mode again\n");
1366 uap->im |= UART011_RXIM;
1367 pl011_write(uap->im, uap, REG_IMSC);
1368 } else {
1369 #ifdef CONFIG_DMA_ENGINE
1370 /* Start Rx DMA poll */
1371 if (uap->dmarx.poll_rate) {
1372 uap->dmarx.last_jiffies = jiffies;
1373 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1374 mod_timer(&uap->dmarx.timer,
1375 jiffies +
1376 msecs_to_jiffies(uap->dmarx.poll_rate));
1377 }
1378 #endif
1379 }
1380 }
1381 spin_lock(&uap->port.lock);
1382 }
1383
pl011_tx_char(struct uart_amba_port * uap,unsigned char c,bool from_irq)1384 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1385 bool from_irq)
1386 {
1387 if (unlikely(!from_irq) &&
1388 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1389 return false; /* unable to transmit character */
1390
1391 pl011_write(c, uap, REG_DR);
1392 uap->port.icount.tx++;
1393
1394 return true;
1395 }
1396
1397 /* Returns true if tx interrupts have to be (kept) enabled */
pl011_tx_chars(struct uart_amba_port * uap,bool from_irq)1398 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1399 {
1400 struct circ_buf *xmit = &uap->port.state->xmit;
1401 int count = uap->fifosize >> 1;
1402
1403 if (uap->port.x_char) {
1404 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1405 return true;
1406 uap->port.x_char = 0;
1407 --count;
1408 }
1409 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1410 pl011_stop_tx(&uap->port);
1411 return false;
1412 }
1413
1414 /* If we are using DMA mode, try to send some characters. */
1415 if (pl011_dma_tx_irq(uap))
1416 return true;
1417
1418 do {
1419 if (likely(from_irq) && count-- == 0)
1420 break;
1421
1422 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1423 break;
1424
1425 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1426 } while (!uart_circ_empty(xmit));
1427
1428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1429 uart_write_wakeup(&uap->port);
1430
1431 if (uart_circ_empty(xmit)) {
1432 pl011_stop_tx(&uap->port);
1433 return false;
1434 }
1435 return true;
1436 }
1437
pl011_modem_status(struct uart_amba_port * uap)1438 static void pl011_modem_status(struct uart_amba_port *uap)
1439 {
1440 unsigned int status, delta;
1441
1442 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1443
1444 delta = status ^ uap->old_status;
1445 uap->old_status = status;
1446
1447 if (!delta)
1448 return;
1449
1450 if (delta & UART01x_FR_DCD)
1451 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1452
1453 if (delta & uap->vendor->fr_dsr)
1454 uap->port.icount.dsr++;
1455
1456 if (delta & uap->vendor->fr_cts)
1457 uart_handle_cts_change(&uap->port,
1458 status & uap->vendor->fr_cts);
1459
1460 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1461 }
1462
check_apply_cts_event_workaround(struct uart_amba_port * uap)1463 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1464 {
1465 if (!uap->vendor->cts_event_workaround)
1466 return;
1467
1468 /* workaround to make sure that all bits are unlocked.. */
1469 pl011_write(0x00, uap, REG_ICR);
1470
1471 /*
1472 * WA: introduce 26ns(1 uart clk) delay before W1C;
1473 * single apb access will incur 2 pclk(133.12Mhz) delay,
1474 * so add 2 dummy reads
1475 */
1476 pl011_read(uap, REG_ICR);
1477 pl011_read(uap, REG_ICR);
1478 }
1479
pl011_int(int irq,void * dev_id)1480 static irqreturn_t pl011_int(int irq, void *dev_id)
1481 {
1482 struct uart_amba_port *uap = dev_id;
1483 unsigned long flags;
1484 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1485 int handled = 0;
1486
1487 spin_lock_irqsave(&uap->port.lock, flags);
1488 status = pl011_read(uap, REG_RIS) & uap->im;
1489 if (status) {
1490 do {
1491 check_apply_cts_event_workaround(uap);
1492
1493 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1494 UART011_RXIS),
1495 uap, REG_ICR);
1496
1497 if (status & (UART011_RTIS|UART011_RXIS)) {
1498 if (pl011_dma_rx_running(uap))
1499 pl011_dma_rx_irq(uap);
1500 else
1501 pl011_rx_chars(uap);
1502 }
1503 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1504 UART011_CTSMIS|UART011_RIMIS))
1505 pl011_modem_status(uap);
1506 if (status & UART011_TXIS)
1507 pl011_tx_chars(uap, true);
1508
1509 if (pass_counter-- == 0)
1510 break;
1511
1512 status = pl011_read(uap, REG_RIS) & uap->im;
1513 } while (status != 0);
1514 handled = 1;
1515 }
1516
1517 spin_unlock_irqrestore(&uap->port.lock, flags);
1518
1519 return IRQ_RETVAL(handled);
1520 }
1521
pl011_tx_empty(struct uart_port * port)1522 static unsigned int pl011_tx_empty(struct uart_port *port)
1523 {
1524 struct uart_amba_port *uap =
1525 container_of(port, struct uart_amba_port, port);
1526
1527 /* Allow feature register bits to be inverted to work around errata */
1528 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1529
1530 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1531 0 : TIOCSER_TEMT;
1532 }
1533
pl011_get_mctrl(struct uart_port * port)1534 static unsigned int pl011_get_mctrl(struct uart_port *port)
1535 {
1536 struct uart_amba_port *uap =
1537 container_of(port, struct uart_amba_port, port);
1538 unsigned int result = 0;
1539 unsigned int status = pl011_read(uap, REG_FR);
1540
1541 #define TIOCMBIT(uartbit, tiocmbit) \
1542 if (status & uartbit) \
1543 result |= tiocmbit
1544
1545 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1546 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1547 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1548 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1549 #undef TIOCMBIT
1550 return result;
1551 }
1552
pl011_set_mctrl(struct uart_port * port,unsigned int mctrl)1553 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1554 {
1555 struct uart_amba_port *uap =
1556 container_of(port, struct uart_amba_port, port);
1557 unsigned int cr;
1558
1559 cr = pl011_read(uap, REG_CR);
1560
1561 #define TIOCMBIT(tiocmbit, uartbit) \
1562 if (mctrl & tiocmbit) \
1563 cr |= uartbit; \
1564 else \
1565 cr &= ~uartbit
1566
1567 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1568 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1569 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1570 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1571 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1572
1573 if (port->status & UPSTAT_AUTORTS) {
1574 /* We need to disable auto-RTS if we want to turn RTS off */
1575 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1576 }
1577 #undef TIOCMBIT
1578
1579 pl011_write(cr, uap, REG_CR);
1580 }
1581
pl011_break_ctl(struct uart_port * port,int break_state)1582 static void pl011_break_ctl(struct uart_port *port, int break_state)
1583 {
1584 struct uart_amba_port *uap =
1585 container_of(port, struct uart_amba_port, port);
1586 unsigned long flags;
1587 unsigned int lcr_h;
1588
1589 spin_lock_irqsave(&uap->port.lock, flags);
1590 lcr_h = pl011_read(uap, REG_LCRH_TX);
1591 if (break_state == -1)
1592 lcr_h |= UART01x_LCRH_BRK;
1593 else
1594 lcr_h &= ~UART01x_LCRH_BRK;
1595 pl011_write(lcr_h, uap, REG_LCRH_TX);
1596 spin_unlock_irqrestore(&uap->port.lock, flags);
1597 }
1598
1599 #ifdef CONFIG_CONSOLE_POLL
1600
pl011_quiesce_irqs(struct uart_port * port)1601 static void pl011_quiesce_irqs(struct uart_port *port)
1602 {
1603 struct uart_amba_port *uap =
1604 container_of(port, struct uart_amba_port, port);
1605
1606 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1607 /*
1608 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1609 * we simply mask it. start_tx() will unmask it.
1610 *
1611 * Note we can race with start_tx(), and if the race happens, the
1612 * polling user might get another interrupt just after we clear it.
1613 * But it should be OK and can happen even w/o the race, e.g.
1614 * controller immediately got some new data and raised the IRQ.
1615 *
1616 * And whoever uses polling routines assumes that it manages the device
1617 * (including tx queue), so we're also fine with start_tx()'s caller
1618 * side.
1619 */
1620 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1621 REG_IMSC);
1622 }
1623
pl011_get_poll_char(struct uart_port * port)1624 static int pl011_get_poll_char(struct uart_port *port)
1625 {
1626 struct uart_amba_port *uap =
1627 container_of(port, struct uart_amba_port, port);
1628 unsigned int status;
1629
1630 /*
1631 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1632 * debugger.
1633 */
1634 pl011_quiesce_irqs(port);
1635
1636 status = pl011_read(uap, REG_FR);
1637 if (status & UART01x_FR_RXFE)
1638 return NO_POLL_CHAR;
1639
1640 return pl011_read(uap, REG_DR);
1641 }
1642
pl011_put_poll_char(struct uart_port * port,unsigned char ch)1643 static void pl011_put_poll_char(struct uart_port *port,
1644 unsigned char ch)
1645 {
1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
1648
1649 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1650 cpu_relax();
1651
1652 pl011_write(ch, uap, REG_DR);
1653 }
1654
1655 #endif /* CONFIG_CONSOLE_POLL */
1656
pl011_hwinit(struct uart_port * port)1657 static int pl011_hwinit(struct uart_port *port)
1658 {
1659 struct uart_amba_port *uap =
1660 container_of(port, struct uart_amba_port, port);
1661 int retval;
1662
1663 /* Optionaly enable pins to be muxed in and configured */
1664 pinctrl_pm_select_default_state(port->dev);
1665
1666 /*
1667 * Try to enable the clock producer.
1668 */
1669 retval = clk_prepare_enable(uap->clk);
1670 if (retval)
1671 return retval;
1672
1673 uap->port.uartclk = clk_get_rate(uap->clk);
1674
1675 /* Clear pending error and receive interrupts */
1676 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1677 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1678 uap, REG_ICR);
1679
1680 /*
1681 * Save interrupts enable mask, and enable RX interrupts in case if
1682 * the interrupt is used for NMI entry.
1683 */
1684 uap->im = pl011_read(uap, REG_IMSC);
1685 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1686
1687 if (dev_get_platdata(uap->port.dev)) {
1688 struct amba_pl011_data *plat;
1689
1690 plat = dev_get_platdata(uap->port.dev);
1691 if (plat->init)
1692 plat->init();
1693 }
1694 return 0;
1695 }
1696
pl011_split_lcrh(const struct uart_amba_port * uap)1697 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1698 {
1699 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1700 pl011_reg_to_offset(uap, REG_LCRH_TX);
1701 }
1702
pl011_write_lcr_h(struct uart_amba_port * uap,unsigned int lcr_h)1703 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1704 {
1705 pl011_write(lcr_h, uap, REG_LCRH_RX);
1706 if (pl011_split_lcrh(uap)) {
1707 int i;
1708 /*
1709 * Wait 10 PCLKs before writing LCRH_TX register,
1710 * to get this delay write read only register 10 times
1711 */
1712 for (i = 0; i < 10; ++i)
1713 pl011_write(0xff, uap, REG_MIS);
1714 pl011_write(lcr_h, uap, REG_LCRH_TX);
1715 }
1716 }
1717
pl011_allocate_irq(struct uart_amba_port * uap)1718 static int pl011_allocate_irq(struct uart_amba_port *uap)
1719 {
1720 pl011_write(uap->im, uap, REG_IMSC);
1721
1722 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1723 }
1724
1725 /*
1726 * Enable interrupts, only timeouts when using DMA
1727 * if initial RX DMA job failed, start in interrupt mode
1728 * as well.
1729 */
pl011_enable_interrupts(struct uart_amba_port * uap)1730 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1731 {
1732 unsigned long flags;
1733 unsigned int i;
1734
1735 spin_lock_irqsave(&uap->port.lock, flags);
1736
1737 /* Clear out any spuriously appearing RX interrupts */
1738 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1739
1740 /*
1741 * RXIS is asserted only when the RX FIFO transitions from below
1742 * to above the trigger threshold. If the RX FIFO is already
1743 * full to the threshold this can't happen and RXIS will now be
1744 * stuck off. Drain the RX FIFO explicitly to fix this:
1745 */
1746 for (i = 0; i < uap->fifosize * 2; ++i) {
1747 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1748 break;
1749
1750 pl011_read(uap, REG_DR);
1751 }
1752
1753 uap->im = UART011_RTIM;
1754 if (!pl011_dma_rx_running(uap))
1755 uap->im |= UART011_RXIM;
1756 pl011_write(uap->im, uap, REG_IMSC);
1757 spin_unlock_irqrestore(&uap->port.lock, flags);
1758 }
1759
pl011_unthrottle_rx(struct uart_port * port)1760 static void pl011_unthrottle_rx(struct uart_port *port)
1761 {
1762 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1763 unsigned long flags;
1764
1765 spin_lock_irqsave(&uap->port.lock, flags);
1766
1767 uap->im = UART011_RTIM;
1768 if (!pl011_dma_rx_running(uap))
1769 uap->im |= UART011_RXIM;
1770
1771 pl011_write(uap->im, uap, REG_IMSC);
1772
1773 spin_unlock_irqrestore(&uap->port.lock, flags);
1774 }
1775
pl011_startup(struct uart_port * port)1776 static int pl011_startup(struct uart_port *port)
1777 {
1778 struct uart_amba_port *uap =
1779 container_of(port, struct uart_amba_port, port);
1780 unsigned int cr;
1781 int retval;
1782
1783 retval = pl011_hwinit(port);
1784 if (retval)
1785 goto clk_dis;
1786
1787 retval = pl011_allocate_irq(uap);
1788 if (retval)
1789 goto clk_dis;
1790
1791 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1792
1793 spin_lock_irq(&uap->port.lock);
1794
1795 /* restore RTS and DTR */
1796 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1797 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1798 pl011_write(cr, uap, REG_CR);
1799
1800 spin_unlock_irq(&uap->port.lock);
1801
1802 /*
1803 * initialise the old status of the modem signals
1804 */
1805 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1806
1807 /* Startup DMA */
1808 pl011_dma_startup(uap);
1809
1810 pl011_enable_interrupts(uap);
1811
1812 return 0;
1813
1814 clk_dis:
1815 clk_disable_unprepare(uap->clk);
1816 return retval;
1817 }
1818
sbsa_uart_startup(struct uart_port * port)1819 static int sbsa_uart_startup(struct uart_port *port)
1820 {
1821 struct uart_amba_port *uap =
1822 container_of(port, struct uart_amba_port, port);
1823 int retval;
1824
1825 retval = pl011_hwinit(port);
1826 if (retval)
1827 return retval;
1828
1829 retval = pl011_allocate_irq(uap);
1830 if (retval)
1831 return retval;
1832
1833 /* The SBSA UART does not support any modem status lines. */
1834 uap->old_status = 0;
1835
1836 pl011_enable_interrupts(uap);
1837
1838 return 0;
1839 }
1840
pl011_shutdown_channel(struct uart_amba_port * uap,unsigned int lcrh)1841 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1842 unsigned int lcrh)
1843 {
1844 unsigned long val;
1845
1846 val = pl011_read(uap, lcrh);
1847 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1848 pl011_write(val, uap, lcrh);
1849 }
1850
1851 /*
1852 * disable the port. It should not disable RTS and DTR.
1853 * Also RTS and DTR state should be preserved to restore
1854 * it during startup().
1855 */
pl011_disable_uart(struct uart_amba_port * uap)1856 static void pl011_disable_uart(struct uart_amba_port *uap)
1857 {
1858 unsigned int cr;
1859
1860 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1861 spin_lock_irq(&uap->port.lock);
1862 cr = pl011_read(uap, REG_CR);
1863 uap->old_cr = cr;
1864 cr &= UART011_CR_RTS | UART011_CR_DTR;
1865 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1866 pl011_write(cr, uap, REG_CR);
1867 spin_unlock_irq(&uap->port.lock);
1868
1869 /*
1870 * disable break condition and fifos
1871 */
1872 pl011_shutdown_channel(uap, REG_LCRH_RX);
1873 if (pl011_split_lcrh(uap))
1874 pl011_shutdown_channel(uap, REG_LCRH_TX);
1875 }
1876
pl011_disable_interrupts(struct uart_amba_port * uap)1877 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1878 {
1879 spin_lock_irq(&uap->port.lock);
1880
1881 /* mask all interrupts and clear all pending ones */
1882 uap->im = 0;
1883 pl011_write(uap->im, uap, REG_IMSC);
1884 pl011_write(0xffff, uap, REG_ICR);
1885
1886 spin_unlock_irq(&uap->port.lock);
1887 }
1888
pl011_shutdown(struct uart_port * port)1889 static void pl011_shutdown(struct uart_port *port)
1890 {
1891 struct uart_amba_port *uap =
1892 container_of(port, struct uart_amba_port, port);
1893
1894 pl011_disable_interrupts(uap);
1895
1896 pl011_dma_shutdown(uap);
1897
1898 free_irq(uap->port.irq, uap);
1899
1900 pl011_disable_uart(uap);
1901
1902 /*
1903 * Shut down the clock producer
1904 */
1905 clk_disable_unprepare(uap->clk);
1906 /* Optionally let pins go into sleep states */
1907 pinctrl_pm_select_sleep_state(port->dev);
1908
1909 if (dev_get_platdata(uap->port.dev)) {
1910 struct amba_pl011_data *plat;
1911
1912 plat = dev_get_platdata(uap->port.dev);
1913 if (plat->exit)
1914 plat->exit();
1915 }
1916
1917 if (uap->port.ops->flush_buffer)
1918 uap->port.ops->flush_buffer(port);
1919 }
1920
sbsa_uart_shutdown(struct uart_port * port)1921 static void sbsa_uart_shutdown(struct uart_port *port)
1922 {
1923 struct uart_amba_port *uap =
1924 container_of(port, struct uart_amba_port, port);
1925
1926 pl011_disable_interrupts(uap);
1927
1928 free_irq(uap->port.irq, uap);
1929
1930 if (uap->port.ops->flush_buffer)
1931 uap->port.ops->flush_buffer(port);
1932 }
1933
1934 static void
pl011_setup_status_masks(struct uart_port * port,struct ktermios * termios)1935 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1936 {
1937 port->read_status_mask = UART011_DR_OE | 255;
1938 if (termios->c_iflag & INPCK)
1939 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1940 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1941 port->read_status_mask |= UART011_DR_BE;
1942
1943 /*
1944 * Characters to ignore
1945 */
1946 port->ignore_status_mask = 0;
1947 if (termios->c_iflag & IGNPAR)
1948 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1949 if (termios->c_iflag & IGNBRK) {
1950 port->ignore_status_mask |= UART011_DR_BE;
1951 /*
1952 * If we're ignoring parity and break indicators,
1953 * ignore overruns too (for real raw support).
1954 */
1955 if (termios->c_iflag & IGNPAR)
1956 port->ignore_status_mask |= UART011_DR_OE;
1957 }
1958
1959 /*
1960 * Ignore all characters if CREAD is not set.
1961 */
1962 if ((termios->c_cflag & CREAD) == 0)
1963 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1964 }
1965
1966 static void
pl011_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1967 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1968 struct ktermios *old)
1969 {
1970 struct uart_amba_port *uap =
1971 container_of(port, struct uart_amba_port, port);
1972 unsigned int lcr_h, old_cr;
1973 unsigned long flags;
1974 unsigned int baud, quot, clkdiv;
1975
1976 if (uap->vendor->oversampling)
1977 clkdiv = 8;
1978 else
1979 clkdiv = 16;
1980
1981 /*
1982 * Ask the core to calculate the divisor for us.
1983 */
1984 baud = uart_get_baud_rate(port, termios, old, 0,
1985 port->uartclk / clkdiv);
1986 #ifdef CONFIG_DMA_ENGINE
1987 /*
1988 * Adjust RX DMA polling rate with baud rate if not specified.
1989 */
1990 if (uap->dmarx.auto_poll_rate)
1991 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1992 #endif
1993
1994 if (baud > port->uartclk/16)
1995 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1996 else
1997 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1998
1999 switch (termios->c_cflag & CSIZE) {
2000 case CS5:
2001 lcr_h = UART01x_LCRH_WLEN_5;
2002 break;
2003 case CS6:
2004 lcr_h = UART01x_LCRH_WLEN_6;
2005 break;
2006 case CS7:
2007 lcr_h = UART01x_LCRH_WLEN_7;
2008 break;
2009 default: // CS8
2010 lcr_h = UART01x_LCRH_WLEN_8;
2011 break;
2012 }
2013 if (termios->c_cflag & CSTOPB)
2014 lcr_h |= UART01x_LCRH_STP2;
2015 if (termios->c_cflag & PARENB) {
2016 lcr_h |= UART01x_LCRH_PEN;
2017 if (!(termios->c_cflag & PARODD))
2018 lcr_h |= UART01x_LCRH_EPS;
2019 if (termios->c_cflag & CMSPAR)
2020 lcr_h |= UART011_LCRH_SPS;
2021 }
2022 if (uap->fifosize > 1)
2023 lcr_h |= UART01x_LCRH_FEN;
2024
2025 spin_lock_irqsave(&port->lock, flags);
2026
2027 /*
2028 * Update the per-port timeout.
2029 */
2030 uart_update_timeout(port, termios->c_cflag, baud);
2031
2032 pl011_setup_status_masks(port, termios);
2033
2034 if (UART_ENABLE_MS(port, termios->c_cflag))
2035 pl011_enable_ms(port);
2036
2037 /* first, disable everything */
2038 old_cr = pl011_read(uap, REG_CR);
2039 pl011_write(0, uap, REG_CR);
2040
2041 if (termios->c_cflag & CRTSCTS) {
2042 if (old_cr & UART011_CR_RTS)
2043 old_cr |= UART011_CR_RTSEN;
2044
2045 old_cr |= UART011_CR_CTSEN;
2046 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2047 } else {
2048 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2049 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2050 }
2051
2052 if (uap->vendor->oversampling) {
2053 if (baud > port->uartclk / 16)
2054 old_cr |= ST_UART011_CR_OVSFACT;
2055 else
2056 old_cr &= ~ST_UART011_CR_OVSFACT;
2057 }
2058
2059 /*
2060 * Workaround for the ST Micro oversampling variants to
2061 * increase the bitrate slightly, by lowering the divisor,
2062 * to avoid delayed sampling of start bit at high speeds,
2063 * else we see data corruption.
2064 */
2065 if (uap->vendor->oversampling) {
2066 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2067 quot -= 1;
2068 else if ((baud > 3250000) && (quot > 2))
2069 quot -= 2;
2070 }
2071 /* Set baud rate */
2072 pl011_write(quot & 0x3f, uap, REG_FBRD);
2073 pl011_write(quot >> 6, uap, REG_IBRD);
2074
2075 /*
2076 * ----------v----------v----------v----------v-----
2077 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2078 * REG_FBRD & REG_IBRD.
2079 * ----------^----------^----------^----------^-----
2080 */
2081 pl011_write_lcr_h(uap, lcr_h);
2082 pl011_write(old_cr, uap, REG_CR);
2083
2084 spin_unlock_irqrestore(&port->lock, flags);
2085 }
2086
2087 static void
sbsa_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)2088 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2089 struct ktermios *old)
2090 {
2091 struct uart_amba_port *uap =
2092 container_of(port, struct uart_amba_port, port);
2093 unsigned long flags;
2094
2095 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2096
2097 /* The SBSA UART only supports 8n1 without hardware flow control. */
2098 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2099 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2100 termios->c_cflag |= CS8 | CLOCAL;
2101
2102 spin_lock_irqsave(&port->lock, flags);
2103 uart_update_timeout(port, CS8, uap->fixed_baud);
2104 pl011_setup_status_masks(port, termios);
2105 spin_unlock_irqrestore(&port->lock, flags);
2106 }
2107
pl011_type(struct uart_port * port)2108 static const char *pl011_type(struct uart_port *port)
2109 {
2110 struct uart_amba_port *uap =
2111 container_of(port, struct uart_amba_port, port);
2112 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2113 }
2114
2115 /*
2116 * Configure/autoconfigure the port.
2117 */
pl011_config_port(struct uart_port * port,int flags)2118 static void pl011_config_port(struct uart_port *port, int flags)
2119 {
2120 if (flags & UART_CONFIG_TYPE)
2121 port->type = PORT_AMBA;
2122 }
2123
2124 /*
2125 * verify the new serial_struct (for TIOCSSERIAL).
2126 */
pl011_verify_port(struct uart_port * port,struct serial_struct * ser)2127 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2128 {
2129 int ret = 0;
2130 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2131 ret = -EINVAL;
2132 if (ser->irq < 0 || ser->irq >= nr_irqs)
2133 ret = -EINVAL;
2134 if (ser->baud_base < 9600)
2135 ret = -EINVAL;
2136 if (port->mapbase != (unsigned long) ser->iomem_base)
2137 ret = -EINVAL;
2138 return ret;
2139 }
2140
2141 static const struct uart_ops amba_pl011_pops = {
2142 .tx_empty = pl011_tx_empty,
2143 .set_mctrl = pl011_set_mctrl,
2144 .get_mctrl = pl011_get_mctrl,
2145 .stop_tx = pl011_stop_tx,
2146 .start_tx = pl011_start_tx,
2147 .stop_rx = pl011_stop_rx,
2148 .throttle = pl011_throttle_rx,
2149 .unthrottle = pl011_unthrottle_rx,
2150 .enable_ms = pl011_enable_ms,
2151 .break_ctl = pl011_break_ctl,
2152 .startup = pl011_startup,
2153 .shutdown = pl011_shutdown,
2154 .flush_buffer = pl011_dma_flush_buffer,
2155 .set_termios = pl011_set_termios,
2156 .type = pl011_type,
2157 .config_port = pl011_config_port,
2158 .verify_port = pl011_verify_port,
2159 #ifdef CONFIG_CONSOLE_POLL
2160 .poll_init = pl011_hwinit,
2161 .poll_get_char = pl011_get_poll_char,
2162 .poll_put_char = pl011_put_poll_char,
2163 #endif
2164 };
2165
sbsa_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)2166 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2167 {
2168 }
2169
sbsa_uart_get_mctrl(struct uart_port * port)2170 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2171 {
2172 return 0;
2173 }
2174
2175 static const struct uart_ops sbsa_uart_pops = {
2176 .tx_empty = pl011_tx_empty,
2177 .set_mctrl = sbsa_uart_set_mctrl,
2178 .get_mctrl = sbsa_uart_get_mctrl,
2179 .stop_tx = pl011_stop_tx,
2180 .start_tx = pl011_start_tx,
2181 .stop_rx = pl011_stop_rx,
2182 .startup = sbsa_uart_startup,
2183 .shutdown = sbsa_uart_shutdown,
2184 .set_termios = sbsa_uart_set_termios,
2185 .type = pl011_type,
2186 .config_port = pl011_config_port,
2187 .verify_port = pl011_verify_port,
2188 #ifdef CONFIG_CONSOLE_POLL
2189 .poll_init = pl011_hwinit,
2190 .poll_get_char = pl011_get_poll_char,
2191 .poll_put_char = pl011_put_poll_char,
2192 #endif
2193 };
2194
2195 static struct uart_amba_port *amba_ports[UART_NR];
2196
2197 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2198
pl011_console_putchar(struct uart_port * port,int ch)2199 static void pl011_console_putchar(struct uart_port *port, int ch)
2200 {
2201 struct uart_amba_port *uap =
2202 container_of(port, struct uart_amba_port, port);
2203
2204 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2205 cpu_relax();
2206 pl011_write(ch, uap, REG_DR);
2207 }
2208
2209 static void
pl011_console_write(struct console * co,const char * s,unsigned int count)2210 pl011_console_write(struct console *co, const char *s, unsigned int count)
2211 {
2212 struct uart_amba_port *uap = amba_ports[co->index];
2213 unsigned int old_cr = 0, new_cr;
2214 unsigned long flags;
2215 int locked = 1;
2216
2217 clk_enable(uap->clk);
2218
2219 local_irq_save(flags);
2220 if (uap->port.sysrq)
2221 locked = 0;
2222 else if (oops_in_progress)
2223 locked = spin_trylock(&uap->port.lock);
2224 else
2225 spin_lock(&uap->port.lock);
2226
2227 /*
2228 * First save the CR then disable the interrupts
2229 */
2230 if (!uap->vendor->always_enabled) {
2231 old_cr = pl011_read(uap, REG_CR);
2232 new_cr = old_cr & ~UART011_CR_CTSEN;
2233 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2234 pl011_write(new_cr, uap, REG_CR);
2235 }
2236
2237 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2238
2239 /*
2240 * Finally, wait for transmitter to become empty and restore the
2241 * TCR. Allow feature register bits to be inverted to work around
2242 * errata.
2243 */
2244 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2245 & uap->vendor->fr_busy)
2246 cpu_relax();
2247 if (!uap->vendor->always_enabled)
2248 pl011_write(old_cr, uap, REG_CR);
2249
2250 if (locked)
2251 spin_unlock(&uap->port.lock);
2252 local_irq_restore(flags);
2253
2254 clk_disable(uap->clk);
2255 }
2256
pl011_console_get_options(struct uart_amba_port * uap,int * baud,int * parity,int * bits)2257 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2258 int *parity, int *bits)
2259 {
2260 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2261 unsigned int lcr_h, ibrd, fbrd;
2262
2263 lcr_h = pl011_read(uap, REG_LCRH_TX);
2264
2265 *parity = 'n';
2266 if (lcr_h & UART01x_LCRH_PEN) {
2267 if (lcr_h & UART01x_LCRH_EPS)
2268 *parity = 'e';
2269 else
2270 *parity = 'o';
2271 }
2272
2273 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2274 *bits = 7;
2275 else
2276 *bits = 8;
2277
2278 ibrd = pl011_read(uap, REG_IBRD);
2279 fbrd = pl011_read(uap, REG_FBRD);
2280
2281 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2282
2283 if (uap->vendor->oversampling) {
2284 if (pl011_read(uap, REG_CR)
2285 & ST_UART011_CR_OVSFACT)
2286 *baud *= 2;
2287 }
2288 }
2289 }
2290
pl011_console_setup(struct console * co,char * options)2291 static int pl011_console_setup(struct console *co, char *options)
2292 {
2293 struct uart_amba_port *uap;
2294 int baud = 38400;
2295 int bits = 8;
2296 int parity = 'n';
2297 int flow = 'n';
2298 int ret;
2299
2300 /*
2301 * Check whether an invalid uart number has been specified, and
2302 * if so, search for the first available port that does have
2303 * console support.
2304 */
2305 if (co->index >= UART_NR)
2306 co->index = 0;
2307 uap = amba_ports[co->index];
2308 if (!uap)
2309 return -ENODEV;
2310
2311 /* Allow pins to be muxed in and configured */
2312 pinctrl_pm_select_default_state(uap->port.dev);
2313
2314 ret = clk_prepare(uap->clk);
2315 if (ret)
2316 return ret;
2317
2318 if (dev_get_platdata(uap->port.dev)) {
2319 struct amba_pl011_data *plat;
2320
2321 plat = dev_get_platdata(uap->port.dev);
2322 if (plat->init)
2323 plat->init();
2324 }
2325
2326 uap->port.uartclk = clk_get_rate(uap->clk);
2327
2328 if (uap->vendor->fixed_options) {
2329 baud = uap->fixed_baud;
2330 } else {
2331 if (options)
2332 uart_parse_options(options,
2333 &baud, &parity, &bits, &flow);
2334 else
2335 pl011_console_get_options(uap, &baud, &parity, &bits);
2336 }
2337
2338 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2339 }
2340
2341 /**
2342 * pl011_console_match - non-standard console matching
2343 * @co: registering console
2344 * @name: name from console command line
2345 * @idx: index from console command line
2346 * @options: ptr to option string from console command line
2347 *
2348 * Only attempts to match console command lines of the form:
2349 * console=pl011,mmio|mmio32,<addr>[,<options>]
2350 * console=pl011,0x<addr>[,<options>]
2351 * This form is used to register an initial earlycon boot console and
2352 * replace it with the amba_console at pl011 driver init.
2353 *
2354 * Performs console setup for a match (as required by interface)
2355 * If no <options> are specified, then assume the h/w is already setup.
2356 *
2357 * Returns 0 if console matches; otherwise non-zero to use default matching
2358 */
pl011_console_match(struct console * co,char * name,int idx,char * options)2359 static int pl011_console_match(struct console *co, char *name, int idx,
2360 char *options)
2361 {
2362 unsigned char iotype;
2363 resource_size_t addr;
2364 int i;
2365
2366 /*
2367 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2368 * have a distinct console name, so make sure we check for that.
2369 * The actual implementation of the erratum occurs in the probe
2370 * function.
2371 */
2372 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2373 return -ENODEV;
2374
2375 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2376 return -ENODEV;
2377
2378 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2379 return -ENODEV;
2380
2381 /* try to match the port specified on the command line */
2382 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2383 struct uart_port *port;
2384
2385 if (!amba_ports[i])
2386 continue;
2387
2388 port = &amba_ports[i]->port;
2389
2390 if (port->mapbase != addr)
2391 continue;
2392
2393 co->index = i;
2394 port->cons = co;
2395 return pl011_console_setup(co, options);
2396 }
2397
2398 return -ENODEV;
2399 }
2400
2401 static struct uart_driver amba_reg;
2402 static struct console amba_console = {
2403 .name = "ttyAMA",
2404 .write = pl011_console_write,
2405 .device = uart_console_device,
2406 .setup = pl011_console_setup,
2407 .match = pl011_console_match,
2408 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2409 .index = -1,
2410 .data = &amba_reg,
2411 };
2412
2413 #define AMBA_CONSOLE (&amba_console)
2414
qdf2400_e44_putc(struct uart_port * port,int c)2415 static void qdf2400_e44_putc(struct uart_port *port, int c)
2416 {
2417 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2418 cpu_relax();
2419 writel(c, port->membase + UART01x_DR);
2420 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2421 cpu_relax();
2422 }
2423
qdf2400_e44_early_write(struct console * con,const char * s,unsigned n)2424 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2425 {
2426 struct earlycon_device *dev = con->data;
2427
2428 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2429 }
2430
pl011_putc(struct uart_port * port,int c)2431 static void pl011_putc(struct uart_port *port, int c)
2432 {
2433 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2434 cpu_relax();
2435 if (port->iotype == UPIO_MEM32)
2436 writel(c, port->membase + UART01x_DR);
2437 else
2438 writeb(c, port->membase + UART01x_DR);
2439 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2440 cpu_relax();
2441 }
2442
pl011_early_write(struct console * con,const char * s,unsigned n)2443 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2444 {
2445 struct earlycon_device *dev = con->data;
2446
2447 uart_console_write(&dev->port, s, n, pl011_putc);
2448 }
2449
2450 #ifdef CONFIG_CONSOLE_POLL
pl011_getc(struct uart_port * port)2451 static int pl011_getc(struct uart_port *port)
2452 {
2453 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2454 return NO_POLL_CHAR;
2455
2456 if (port->iotype == UPIO_MEM32)
2457 return readl(port->membase + UART01x_DR);
2458 else
2459 return readb(port->membase + UART01x_DR);
2460 }
2461
pl011_early_read(struct console * con,char * s,unsigned int n)2462 static int pl011_early_read(struct console *con, char *s, unsigned int n)
2463 {
2464 struct earlycon_device *dev = con->data;
2465 int ch, num_read = 0;
2466
2467 while (num_read < n) {
2468 ch = pl011_getc(&dev->port);
2469 if (ch == NO_POLL_CHAR)
2470 break;
2471
2472 s[num_read++] = ch;
2473 }
2474
2475 return num_read;
2476 }
2477 #else
2478 #define pl011_early_read NULL
2479 #endif
2480
2481 /*
2482 * On non-ACPI systems, earlycon is enabled by specifying
2483 * "earlycon=pl011,<address>" on the kernel command line.
2484 *
2485 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2486 * by specifying only "earlycon" on the command line. Because it requires
2487 * SPCR, the console starts after ACPI is parsed, which is later than a
2488 * traditional early console.
2489 *
2490 * To get the traditional early console that starts before ACPI is parsed,
2491 * specify the full "earlycon=pl011,<address>" option.
2492 */
pl011_early_console_setup(struct earlycon_device * device,const char * opt)2493 static int __init pl011_early_console_setup(struct earlycon_device *device,
2494 const char *opt)
2495 {
2496 if (!device->port.membase)
2497 return -ENODEV;
2498
2499 device->con->write = pl011_early_write;
2500 device->con->read = pl011_early_read;
2501
2502 return 0;
2503 }
2504 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2505 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2506
2507 /*
2508 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2509 * Erratum 44, traditional earlycon can be enabled by specifying
2510 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2511 *
2512 * Alternatively, you can just specify "earlycon", and the early console
2513 * will be enabled with the information from the SPCR table. In this
2514 * case, the SPCR code will detect the need for the E44 work-around,
2515 * and set the console name to "qdf2400_e44".
2516 */
2517 static int __init
qdf2400_e44_early_console_setup(struct earlycon_device * device,const char * opt)2518 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2519 const char *opt)
2520 {
2521 if (!device->port.membase)
2522 return -ENODEV;
2523
2524 device->con->write = qdf2400_e44_early_write;
2525 return 0;
2526 }
2527 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2528
2529 #else
2530 #define AMBA_CONSOLE NULL
2531 #endif
2532
2533 static struct uart_driver amba_reg = {
2534 .owner = THIS_MODULE,
2535 .driver_name = "ttyAMA",
2536 .dev_name = "ttyAMA",
2537 .major = SERIAL_AMBA_MAJOR,
2538 .minor = SERIAL_AMBA_MINOR,
2539 .nr = UART_NR,
2540 .cons = AMBA_CONSOLE,
2541 };
2542
pl011_probe_dt_alias(int index,struct device * dev)2543 static int pl011_probe_dt_alias(int index, struct device *dev)
2544 {
2545 struct device_node *np;
2546 static bool seen_dev_with_alias = false;
2547 static bool seen_dev_without_alias = false;
2548 int ret = index;
2549
2550 if (!IS_ENABLED(CONFIG_OF))
2551 return ret;
2552
2553 np = dev->of_node;
2554 if (!np)
2555 return ret;
2556
2557 ret = of_alias_get_id(np, "serial");
2558 if (ret < 0) {
2559 seen_dev_without_alias = true;
2560 ret = index;
2561 } else {
2562 seen_dev_with_alias = true;
2563 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2564 dev_warn(dev, "requested serial port %d not available.\n", ret);
2565 ret = index;
2566 }
2567 }
2568
2569 if (seen_dev_with_alias && seen_dev_without_alias)
2570 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2571
2572 return ret;
2573 }
2574
2575 /* unregisters the driver also if no more ports are left */
pl011_unregister_port(struct uart_amba_port * uap)2576 static void pl011_unregister_port(struct uart_amba_port *uap)
2577 {
2578 int i;
2579 bool busy = false;
2580
2581 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2582 if (amba_ports[i] == uap)
2583 amba_ports[i] = NULL;
2584 else if (amba_ports[i])
2585 busy = true;
2586 }
2587 pl011_dma_remove(uap);
2588 if (!busy)
2589 uart_unregister_driver(&amba_reg);
2590 }
2591
pl011_find_free_port(void)2592 static int pl011_find_free_port(void)
2593 {
2594 int i;
2595
2596 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2597 if (amba_ports[i] == NULL)
2598 return i;
2599
2600 return -EBUSY;
2601 }
2602
pl011_setup_port(struct device * dev,struct uart_amba_port * uap,struct resource * mmiobase,int index)2603 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2604 struct resource *mmiobase, int index)
2605 {
2606 void __iomem *base;
2607
2608 base = devm_ioremap_resource(dev, mmiobase);
2609 if (IS_ERR(base))
2610 return PTR_ERR(base);
2611
2612 index = pl011_probe_dt_alias(index, dev);
2613
2614 uap->old_cr = 0;
2615 uap->port.dev = dev;
2616 uap->port.mapbase = mmiobase->start;
2617 uap->port.membase = base;
2618 uap->port.fifosize = uap->fifosize;
2619 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2620 uap->port.flags = UPF_BOOT_AUTOCONF;
2621 uap->port.line = index;
2622
2623 amba_ports[index] = uap;
2624
2625 return 0;
2626 }
2627
pl011_register_port(struct uart_amba_port * uap)2628 static int pl011_register_port(struct uart_amba_port *uap)
2629 {
2630 int ret, i;
2631
2632 /* Ensure interrupts from this UART are masked and cleared */
2633 pl011_write(0, uap, REG_IMSC);
2634 pl011_write(0xffff, uap, REG_ICR);
2635
2636 if (!amba_reg.state) {
2637 ret = uart_register_driver(&amba_reg);
2638 if (ret < 0) {
2639 dev_err(uap->port.dev,
2640 "Failed to register AMBA-PL011 driver\n");
2641 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2642 if (amba_ports[i] == uap)
2643 amba_ports[i] = NULL;
2644 return ret;
2645 }
2646 }
2647
2648 ret = uart_add_one_port(&amba_reg, &uap->port);
2649 if (ret)
2650 pl011_unregister_port(uap);
2651
2652 return ret;
2653 }
2654
pl011_probe(struct amba_device * dev,const struct amba_id * id)2655 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2656 {
2657 struct uart_amba_port *uap;
2658 struct vendor_data *vendor = id->data;
2659 int portnr, ret;
2660
2661 portnr = pl011_find_free_port();
2662 if (portnr < 0)
2663 return portnr;
2664
2665 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2666 GFP_KERNEL);
2667 if (!uap)
2668 return -ENOMEM;
2669
2670 uap->clk = devm_clk_get(&dev->dev, NULL);
2671 if (IS_ERR(uap->clk))
2672 return PTR_ERR(uap->clk);
2673
2674 uap->reg_offset = vendor->reg_offset;
2675 uap->vendor = vendor;
2676 uap->fifosize = vendor->get_fifosize(dev);
2677 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2678 uap->port.irq = dev->irq[0];
2679 uap->port.ops = &amba_pl011_pops;
2680
2681 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2682
2683 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2684 if (ret)
2685 return ret;
2686
2687 amba_set_drvdata(dev, uap);
2688
2689 return pl011_register_port(uap);
2690 }
2691
pl011_remove(struct amba_device * dev)2692 static void pl011_remove(struct amba_device *dev)
2693 {
2694 struct uart_amba_port *uap = amba_get_drvdata(dev);
2695
2696 uart_remove_one_port(&amba_reg, &uap->port);
2697 pl011_unregister_port(uap);
2698 }
2699
2700 #ifdef CONFIG_PM_SLEEP
pl011_suspend(struct device * dev)2701 static int pl011_suspend(struct device *dev)
2702 {
2703 struct uart_amba_port *uap = dev_get_drvdata(dev);
2704
2705 if (!uap)
2706 return -EINVAL;
2707
2708 return uart_suspend_port(&amba_reg, &uap->port);
2709 }
2710
pl011_resume(struct device * dev)2711 static int pl011_resume(struct device *dev)
2712 {
2713 struct uart_amba_port *uap = dev_get_drvdata(dev);
2714
2715 if (!uap)
2716 return -EINVAL;
2717
2718 return uart_resume_port(&amba_reg, &uap->port);
2719 }
2720 #endif
2721
2722 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2723
sbsa_uart_probe(struct platform_device * pdev)2724 static int sbsa_uart_probe(struct platform_device *pdev)
2725 {
2726 struct uart_amba_port *uap;
2727 struct resource *r;
2728 int portnr, ret;
2729 int baudrate;
2730
2731 /*
2732 * Check the mandatory baud rate parameter in the DT node early
2733 * so that we can easily exit with the error.
2734 */
2735 if (pdev->dev.of_node) {
2736 struct device_node *np = pdev->dev.of_node;
2737
2738 ret = of_property_read_u32(np, "current-speed", &baudrate);
2739 if (ret)
2740 return ret;
2741 } else {
2742 baudrate = 115200;
2743 }
2744
2745 portnr = pl011_find_free_port();
2746 if (portnr < 0)
2747 return portnr;
2748
2749 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2750 GFP_KERNEL);
2751 if (!uap)
2752 return -ENOMEM;
2753
2754 ret = platform_get_irq(pdev, 0);
2755 if (ret < 0)
2756 return ret;
2757 uap->port.irq = ret;
2758
2759 #ifdef CONFIG_ACPI_SPCR_TABLE
2760 if (qdf2400_e44_present) {
2761 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2762 uap->vendor = &vendor_qdt_qdf2400_e44;
2763 } else
2764 #endif
2765 uap->vendor = &vendor_sbsa;
2766
2767 uap->reg_offset = uap->vendor->reg_offset;
2768 uap->fifosize = 32;
2769 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2770 uap->port.ops = &sbsa_uart_pops;
2771 uap->fixed_baud = baudrate;
2772
2773 snprintf(uap->type, sizeof(uap->type), "SBSA");
2774
2775 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2776
2777 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2778 if (ret)
2779 return ret;
2780
2781 platform_set_drvdata(pdev, uap);
2782
2783 return pl011_register_port(uap);
2784 }
2785
sbsa_uart_remove(struct platform_device * pdev)2786 static int sbsa_uart_remove(struct platform_device *pdev)
2787 {
2788 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2789
2790 uart_remove_one_port(&amba_reg, &uap->port);
2791 pl011_unregister_port(uap);
2792 return 0;
2793 }
2794
2795 static const struct of_device_id sbsa_uart_of_match[] = {
2796 { .compatible = "arm,sbsa-uart", },
2797 {},
2798 };
2799 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2800
2801 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2802 { "ARMH0011", 0 },
2803 { "ARMHB000", 0 },
2804 {},
2805 };
2806 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2807
2808 static struct platform_driver arm_sbsa_uart_platform_driver = {
2809 .probe = sbsa_uart_probe,
2810 .remove = sbsa_uart_remove,
2811 .driver = {
2812 .name = "sbsa-uart",
2813 .pm = &pl011_dev_pm_ops,
2814 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2815 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2816 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2817 },
2818 };
2819
2820 static const struct amba_id pl011_ids[] = {
2821 {
2822 .id = 0x00041011,
2823 .mask = 0x000fffff,
2824 .data = &vendor_arm,
2825 },
2826 {
2827 .id = 0x00380802,
2828 .mask = 0x00ffffff,
2829 .data = &vendor_st,
2830 },
2831 {
2832 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2833 .mask = 0x00ffffff,
2834 .data = &vendor_zte,
2835 },
2836 { 0, 0 },
2837 };
2838
2839 MODULE_DEVICE_TABLE(amba, pl011_ids);
2840
2841 static struct amba_driver pl011_driver = {
2842 .drv = {
2843 .name = "uart-pl011",
2844 .pm = &pl011_dev_pm_ops,
2845 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2846 },
2847 .id_table = pl011_ids,
2848 .probe = pl011_probe,
2849 .remove = pl011_remove,
2850 };
2851
pl011_init(void)2852 static int __init pl011_init(void)
2853 {
2854 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2855
2856 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2857 pr_warn("could not register SBSA UART platform driver\n");
2858 return amba_driver_register(&pl011_driver);
2859 }
2860
pl011_exit(void)2861 static void __exit pl011_exit(void)
2862 {
2863 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2864 amba_driver_unregister(&pl011_driver);
2865 }
2866
2867 /*
2868 * While this can be a module, if builtin it's most likely the console
2869 * So let's leave module_exit but move module_init to an earlier place
2870 */
2871 arch_initcall(pl011_init);
2872 module_exit(pl011_exit);
2873
2874 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2875 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2876 MODULE_LICENSE("GPL");
2877