1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/version.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/gpio.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/of_device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
34 #include <dt-bindings/sound/cs42l42.h>
35
36 #include "cs42l42.h"
37
38 static const struct reg_default cs42l42_reg_defaults[] = {
39 { CS42L42_FRZ_CTL, 0x00 },
40 { CS42L42_SRC_CTL, 0x10 },
41 { CS42L42_MCLK_STATUS, 0x02 },
42 { CS42L42_MCLK_CTL, 0x02 },
43 { CS42L42_SFTRAMP_RATE, 0xA4 },
44 { CS42L42_I2C_DEBOUNCE, 0x88 },
45 { CS42L42_I2C_STRETCH, 0x03 },
46 { CS42L42_I2C_TIMEOUT, 0xB7 },
47 { CS42L42_PWR_CTL1, 0xFF },
48 { CS42L42_PWR_CTL2, 0x84 },
49 { CS42L42_PWR_CTL3, 0x20 },
50 { CS42L42_RSENSE_CTL1, 0x40 },
51 { CS42L42_RSENSE_CTL2, 0x00 },
52 { CS42L42_OSC_SWITCH, 0x00 },
53 { CS42L42_OSC_SWITCH_STATUS, 0x05 },
54 { CS42L42_RSENSE_CTL3, 0x1B },
55 { CS42L42_TSENSE_CTL, 0x1B },
56 { CS42L42_TSRS_INT_DISABLE, 0x00 },
57 { CS42L42_TRSENSE_STATUS, 0x00 },
58 { CS42L42_HSDET_CTL1, 0x77 },
59 { CS42L42_HSDET_CTL2, 0x00 },
60 { CS42L42_HS_SWITCH_CTL, 0xF3 },
61 { CS42L42_HS_DET_STATUS, 0x00 },
62 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
63 { CS42L42_MCLK_SRC_SEL, 0x00 },
64 { CS42L42_SPDIF_CLK_CFG, 0x00 },
65 { CS42L42_FSYNC_PW_LOWER, 0x00 },
66 { CS42L42_FSYNC_PW_UPPER, 0x00 },
67 { CS42L42_FSYNC_P_LOWER, 0xF9 },
68 { CS42L42_FSYNC_P_UPPER, 0x00 },
69 { CS42L42_ASP_CLK_CFG, 0x00 },
70 { CS42L42_ASP_FRM_CFG, 0x10 },
71 { CS42L42_FS_RATE_EN, 0x00 },
72 { CS42L42_IN_ASRC_CLK, 0x00 },
73 { CS42L42_OUT_ASRC_CLK, 0x00 },
74 { CS42L42_PLL_DIV_CFG1, 0x00 },
75 { CS42L42_ADC_OVFL_STATUS, 0x00 },
76 { CS42L42_MIXER_STATUS, 0x00 },
77 { CS42L42_SRC_STATUS, 0x00 },
78 { CS42L42_ASP_RX_STATUS, 0x00 },
79 { CS42L42_ASP_TX_STATUS, 0x00 },
80 { CS42L42_CODEC_STATUS, 0x00 },
81 { CS42L42_DET_INT_STATUS1, 0x00 },
82 { CS42L42_DET_INT_STATUS2, 0x00 },
83 { CS42L42_SRCPL_INT_STATUS, 0x00 },
84 { CS42L42_VPMON_STATUS, 0x00 },
85 { CS42L42_PLL_LOCK_STATUS, 0x00 },
86 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
87 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
88 { CS42L42_MIXER_INT_MASK, 0x0F },
89 { CS42L42_SRC_INT_MASK, 0x0F },
90 { CS42L42_ASP_RX_INT_MASK, 0x1F },
91 { CS42L42_ASP_TX_INT_MASK, 0x0F },
92 { CS42L42_CODEC_INT_MASK, 0x03 },
93 { CS42L42_SRCPL_INT_MASK, 0x7F },
94 { CS42L42_VPMON_INT_MASK, 0x01 },
95 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
96 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
97 { CS42L42_PLL_CTL1, 0x00 },
98 { CS42L42_PLL_DIV_FRAC0, 0x00 },
99 { CS42L42_PLL_DIV_FRAC1, 0x00 },
100 { CS42L42_PLL_DIV_FRAC2, 0x00 },
101 { CS42L42_PLL_DIV_INT, 0x40 },
102 { CS42L42_PLL_CTL3, 0x10 },
103 { CS42L42_PLL_CAL_RATIO, 0x80 },
104 { CS42L42_PLL_CTL4, 0x03 },
105 { CS42L42_LOAD_DET_RCSTAT, 0x00 },
106 { CS42L42_LOAD_DET_DONE, 0x00 },
107 { CS42L42_LOAD_DET_EN, 0x00 },
108 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
109 { CS42L42_WAKE_CTL, 0xC0 },
110 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
111 { CS42L42_TIPSENSE_CTL, 0x02 },
112 { CS42L42_MISC_DET_CTL, 0x03 },
113 { CS42L42_MIC_DET_CTL1, 0x1F },
114 { CS42L42_MIC_DET_CTL2, 0x2F },
115 { CS42L42_DET_STATUS1, 0x00 },
116 { CS42L42_DET_STATUS2, 0x00 },
117 { CS42L42_DET_INT1_MASK, 0xE0 },
118 { CS42L42_DET_INT2_MASK, 0xFF },
119 { CS42L42_HS_BIAS_CTL, 0xC2 },
120 { CS42L42_ADC_CTL, 0x00 },
121 { CS42L42_ADC_VOLUME, 0x00 },
122 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
123 { CS42L42_DAC_CTL1, 0x00 },
124 { CS42L42_DAC_CTL2, 0x02 },
125 { CS42L42_HP_CTL, 0x0D },
126 { CS42L42_CLASSH_CTL, 0x07 },
127 { CS42L42_MIXER_CHA_VOL, 0x3F },
128 { CS42L42_MIXER_ADC_VOL, 0x3F },
129 { CS42L42_MIXER_CHB_VOL, 0x3F },
130 { CS42L42_EQ_COEF_IN0, 0x00 },
131 { CS42L42_EQ_COEF_IN1, 0x00 },
132 { CS42L42_EQ_COEF_IN2, 0x00 },
133 { CS42L42_EQ_COEF_IN3, 0x00 },
134 { CS42L42_EQ_COEF_RW, 0x00 },
135 { CS42L42_EQ_COEF_OUT0, 0x00 },
136 { CS42L42_EQ_COEF_OUT1, 0x00 },
137 { CS42L42_EQ_COEF_OUT2, 0x00 },
138 { CS42L42_EQ_COEF_OUT3, 0x00 },
139 { CS42L42_EQ_INIT_STAT, 0x00 },
140 { CS42L42_EQ_START_FILT, 0x00 },
141 { CS42L42_EQ_MUTE_CTL, 0x00 },
142 { CS42L42_SP_RX_CH_SEL, 0x04 },
143 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
144 { CS42L42_SP_RX_FS, 0x8C },
145 { CS42l42_SPDIF_CH_SEL, 0x0E },
146 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
147 { CS42L42_SP_TX_FS, 0xCC },
148 { CS42L42_SPDIF_SW_CTL1, 0x3F },
149 { CS42L42_SRC_SDIN_FS, 0x40 },
150 { CS42L42_SRC_SDOUT_FS, 0x40 },
151 { CS42L42_SPDIF_CTL1, 0x01 },
152 { CS42L42_SPDIF_CTL2, 0x00 },
153 { CS42L42_SPDIF_CTL3, 0x00 },
154 { CS42L42_SPDIF_CTL4, 0x42 },
155 { CS42L42_ASP_TX_SZ_EN, 0x00 },
156 { CS42L42_ASP_TX_CH_EN, 0x00 },
157 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
158 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
159 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
160 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
161 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
162 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
163 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
164 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
165 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
166 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
167 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
168 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
169 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
170 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
171 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
172 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
173 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
174 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
175 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
176 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
177 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
178 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
179 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
180 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
181 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
182 { CS42L42_SUB_REVID, 0x03 },
183 };
184
cs42l42_readable_register(struct device * dev,unsigned int reg)185 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
186 {
187 switch (reg) {
188 case CS42L42_PAGE_REGISTER:
189 case CS42L42_DEVID_AB:
190 case CS42L42_DEVID_CD:
191 case CS42L42_DEVID_E:
192 case CS42L42_FABID:
193 case CS42L42_REVID:
194 case CS42L42_FRZ_CTL:
195 case CS42L42_SRC_CTL:
196 case CS42L42_MCLK_STATUS:
197 case CS42L42_MCLK_CTL:
198 case CS42L42_SFTRAMP_RATE:
199 case CS42L42_I2C_DEBOUNCE:
200 case CS42L42_I2C_STRETCH:
201 case CS42L42_I2C_TIMEOUT:
202 case CS42L42_PWR_CTL1:
203 case CS42L42_PWR_CTL2:
204 case CS42L42_PWR_CTL3:
205 case CS42L42_RSENSE_CTL1:
206 case CS42L42_RSENSE_CTL2:
207 case CS42L42_OSC_SWITCH:
208 case CS42L42_OSC_SWITCH_STATUS:
209 case CS42L42_RSENSE_CTL3:
210 case CS42L42_TSENSE_CTL:
211 case CS42L42_TSRS_INT_DISABLE:
212 case CS42L42_TRSENSE_STATUS:
213 case CS42L42_HSDET_CTL1:
214 case CS42L42_HSDET_CTL2:
215 case CS42L42_HS_SWITCH_CTL:
216 case CS42L42_HS_DET_STATUS:
217 case CS42L42_HS_CLAMP_DISABLE:
218 case CS42L42_MCLK_SRC_SEL:
219 case CS42L42_SPDIF_CLK_CFG:
220 case CS42L42_FSYNC_PW_LOWER:
221 case CS42L42_FSYNC_PW_UPPER:
222 case CS42L42_FSYNC_P_LOWER:
223 case CS42L42_FSYNC_P_UPPER:
224 case CS42L42_ASP_CLK_CFG:
225 case CS42L42_ASP_FRM_CFG:
226 case CS42L42_FS_RATE_EN:
227 case CS42L42_IN_ASRC_CLK:
228 case CS42L42_OUT_ASRC_CLK:
229 case CS42L42_PLL_DIV_CFG1:
230 case CS42L42_ADC_OVFL_STATUS:
231 case CS42L42_MIXER_STATUS:
232 case CS42L42_SRC_STATUS:
233 case CS42L42_ASP_RX_STATUS:
234 case CS42L42_ASP_TX_STATUS:
235 case CS42L42_CODEC_STATUS:
236 case CS42L42_DET_INT_STATUS1:
237 case CS42L42_DET_INT_STATUS2:
238 case CS42L42_SRCPL_INT_STATUS:
239 case CS42L42_VPMON_STATUS:
240 case CS42L42_PLL_LOCK_STATUS:
241 case CS42L42_TSRS_PLUG_STATUS:
242 case CS42L42_ADC_OVFL_INT_MASK:
243 case CS42L42_MIXER_INT_MASK:
244 case CS42L42_SRC_INT_MASK:
245 case CS42L42_ASP_RX_INT_MASK:
246 case CS42L42_ASP_TX_INT_MASK:
247 case CS42L42_CODEC_INT_MASK:
248 case CS42L42_SRCPL_INT_MASK:
249 case CS42L42_VPMON_INT_MASK:
250 case CS42L42_PLL_LOCK_INT_MASK:
251 case CS42L42_TSRS_PLUG_INT_MASK:
252 case CS42L42_PLL_CTL1:
253 case CS42L42_PLL_DIV_FRAC0:
254 case CS42L42_PLL_DIV_FRAC1:
255 case CS42L42_PLL_DIV_FRAC2:
256 case CS42L42_PLL_DIV_INT:
257 case CS42L42_PLL_CTL3:
258 case CS42L42_PLL_CAL_RATIO:
259 case CS42L42_PLL_CTL4:
260 case CS42L42_LOAD_DET_RCSTAT:
261 case CS42L42_LOAD_DET_DONE:
262 case CS42L42_LOAD_DET_EN:
263 case CS42L42_HSBIAS_SC_AUTOCTL:
264 case CS42L42_WAKE_CTL:
265 case CS42L42_ADC_DISABLE_MUTE:
266 case CS42L42_TIPSENSE_CTL:
267 case CS42L42_MISC_DET_CTL:
268 case CS42L42_MIC_DET_CTL1:
269 case CS42L42_MIC_DET_CTL2:
270 case CS42L42_DET_STATUS1:
271 case CS42L42_DET_STATUS2:
272 case CS42L42_DET_INT1_MASK:
273 case CS42L42_DET_INT2_MASK:
274 case CS42L42_HS_BIAS_CTL:
275 case CS42L42_ADC_CTL:
276 case CS42L42_ADC_VOLUME:
277 case CS42L42_ADC_WNF_HPF_CTL:
278 case CS42L42_DAC_CTL1:
279 case CS42L42_DAC_CTL2:
280 case CS42L42_HP_CTL:
281 case CS42L42_CLASSH_CTL:
282 case CS42L42_MIXER_CHA_VOL:
283 case CS42L42_MIXER_ADC_VOL:
284 case CS42L42_MIXER_CHB_VOL:
285 case CS42L42_EQ_COEF_IN0:
286 case CS42L42_EQ_COEF_IN1:
287 case CS42L42_EQ_COEF_IN2:
288 case CS42L42_EQ_COEF_IN3:
289 case CS42L42_EQ_COEF_RW:
290 case CS42L42_EQ_COEF_OUT0:
291 case CS42L42_EQ_COEF_OUT1:
292 case CS42L42_EQ_COEF_OUT2:
293 case CS42L42_EQ_COEF_OUT3:
294 case CS42L42_EQ_INIT_STAT:
295 case CS42L42_EQ_START_FILT:
296 case CS42L42_EQ_MUTE_CTL:
297 case CS42L42_SP_RX_CH_SEL:
298 case CS42L42_SP_RX_ISOC_CTL:
299 case CS42L42_SP_RX_FS:
300 case CS42l42_SPDIF_CH_SEL:
301 case CS42L42_SP_TX_ISOC_CTL:
302 case CS42L42_SP_TX_FS:
303 case CS42L42_SPDIF_SW_CTL1:
304 case CS42L42_SRC_SDIN_FS:
305 case CS42L42_SRC_SDOUT_FS:
306 case CS42L42_SPDIF_CTL1:
307 case CS42L42_SPDIF_CTL2:
308 case CS42L42_SPDIF_CTL3:
309 case CS42L42_SPDIF_CTL4:
310 case CS42L42_ASP_TX_SZ_EN:
311 case CS42L42_ASP_TX_CH_EN:
312 case CS42L42_ASP_TX_CH_AP_RES:
313 case CS42L42_ASP_TX_CH1_BIT_MSB:
314 case CS42L42_ASP_TX_CH1_BIT_LSB:
315 case CS42L42_ASP_TX_HIZ_DLY_CFG:
316 case CS42L42_ASP_TX_CH2_BIT_MSB:
317 case CS42L42_ASP_TX_CH2_BIT_LSB:
318 case CS42L42_ASP_RX_DAI0_EN:
319 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
320 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
321 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
322 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
323 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
324 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
325 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
326 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
327 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
328 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
329 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
330 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
331 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
332 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
333 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
334 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
335 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
336 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
337 case CS42L42_SUB_REVID:
338 return true;
339 default:
340 return false;
341 }
342 }
343
cs42l42_volatile_register(struct device * dev,unsigned int reg)344 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
345 {
346 switch (reg) {
347 case CS42L42_DEVID_AB:
348 case CS42L42_DEVID_CD:
349 case CS42L42_DEVID_E:
350 case CS42L42_MCLK_STATUS:
351 case CS42L42_TRSENSE_STATUS:
352 case CS42L42_HS_DET_STATUS:
353 case CS42L42_ADC_OVFL_STATUS:
354 case CS42L42_MIXER_STATUS:
355 case CS42L42_SRC_STATUS:
356 case CS42L42_ASP_RX_STATUS:
357 case CS42L42_ASP_TX_STATUS:
358 case CS42L42_CODEC_STATUS:
359 case CS42L42_DET_INT_STATUS1:
360 case CS42L42_DET_INT_STATUS2:
361 case CS42L42_SRCPL_INT_STATUS:
362 case CS42L42_VPMON_STATUS:
363 case CS42L42_PLL_LOCK_STATUS:
364 case CS42L42_TSRS_PLUG_STATUS:
365 case CS42L42_LOAD_DET_RCSTAT:
366 case CS42L42_LOAD_DET_DONE:
367 case CS42L42_DET_STATUS1:
368 case CS42L42_DET_STATUS2:
369 return true;
370 default:
371 return false;
372 }
373 }
374
375 static const struct regmap_range_cfg cs42l42_page_range = {
376 .name = "Pages",
377 .range_min = 0,
378 .range_max = CS42L42_MAX_REGISTER,
379 .selector_reg = CS42L42_PAGE_REGISTER,
380 .selector_mask = 0xff,
381 .selector_shift = 0,
382 .window_start = 0,
383 .window_len = 256,
384 };
385
386 static const struct regmap_config cs42l42_regmap = {
387 .reg_bits = 8,
388 .val_bits = 8,
389
390 .readable_reg = cs42l42_readable_register,
391 .volatile_reg = cs42l42_volatile_register,
392
393 .ranges = &cs42l42_page_range,
394 .num_ranges = 1,
395
396 .max_register = CS42L42_MAX_REGISTER,
397 .reg_defaults = cs42l42_reg_defaults,
398 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
399 .cache_type = REGCACHE_RBTREE,
400
401 .use_single_read = true,
402 .use_single_write = true,
403 };
404
405 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
406 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
407
408 static const char * const cs42l42_hpf_freq_text[] = {
409 "1.86Hz", "120Hz", "235Hz", "466Hz"
410 };
411
412 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
413 CS42L42_ADC_HPF_CF_SHIFT,
414 cs42l42_hpf_freq_text);
415
416 static const char * const cs42l42_wnf3_freq_text[] = {
417 "160Hz", "180Hz", "200Hz", "220Hz",
418 "240Hz", "260Hz", "280Hz", "300Hz"
419 };
420
421 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
422 CS42L42_ADC_WNF_CF_SHIFT,
423 cs42l42_wnf3_freq_text);
424
425 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
426 /* ADC Volume and Filter Controls */
427 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
428 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
429 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
430 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
431 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
432 CS42L42_ADC_INV_SHIFT, true, false),
433 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
434 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
435 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
436 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
437 CS42L42_ADC_WNF_EN_SHIFT, true, false),
438 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
439 CS42L42_ADC_HPF_EN_SHIFT, true, false),
440 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
441 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
442
443 /* DAC Volume and Filter Controls */
444 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
445 CS42L42_DACA_INV_SHIFT, true, false),
446 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
447 CS42L42_DACB_INV_SHIFT, true, false),
448 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
449 CS42L42_DAC_HPF_EN_SHIFT, true, false),
450 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
451 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
452 0x3f, 1, mixer_tlv)
453 };
454
cs42l42_hpdrv_evt(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)455 static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event)
457 {
458 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
459
460 if (event & SND_SOC_DAPM_POST_PMU) {
461 /* Enable the channels */
462 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
463 CS42L42_ASP_RX0_CH_EN_MASK,
464 (CS42L42_ASP_RX0_CH1_EN |
465 CS42L42_ASP_RX0_CH2_EN) <<
466 CS42L42_ASP_RX0_CH_EN_SHIFT);
467
468 /* Power up */
469 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
470 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
471 CS42L42_HP_PDN_MASK, 0);
472 } else if (event & SND_SOC_DAPM_PRE_PMD) {
473 /* Disable the channels */
474 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
475 CS42L42_ASP_RX0_CH_EN_MASK, 0);
476
477 /* Power down */
478 snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
479 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
480 CS42L42_HP_PDN_MASK,
481 CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
482 CS42L42_HP_PDN_MASK);
483 } else {
484 dev_err(component->dev, "Invalid event 0x%x\n", event);
485 }
486 return 0;
487 }
488
489 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
490 SND_SOC_DAPM_OUTPUT("HP"),
491 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
492 CS42L42_ASP_SCLK_EN_SHIFT, false),
493 SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
494 0, NULL, 0, cs42l42_hpdrv_evt,
495 SND_SOC_DAPM_POST_PMU |
496 SND_SOC_DAPM_PRE_PMD)
497 };
498
499 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
500 {"SDIN", NULL, "Playback"},
501 {"HPDRV", NULL, "SDIN"},
502 {"HP", NULL, "HPDRV"}
503 };
504
cs42l42_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)505 static int cs42l42_set_bias_level(struct snd_soc_component *component,
506 enum snd_soc_bias_level level)
507 {
508 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
509 int ret;
510
511 switch (level) {
512 case SND_SOC_BIAS_ON:
513 break;
514 case SND_SOC_BIAS_PREPARE:
515 break;
516 case SND_SOC_BIAS_STANDBY:
517 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
518 regcache_cache_only(cs42l42->regmap, false);
519 regcache_sync(cs42l42->regmap);
520 ret = regulator_bulk_enable(
521 ARRAY_SIZE(cs42l42->supplies),
522 cs42l42->supplies);
523 if (ret != 0) {
524 dev_err(component->dev,
525 "Failed to enable regulators: %d\n",
526 ret);
527 return ret;
528 }
529 }
530 break;
531 case SND_SOC_BIAS_OFF:
532
533 regcache_cache_only(cs42l42->regmap, true);
534 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
535 cs42l42->supplies);
536 break;
537 }
538
539 return 0;
540 }
541
cs42l42_component_probe(struct snd_soc_component * component)542 static int cs42l42_component_probe(struct snd_soc_component *component)
543 {
544 struct cs42l42_private *cs42l42 =
545 (struct cs42l42_private *)snd_soc_component_get_drvdata(component);
546
547 cs42l42->component = component;
548
549 return 0;
550 }
551
552 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
553 .probe = cs42l42_component_probe,
554 .set_bias_level = cs42l42_set_bias_level,
555 .dapm_widgets = cs42l42_dapm_widgets,
556 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
557 .dapm_routes = cs42l42_audio_map,
558 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
559 .controls = cs42l42_snd_controls,
560 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
561 .idle_bias_on = 1,
562 .endianness = 1,
563 .non_legacy_dai_naming = 1,
564 };
565
566 struct cs42l42_pll_params {
567 u32 sclk;
568 u8 mclk_div;
569 u8 mclk_src_sel;
570 u8 sclk_prediv;
571 u8 pll_div_int;
572 u32 pll_div_frac;
573 u8 pll_mode;
574 u8 pll_divout;
575 u32 mclk_int;
576 u8 pll_cal_ratio;
577 };
578
579 /*
580 * Common PLL Settings for given SCLK
581 * Table 4-5 from the Datasheet
582 */
583 static const struct cs42l42_pll_params pll_ratio_table[] = {
584 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
585 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
586 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
587 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
588 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
589 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
590 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
591 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
592 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
593 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
594 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
595 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
596 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
597 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
598 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
599 };
600
cs42l42_pll_config(struct snd_soc_component * component)601 static int cs42l42_pll_config(struct snd_soc_component *component)
602 {
603 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
604 int i;
605 u32 fsync;
606
607 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
608 if (pll_ratio_table[i].sclk == cs42l42->sclk) {
609 /* Configure the internal sample rate */
610 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
611 CS42L42_INTERNAL_FS_MASK,
612 ((pll_ratio_table[i].mclk_int !=
613 12000000) &&
614 (pll_ratio_table[i].mclk_int !=
615 24000000)) <<
616 CS42L42_INTERNAL_FS_SHIFT);
617 /* Set the MCLK src (PLL or SCLK) and the divide
618 * ratio
619 */
620 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
621 CS42L42_MCLK_SRC_SEL_MASK |
622 CS42L42_MCLKDIV_MASK,
623 (pll_ratio_table[i].mclk_src_sel
624 << CS42L42_MCLK_SRC_SEL_SHIFT) |
625 (pll_ratio_table[i].mclk_div <<
626 CS42L42_MCLKDIV_SHIFT));
627 /* Set up the LRCLK */
628 fsync = cs42l42->sclk / cs42l42->srate;
629 if (((fsync * cs42l42->srate) != cs42l42->sclk)
630 || ((fsync % 2) != 0)) {
631 dev_err(component->dev,
632 "Unsupported sclk %d/sample rate %d\n",
633 cs42l42->sclk,
634 cs42l42->srate);
635 return -EINVAL;
636 }
637 /* Set the LRCLK period */
638 snd_soc_component_update_bits(component,
639 CS42L42_FSYNC_P_LOWER,
640 CS42L42_FSYNC_PERIOD_MASK,
641 CS42L42_FRAC0_VAL(fsync - 1) <<
642 CS42L42_FSYNC_PERIOD_SHIFT);
643 snd_soc_component_update_bits(component,
644 CS42L42_FSYNC_P_UPPER,
645 CS42L42_FSYNC_PERIOD_MASK,
646 CS42L42_FRAC1_VAL(fsync - 1) <<
647 CS42L42_FSYNC_PERIOD_SHIFT);
648 /* Set the LRCLK to 50% duty cycle */
649 fsync = fsync / 2;
650 snd_soc_component_update_bits(component,
651 CS42L42_FSYNC_PW_LOWER,
652 CS42L42_FSYNC_PULSE_WIDTH_MASK,
653 CS42L42_FRAC0_VAL(fsync - 1) <<
654 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
655 snd_soc_component_update_bits(component,
656 CS42L42_FSYNC_PW_UPPER,
657 CS42L42_FSYNC_PULSE_WIDTH_MASK,
658 CS42L42_FRAC1_VAL(fsync - 1) <<
659 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
660 /* Set the sample rates (96k or lower) */
661 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
662 CS42L42_FS_EN_MASK,
663 (CS42L42_FS_EN_IASRC_96K |
664 CS42L42_FS_EN_OASRC_96K) <<
665 CS42L42_FS_EN_SHIFT);
666 /* Set the input/output internal MCLK clock ~12 MHz */
667 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
668 CS42L42_CLK_IASRC_SEL_MASK,
669 CS42L42_CLK_IASRC_SEL_12 <<
670 CS42L42_CLK_IASRC_SEL_SHIFT);
671 snd_soc_component_update_bits(component,
672 CS42L42_OUT_ASRC_CLK,
673 CS42L42_CLK_OASRC_SEL_MASK,
674 CS42L42_CLK_OASRC_SEL_12 <<
675 CS42L42_CLK_OASRC_SEL_SHIFT);
676 if (pll_ratio_table[i].mclk_src_sel == 0) {
677 /* Pass the clock straight through */
678 snd_soc_component_update_bits(component,
679 CS42L42_PLL_CTL1,
680 CS42L42_PLL_START_MASK, 0);
681 } else {
682 /* Configure PLL per table 4-5 */
683 snd_soc_component_update_bits(component,
684 CS42L42_PLL_DIV_CFG1,
685 CS42L42_SCLK_PREDIV_MASK,
686 pll_ratio_table[i].sclk_prediv
687 << CS42L42_SCLK_PREDIV_SHIFT);
688 snd_soc_component_update_bits(component,
689 CS42L42_PLL_DIV_INT,
690 CS42L42_PLL_DIV_INT_MASK,
691 pll_ratio_table[i].pll_div_int
692 << CS42L42_PLL_DIV_INT_SHIFT);
693 snd_soc_component_update_bits(component,
694 CS42L42_PLL_DIV_FRAC0,
695 CS42L42_PLL_DIV_FRAC_MASK,
696 CS42L42_FRAC0_VAL(
697 pll_ratio_table[i].pll_div_frac)
698 << CS42L42_PLL_DIV_FRAC_SHIFT);
699 snd_soc_component_update_bits(component,
700 CS42L42_PLL_DIV_FRAC1,
701 CS42L42_PLL_DIV_FRAC_MASK,
702 CS42L42_FRAC1_VAL(
703 pll_ratio_table[i].pll_div_frac)
704 << CS42L42_PLL_DIV_FRAC_SHIFT);
705 snd_soc_component_update_bits(component,
706 CS42L42_PLL_DIV_FRAC2,
707 CS42L42_PLL_DIV_FRAC_MASK,
708 CS42L42_FRAC2_VAL(
709 pll_ratio_table[i].pll_div_frac)
710 << CS42L42_PLL_DIV_FRAC_SHIFT);
711 snd_soc_component_update_bits(component,
712 CS42L42_PLL_CTL4,
713 CS42L42_PLL_MODE_MASK,
714 pll_ratio_table[i].pll_mode
715 << CS42L42_PLL_MODE_SHIFT);
716 snd_soc_component_update_bits(component,
717 CS42L42_PLL_CTL3,
718 CS42L42_PLL_DIVOUT_MASK,
719 pll_ratio_table[i].pll_divout
720 << CS42L42_PLL_DIVOUT_SHIFT);
721 snd_soc_component_update_bits(component,
722 CS42L42_PLL_CAL_RATIO,
723 CS42L42_PLL_CAL_RATIO_MASK,
724 pll_ratio_table[i].pll_cal_ratio
725 << CS42L42_PLL_CAL_RATIO_SHIFT);
726 }
727 return 0;
728 }
729 }
730
731 return -EINVAL;
732 }
733
cs42l42_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)734 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
735 {
736 struct snd_soc_component *component = codec_dai->component;
737 u32 asp_cfg_val = 0;
738
739 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
740 case SND_SOC_DAIFMT_CBS_CFM:
741 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
742 CS42L42_ASP_MODE_SHIFT;
743 break;
744 case SND_SOC_DAIFMT_CBS_CFS:
745 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
746 CS42L42_ASP_MODE_SHIFT;
747 break;
748 default:
749 return -EINVAL;
750 }
751
752 /* interface format */
753 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
754 case SND_SOC_DAIFMT_I2S:
755 /*
756 * 5050 mode, frame starts on falling edge of LRCLK,
757 * frame delayed by 1.0 SCLKs
758 */
759 snd_soc_component_update_bits(component,
760 CS42L42_ASP_FRM_CFG,
761 CS42L42_ASP_STP_MASK |
762 CS42L42_ASP_5050_MASK |
763 CS42L42_ASP_FSD_MASK,
764 CS42L42_ASP_5050_MASK |
765 (CS42L42_ASP_FSD_1_0 <<
766 CS42L42_ASP_FSD_SHIFT));
767 break;
768 default:
769 return -EINVAL;
770 }
771
772 /* Bitclock/frame inversion */
773 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
774 case SND_SOC_DAIFMT_NB_NF:
775 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
776 break;
777 case SND_SOC_DAIFMT_NB_IF:
778 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
779 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
780 break;
781 case SND_SOC_DAIFMT_IB_NF:
782 break;
783 case SND_SOC_DAIFMT_IB_IF:
784 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
785 break;
786 }
787
788 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
789 CS42L42_ASP_SCPOL_MASK |
790 CS42L42_ASP_LCPOL_MASK,
791 asp_cfg_val);
792
793 return 0;
794 }
795
cs42l42_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)796 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
797 struct snd_pcm_hw_params *params,
798 struct snd_soc_dai *dai)
799 {
800 struct snd_soc_component *component = dai->component;
801 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
802 unsigned int width = (params_width(params) / 8) - 1;
803 unsigned int val = 0;
804
805 cs42l42->srate = params_rate(params);
806
807 switch(substream->stream) {
808 case SNDRV_PCM_STREAM_PLAYBACK:
809 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
810 /* channel 1 on low LRCLK */
811 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
812 CS42L42_ASP_RX_CH_AP_MASK |
813 CS42L42_ASP_RX_CH_RES_MASK, val);
814 /* Channel 2 on high LRCLK */
815 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
816 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
817 CS42L42_ASP_RX_CH_AP_MASK |
818 CS42L42_ASP_RX_CH_RES_MASK, val);
819 break;
820 default:
821 break;
822 }
823
824 return cs42l42_pll_config(component);
825 }
826
cs42l42_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)827 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
828 int clk_id, unsigned int freq, int dir)
829 {
830 struct snd_soc_component *component = dai->component;
831 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
832
833 cs42l42->sclk = freq;
834
835 return 0;
836 }
837
cs42l42_mute(struct snd_soc_dai * dai,int mute,int direction)838 static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
839 {
840 struct snd_soc_component *component = dai->component;
841 unsigned int regval;
842 u8 fullScaleVol;
843
844 if (mute) {
845 /* Mark SCLK as not present to turn on the internal
846 * oscillator.
847 */
848 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
849 CS42L42_SCLK_PRESENT_MASK, 0);
850
851 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
852 CS42L42_PLL_START_MASK,
853 0 << CS42L42_PLL_START_SHIFT);
854
855 /* Mute the headphone */
856 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
857 CS42L42_HP_ANA_AMUTE_MASK |
858 CS42L42_HP_ANA_BMUTE_MASK,
859 CS42L42_HP_ANA_AMUTE_MASK |
860 CS42L42_HP_ANA_BMUTE_MASK);
861 } else {
862 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
863 CS42L42_PLL_START_MASK,
864 1 << CS42L42_PLL_START_SHIFT);
865 /* Read the headphone load */
866 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
867 if (((regval & CS42L42_RLA_STAT_MASK) >>
868 CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
869 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
870 } else {
871 fullScaleVol = 0;
872 }
873
874 /* Un-mute the headphone, set the full scale volume flag */
875 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
876 CS42L42_HP_ANA_AMUTE_MASK |
877 CS42L42_HP_ANA_BMUTE_MASK |
878 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
879
880 /* Mark SCLK as present, turn off internal oscillator */
881 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
882 CS42L42_SCLK_PRESENT_MASK,
883 CS42L42_SCLK_PRESENT_MASK);
884 }
885
886 return 0;
887 }
888
889 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
890 SNDRV_PCM_FMTBIT_S24_LE |\
891 SNDRV_PCM_FMTBIT_S32_LE )
892
893
894 static const struct snd_soc_dai_ops cs42l42_ops = {
895 .hw_params = cs42l42_pcm_hw_params,
896 .set_fmt = cs42l42_set_dai_fmt,
897 .set_sysclk = cs42l42_set_sysclk,
898 .mute_stream = cs42l42_mute,
899 .no_capture_mute = 1,
900 };
901
902 static struct snd_soc_dai_driver cs42l42_dai = {
903 .name = "cs42l42",
904 .playback = {
905 .stream_name = "Playback",
906 .channels_min = 1,
907 .channels_max = 2,
908 .rates = SNDRV_PCM_RATE_8000_192000,
909 .formats = CS42L42_FORMATS,
910 },
911 .capture = {
912 .stream_name = "Capture",
913 .channels_min = 1,
914 .channels_max = 2,
915 .rates = SNDRV_PCM_RATE_8000_192000,
916 .formats = CS42L42_FORMATS,
917 },
918 .ops = &cs42l42_ops,
919 };
920
cs42l42_process_hs_type_detect(struct cs42l42_private * cs42l42)921 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
922 {
923 unsigned int hs_det_status;
924 unsigned int int_status;
925
926 /* Mask the auto detect interrupt */
927 regmap_update_bits(cs42l42->regmap,
928 CS42L42_CODEC_INT_MASK,
929 CS42L42_PDN_DONE_MASK |
930 CS42L42_HSDET_AUTO_DONE_MASK,
931 (1 << CS42L42_PDN_DONE_SHIFT) |
932 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
933
934 /* Set hs detect to automatic, disabled mode */
935 regmap_update_bits(cs42l42->regmap,
936 CS42L42_HSDET_CTL2,
937 CS42L42_HSDET_CTRL_MASK |
938 CS42L42_HSDET_SET_MASK |
939 CS42L42_HSBIAS_REF_MASK |
940 CS42L42_HSDET_AUTO_TIME_MASK,
941 (2 << CS42L42_HSDET_CTRL_SHIFT) |
942 (2 << CS42L42_HSDET_SET_SHIFT) |
943 (0 << CS42L42_HSBIAS_REF_SHIFT) |
944 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
945
946 /* Read and save the hs detection result */
947 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
948
949 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
950 CS42L42_HSDET_TYPE_SHIFT;
951
952 /* Set up button detection */
953 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
954 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
955 /* Set auto HS bias settings to default */
956 regmap_update_bits(cs42l42->regmap,
957 CS42L42_HSBIAS_SC_AUTOCTL,
958 CS42L42_HSBIAS_SENSE_EN_MASK |
959 CS42L42_AUTO_HSBIAS_HIZ_MASK |
960 CS42L42_TIP_SENSE_EN_MASK |
961 CS42L42_HSBIAS_SENSE_TRIP_MASK,
962 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
963 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
964 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
965 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
966
967 /* Set up hs detect level sensitivity */
968 regmap_update_bits(cs42l42->regmap,
969 CS42L42_MIC_DET_CTL1,
970 CS42L42_LATCH_TO_VP_MASK |
971 CS42L42_EVENT_STAT_SEL_MASK |
972 CS42L42_HS_DET_LEVEL_MASK,
973 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
974 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
975 (cs42l42->bias_thresholds[0] <<
976 CS42L42_HS_DET_LEVEL_SHIFT));
977
978 /* Set auto HS bias settings to default */
979 regmap_update_bits(cs42l42->regmap,
980 CS42L42_HSBIAS_SC_AUTOCTL,
981 CS42L42_HSBIAS_SENSE_EN_MASK |
982 CS42L42_AUTO_HSBIAS_HIZ_MASK |
983 CS42L42_TIP_SENSE_EN_MASK |
984 CS42L42_HSBIAS_SENSE_TRIP_MASK,
985 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
986 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
987 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
988 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
989
990 /* Turn on level detect circuitry */
991 regmap_update_bits(cs42l42->regmap,
992 CS42L42_MISC_DET_CTL,
993 CS42L42_DETECT_MODE_MASK |
994 CS42L42_HSBIAS_CTL_MASK |
995 CS42L42_PDN_MIC_LVL_DET_MASK,
996 (0 << CS42L42_DETECT_MODE_SHIFT) |
997 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
998 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
999
1000 msleep(cs42l42->btn_det_init_dbnce);
1001
1002 /* Clear any button interrupts before unmasking them */
1003 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1004 &int_status);
1005
1006 /* Unmask button detect interrupts */
1007 regmap_update_bits(cs42l42->regmap,
1008 CS42L42_DET_INT2_MASK,
1009 CS42L42_M_DETECT_TF_MASK |
1010 CS42L42_M_DETECT_FT_MASK |
1011 CS42L42_M_HSBIAS_HIZ_MASK |
1012 CS42L42_M_SHORT_RLS_MASK |
1013 CS42L42_M_SHORT_DET_MASK,
1014 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1015 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1016 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1017 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1018 (1 << CS42L42_M_SHORT_DET_SHIFT));
1019 } else {
1020 /* Make sure button detect and HS bias circuits are off */
1021 regmap_update_bits(cs42l42->regmap,
1022 CS42L42_MISC_DET_CTL,
1023 CS42L42_DETECT_MODE_MASK |
1024 CS42L42_HSBIAS_CTL_MASK |
1025 CS42L42_PDN_MIC_LVL_DET_MASK,
1026 (0 << CS42L42_DETECT_MODE_SHIFT) |
1027 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1028 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1029 }
1030
1031 regmap_update_bits(cs42l42->regmap,
1032 CS42L42_DAC_CTL2,
1033 CS42L42_HPOUT_PULLDOWN_MASK |
1034 CS42L42_HPOUT_LOAD_MASK |
1035 CS42L42_HPOUT_CLAMP_MASK |
1036 CS42L42_DAC_HPF_EN_MASK |
1037 CS42L42_DAC_MON_EN_MASK,
1038 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1039 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1040 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1041 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1042 (0 << CS42L42_DAC_MON_EN_SHIFT));
1043
1044 /* Unmask tip sense interrupts */
1045 regmap_update_bits(cs42l42->regmap,
1046 CS42L42_TSRS_PLUG_INT_MASK,
1047 CS42L42_RS_PLUG_MASK |
1048 CS42L42_RS_UNPLUG_MASK |
1049 CS42L42_TS_PLUG_MASK |
1050 CS42L42_TS_UNPLUG_MASK,
1051 (1 << CS42L42_RS_PLUG_SHIFT) |
1052 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1053 (0 << CS42L42_TS_PLUG_SHIFT) |
1054 (0 << CS42L42_TS_UNPLUG_SHIFT));
1055 }
1056
cs42l42_init_hs_type_detect(struct cs42l42_private * cs42l42)1057 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1058 {
1059 /* Mask tip sense interrupts */
1060 regmap_update_bits(cs42l42->regmap,
1061 CS42L42_TSRS_PLUG_INT_MASK,
1062 CS42L42_RS_PLUG_MASK |
1063 CS42L42_RS_UNPLUG_MASK |
1064 CS42L42_TS_PLUG_MASK |
1065 CS42L42_TS_UNPLUG_MASK,
1066 (1 << CS42L42_RS_PLUG_SHIFT) |
1067 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1068 (1 << CS42L42_TS_PLUG_SHIFT) |
1069 (1 << CS42L42_TS_UNPLUG_SHIFT));
1070
1071 /* Make sure button detect and HS bias circuits are off */
1072 regmap_update_bits(cs42l42->regmap,
1073 CS42L42_MISC_DET_CTL,
1074 CS42L42_DETECT_MODE_MASK |
1075 CS42L42_HSBIAS_CTL_MASK |
1076 CS42L42_PDN_MIC_LVL_DET_MASK,
1077 (0 << CS42L42_DETECT_MODE_SHIFT) |
1078 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1079 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1080
1081 /* Set auto HS bias settings to default */
1082 regmap_update_bits(cs42l42->regmap,
1083 CS42L42_HSBIAS_SC_AUTOCTL,
1084 CS42L42_HSBIAS_SENSE_EN_MASK |
1085 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1086 CS42L42_TIP_SENSE_EN_MASK |
1087 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1088 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1089 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1090 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1091 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1092
1093 /* Set hs detect to manual, disabled mode */
1094 regmap_update_bits(cs42l42->regmap,
1095 CS42L42_HSDET_CTL2,
1096 CS42L42_HSDET_CTRL_MASK |
1097 CS42L42_HSDET_SET_MASK |
1098 CS42L42_HSBIAS_REF_MASK |
1099 CS42L42_HSDET_AUTO_TIME_MASK,
1100 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1101 (2 << CS42L42_HSDET_SET_SHIFT) |
1102 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1103 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1104
1105 regmap_update_bits(cs42l42->regmap,
1106 CS42L42_DAC_CTL2,
1107 CS42L42_HPOUT_PULLDOWN_MASK |
1108 CS42L42_HPOUT_LOAD_MASK |
1109 CS42L42_HPOUT_CLAMP_MASK |
1110 CS42L42_DAC_HPF_EN_MASK |
1111 CS42L42_DAC_MON_EN_MASK,
1112 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1113 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1114 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1115 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1116 (1 << CS42L42_DAC_MON_EN_SHIFT));
1117
1118 /* Power up HS bias to 2.7V */
1119 regmap_update_bits(cs42l42->regmap,
1120 CS42L42_MISC_DET_CTL,
1121 CS42L42_DETECT_MODE_MASK |
1122 CS42L42_HSBIAS_CTL_MASK |
1123 CS42L42_PDN_MIC_LVL_DET_MASK,
1124 (0 << CS42L42_DETECT_MODE_SHIFT) |
1125 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1126 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1127
1128 /* Wait for HS bias to ramp up */
1129 msleep(cs42l42->hs_bias_ramp_time);
1130
1131 /* Unmask auto detect interrupt */
1132 regmap_update_bits(cs42l42->regmap,
1133 CS42L42_CODEC_INT_MASK,
1134 CS42L42_PDN_DONE_MASK |
1135 CS42L42_HSDET_AUTO_DONE_MASK,
1136 (1 << CS42L42_PDN_DONE_SHIFT) |
1137 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1138
1139 /* Set hs detect to automatic, enabled mode */
1140 regmap_update_bits(cs42l42->regmap,
1141 CS42L42_HSDET_CTL2,
1142 CS42L42_HSDET_CTRL_MASK |
1143 CS42L42_HSDET_SET_MASK |
1144 CS42L42_HSBIAS_REF_MASK |
1145 CS42L42_HSDET_AUTO_TIME_MASK,
1146 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1147 (2 << CS42L42_HSDET_SET_SHIFT) |
1148 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1149 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1150 }
1151
cs42l42_cancel_hs_type_detect(struct cs42l42_private * cs42l42)1152 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1153 {
1154 /* Mask button detect interrupts */
1155 regmap_update_bits(cs42l42->regmap,
1156 CS42L42_DET_INT2_MASK,
1157 CS42L42_M_DETECT_TF_MASK |
1158 CS42L42_M_DETECT_FT_MASK |
1159 CS42L42_M_HSBIAS_HIZ_MASK |
1160 CS42L42_M_SHORT_RLS_MASK |
1161 CS42L42_M_SHORT_DET_MASK,
1162 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1163 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1164 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1165 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1166 (1 << CS42L42_M_SHORT_DET_SHIFT));
1167
1168 /* Ground HS bias */
1169 regmap_update_bits(cs42l42->regmap,
1170 CS42L42_MISC_DET_CTL,
1171 CS42L42_DETECT_MODE_MASK |
1172 CS42L42_HSBIAS_CTL_MASK |
1173 CS42L42_PDN_MIC_LVL_DET_MASK,
1174 (0 << CS42L42_DETECT_MODE_SHIFT) |
1175 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1176 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1177
1178 /* Set auto HS bias settings to default */
1179 regmap_update_bits(cs42l42->regmap,
1180 CS42L42_HSBIAS_SC_AUTOCTL,
1181 CS42L42_HSBIAS_SENSE_EN_MASK |
1182 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1183 CS42L42_TIP_SENSE_EN_MASK |
1184 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1185 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1186 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1187 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1188 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1189
1190 /* Set hs detect to manual, disabled mode */
1191 regmap_update_bits(cs42l42->regmap,
1192 CS42L42_HSDET_CTL2,
1193 CS42L42_HSDET_CTRL_MASK |
1194 CS42L42_HSDET_SET_MASK |
1195 CS42L42_HSBIAS_REF_MASK |
1196 CS42L42_HSDET_AUTO_TIME_MASK,
1197 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1198 (2 << CS42L42_HSDET_SET_SHIFT) |
1199 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1200 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1201 }
1202
cs42l42_handle_button_press(struct cs42l42_private * cs42l42)1203 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1204 {
1205 int bias_level;
1206 unsigned int detect_status;
1207
1208 /* Mask button detect interrupts */
1209 regmap_update_bits(cs42l42->regmap,
1210 CS42L42_DET_INT2_MASK,
1211 CS42L42_M_DETECT_TF_MASK |
1212 CS42L42_M_DETECT_FT_MASK |
1213 CS42L42_M_HSBIAS_HIZ_MASK |
1214 CS42L42_M_SHORT_RLS_MASK |
1215 CS42L42_M_SHORT_DET_MASK,
1216 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1217 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1218 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1219 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1220 (1 << CS42L42_M_SHORT_DET_SHIFT));
1221
1222 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1223 cs42l42->btn_det_event_dbnce * 2000);
1224
1225 /* Test all 4 level detect biases */
1226 bias_level = 1;
1227 do {
1228 /* Adjust button detect level sensitivity */
1229 regmap_update_bits(cs42l42->regmap,
1230 CS42L42_MIC_DET_CTL1,
1231 CS42L42_LATCH_TO_VP_MASK |
1232 CS42L42_EVENT_STAT_SEL_MASK |
1233 CS42L42_HS_DET_LEVEL_MASK,
1234 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1235 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1236 (cs42l42->bias_thresholds[bias_level] <<
1237 CS42L42_HS_DET_LEVEL_SHIFT));
1238
1239 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1240 &detect_status);
1241 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1242 (++bias_level < CS42L42_NUM_BIASES));
1243
1244 switch (bias_level) {
1245 case 1: /* Function C button press */
1246 dev_dbg(cs42l42->component->dev, "Function C button press\n");
1247 break;
1248 case 2: /* Function B button press */
1249 dev_dbg(cs42l42->component->dev, "Function B button press\n");
1250 break;
1251 case 3: /* Function D button press */
1252 dev_dbg(cs42l42->component->dev, "Function D button press\n");
1253 break;
1254 case 4: /* Function A button press */
1255 dev_dbg(cs42l42->component->dev, "Function A button press\n");
1256 break;
1257 }
1258
1259 /* Set button detect level sensitivity back to default */
1260 regmap_update_bits(cs42l42->regmap,
1261 CS42L42_MIC_DET_CTL1,
1262 CS42L42_LATCH_TO_VP_MASK |
1263 CS42L42_EVENT_STAT_SEL_MASK |
1264 CS42L42_HS_DET_LEVEL_MASK,
1265 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1266 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1267 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1268
1269 /* Clear any button interrupts before unmasking them */
1270 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1271 &detect_status);
1272
1273 /* Unmask button detect interrupts */
1274 regmap_update_bits(cs42l42->regmap,
1275 CS42L42_DET_INT2_MASK,
1276 CS42L42_M_DETECT_TF_MASK |
1277 CS42L42_M_DETECT_FT_MASK |
1278 CS42L42_M_HSBIAS_HIZ_MASK |
1279 CS42L42_M_SHORT_RLS_MASK |
1280 CS42L42_M_SHORT_DET_MASK,
1281 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1282 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1283 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1284 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1285 (1 << CS42L42_M_SHORT_DET_SHIFT));
1286 }
1287
1288 struct cs42l42_irq_params {
1289 u16 status_addr;
1290 u16 mask_addr;
1291 u8 mask;
1292 };
1293
1294 static const struct cs42l42_irq_params irq_params_table[] = {
1295 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1296 CS42L42_ADC_OVFL_VAL_MASK},
1297 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1298 CS42L42_MIXER_VAL_MASK},
1299 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1300 CS42L42_SRC_VAL_MASK},
1301 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1302 CS42L42_ASP_RX_VAL_MASK},
1303 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1304 CS42L42_ASP_TX_VAL_MASK},
1305 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1306 CS42L42_CODEC_VAL_MASK},
1307 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1308 CS42L42_DET_INT_VAL1_MASK},
1309 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1310 CS42L42_DET_INT_VAL2_MASK},
1311 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1312 CS42L42_SRCPL_VAL_MASK},
1313 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1314 CS42L42_VPMON_VAL_MASK},
1315 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1316 CS42L42_PLL_LOCK_VAL_MASK},
1317 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1318 CS42L42_TSRS_PLUG_VAL_MASK}
1319 };
1320
cs42l42_irq_thread(int irq,void * data)1321 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1322 {
1323 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1324 struct snd_soc_component *component = cs42l42->component;
1325 unsigned int stickies[12];
1326 unsigned int masks[12];
1327 unsigned int current_plug_status;
1328 unsigned int current_button_status;
1329 unsigned int i;
1330
1331 /* Read sticky registers to clear interurpt */
1332 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1333 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1334 &(stickies[i]));
1335 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1336 &(masks[i]));
1337 stickies[i] = stickies[i] & (~masks[i]) &
1338 irq_params_table[i].mask;
1339 }
1340
1341 /* Read tip sense status before handling type detect */
1342 current_plug_status = (stickies[11] &
1343 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1344 CS42L42_TS_PLUG_SHIFT;
1345
1346 /* Read button sense status */
1347 current_button_status = stickies[7] &
1348 (CS42L42_M_DETECT_TF_MASK |
1349 CS42L42_M_DETECT_FT_MASK |
1350 CS42L42_M_HSBIAS_HIZ_MASK);
1351
1352 /* Check auto-detect status */
1353 if ((~masks[5]) & irq_params_table[5].mask) {
1354 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1355 cs42l42_process_hs_type_detect(cs42l42);
1356 dev_dbg(component->dev,
1357 "Auto detect done (%d)\n",
1358 cs42l42->hs_type);
1359 }
1360 }
1361
1362 /* Check tip sense status */
1363 if ((~masks[11]) & irq_params_table[11].mask) {
1364 switch (current_plug_status) {
1365 case CS42L42_TS_PLUG:
1366 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1367 cs42l42->plug_state = CS42L42_TS_PLUG;
1368 cs42l42_init_hs_type_detect(cs42l42);
1369 }
1370 break;
1371
1372 case CS42L42_TS_UNPLUG:
1373 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1374 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1375 cs42l42_cancel_hs_type_detect(cs42l42);
1376 dev_dbg(component->dev,
1377 "Unplug event\n");
1378 }
1379 break;
1380
1381 default:
1382 if (cs42l42->plug_state != CS42L42_TS_TRANS)
1383 cs42l42->plug_state = CS42L42_TS_TRANS;
1384 }
1385 }
1386
1387 /* Check button detect status */
1388 if ((~masks[7]) & irq_params_table[7].mask) {
1389 if (!(current_button_status &
1390 CS42L42_M_HSBIAS_HIZ_MASK)) {
1391
1392 if (current_button_status &
1393 CS42L42_M_DETECT_TF_MASK) {
1394 dev_dbg(component->dev,
1395 "Button released\n");
1396 } else if (current_button_status &
1397 CS42L42_M_DETECT_FT_MASK) {
1398 cs42l42_handle_button_press(cs42l42);
1399 }
1400 }
1401 }
1402
1403 return IRQ_HANDLED;
1404 }
1405
cs42l42_set_interrupt_masks(struct cs42l42_private * cs42l42)1406 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1407 {
1408 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1409 CS42L42_ADC_OVFL_MASK,
1410 (1 << CS42L42_ADC_OVFL_SHIFT));
1411
1412 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1413 CS42L42_MIX_CHB_OVFL_MASK |
1414 CS42L42_MIX_CHA_OVFL_MASK |
1415 CS42L42_EQ_OVFL_MASK |
1416 CS42L42_EQ_BIQUAD_OVFL_MASK,
1417 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1418 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1419 (1 << CS42L42_EQ_OVFL_SHIFT) |
1420 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1421
1422 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1423 CS42L42_SRC_ILK_MASK |
1424 CS42L42_SRC_OLK_MASK |
1425 CS42L42_SRC_IUNLK_MASK |
1426 CS42L42_SRC_OUNLK_MASK,
1427 (1 << CS42L42_SRC_ILK_SHIFT) |
1428 (1 << CS42L42_SRC_OLK_SHIFT) |
1429 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1430 (1 << CS42L42_SRC_OUNLK_SHIFT));
1431
1432 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1433 CS42L42_ASPRX_NOLRCK_MASK |
1434 CS42L42_ASPRX_EARLY_MASK |
1435 CS42L42_ASPRX_LATE_MASK |
1436 CS42L42_ASPRX_ERROR_MASK |
1437 CS42L42_ASPRX_OVLD_MASK,
1438 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1439 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1440 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1441 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1442 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1443
1444 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1445 CS42L42_ASPTX_NOLRCK_MASK |
1446 CS42L42_ASPTX_EARLY_MASK |
1447 CS42L42_ASPTX_LATE_MASK |
1448 CS42L42_ASPTX_SMERROR_MASK,
1449 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1450 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1451 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1452 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1453
1454 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1455 CS42L42_PDN_DONE_MASK |
1456 CS42L42_HSDET_AUTO_DONE_MASK,
1457 (1 << CS42L42_PDN_DONE_SHIFT) |
1458 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1459
1460 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1461 CS42L42_SRCPL_ADC_LK_MASK |
1462 CS42L42_SRCPL_DAC_LK_MASK |
1463 CS42L42_SRCPL_ADC_UNLK_MASK |
1464 CS42L42_SRCPL_DAC_UNLK_MASK,
1465 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1466 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1467 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1468 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1469
1470 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1471 CS42L42_TIP_SENSE_UNPLUG_MASK |
1472 CS42L42_TIP_SENSE_PLUG_MASK |
1473 CS42L42_HSBIAS_SENSE_MASK,
1474 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1475 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1476 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1477
1478 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1479 CS42L42_M_DETECT_TF_MASK |
1480 CS42L42_M_DETECT_FT_MASK |
1481 CS42L42_M_HSBIAS_HIZ_MASK |
1482 CS42L42_M_SHORT_RLS_MASK |
1483 CS42L42_M_SHORT_DET_MASK,
1484 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1485 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1486 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1487 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1488 (1 << CS42L42_M_SHORT_DET_SHIFT));
1489
1490 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1491 CS42L42_VPMON_MASK,
1492 (1 << CS42L42_VPMON_SHIFT));
1493
1494 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1495 CS42L42_PLL_LOCK_MASK,
1496 (1 << CS42L42_PLL_LOCK_SHIFT));
1497
1498 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1499 CS42L42_RS_PLUG_MASK |
1500 CS42L42_RS_UNPLUG_MASK |
1501 CS42L42_TS_PLUG_MASK |
1502 CS42L42_TS_UNPLUG_MASK,
1503 (1 << CS42L42_RS_PLUG_SHIFT) |
1504 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1505 (0 << CS42L42_TS_PLUG_SHIFT) |
1506 (0 << CS42L42_TS_UNPLUG_SHIFT));
1507 }
1508
cs42l42_setup_hs_type_detect(struct cs42l42_private * cs42l42)1509 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1510 {
1511 unsigned int reg;
1512
1513 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1514
1515 /* Latch analog controls to VP power domain */
1516 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1517 CS42L42_LATCH_TO_VP_MASK |
1518 CS42L42_EVENT_STAT_SEL_MASK |
1519 CS42L42_HS_DET_LEVEL_MASK,
1520 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1521 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1522 (cs42l42->bias_thresholds[0] <<
1523 CS42L42_HS_DET_LEVEL_SHIFT));
1524
1525 /* Remove ground noise-suppression clamps */
1526 regmap_update_bits(cs42l42->regmap,
1527 CS42L42_HS_CLAMP_DISABLE,
1528 CS42L42_HS_CLAMP_DISABLE_MASK,
1529 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1530
1531 /* Enable the tip sense circuit */
1532 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1533 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1534
1535 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1536 CS42L42_TIP_SENSE_CTRL_MASK |
1537 CS42L42_TIP_SENSE_INV_MASK |
1538 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1539 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1540 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1541 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1542
1543 /* Save the initial status of the tip sense */
1544 regmap_read(cs42l42->regmap,
1545 CS42L42_TSRS_PLUG_STATUS,
1546 ®);
1547 cs42l42->plug_state = (((char) reg) &
1548 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1549 CS42L42_TS_PLUG_SHIFT;
1550 }
1551
1552 static const unsigned int threshold_defaults[] = {
1553 CS42L42_HS_DET_LEVEL_15,
1554 CS42L42_HS_DET_LEVEL_8,
1555 CS42L42_HS_DET_LEVEL_4,
1556 CS42L42_HS_DET_LEVEL_1
1557 };
1558
cs42l42_handle_device_data(struct device * dev,struct cs42l42_private * cs42l42)1559 static int cs42l42_handle_device_data(struct device *dev,
1560 struct cs42l42_private *cs42l42)
1561 {
1562 unsigned int val;
1563 u32 thresholds[CS42L42_NUM_BIASES];
1564 int ret;
1565 int i;
1566
1567 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1568 if (!ret) {
1569 switch (val) {
1570 case CS42L42_TS_INV_EN:
1571 case CS42L42_TS_INV_DIS:
1572 cs42l42->ts_inv = val;
1573 break;
1574 default:
1575 dev_err(dev,
1576 "Wrong cirrus,ts-inv DT value %d\n",
1577 val);
1578 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1579 }
1580 } else {
1581 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1582 }
1583
1584 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1585 if (!ret) {
1586 switch (val) {
1587 case CS42L42_TS_DBNCE_0:
1588 case CS42L42_TS_DBNCE_125:
1589 case CS42L42_TS_DBNCE_250:
1590 case CS42L42_TS_DBNCE_500:
1591 case CS42L42_TS_DBNCE_750:
1592 case CS42L42_TS_DBNCE_1000:
1593 case CS42L42_TS_DBNCE_1250:
1594 case CS42L42_TS_DBNCE_1500:
1595 cs42l42->ts_dbnc_rise = val;
1596 break;
1597 default:
1598 dev_err(dev,
1599 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1600 val);
1601 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1602 }
1603 } else {
1604 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1605 }
1606
1607 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1608 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1609 (cs42l42->ts_dbnc_rise <<
1610 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1611
1612 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1613 if (!ret) {
1614 switch (val) {
1615 case CS42L42_TS_DBNCE_0:
1616 case CS42L42_TS_DBNCE_125:
1617 case CS42L42_TS_DBNCE_250:
1618 case CS42L42_TS_DBNCE_500:
1619 case CS42L42_TS_DBNCE_750:
1620 case CS42L42_TS_DBNCE_1000:
1621 case CS42L42_TS_DBNCE_1250:
1622 case CS42L42_TS_DBNCE_1500:
1623 cs42l42->ts_dbnc_fall = val;
1624 break;
1625 default:
1626 dev_err(dev,
1627 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1628 val);
1629 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1630 }
1631 } else {
1632 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1633 }
1634
1635 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1636 CS42L42_TS_FALL_DBNCE_TIME_MASK,
1637 (cs42l42->ts_dbnc_fall <<
1638 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1639
1640 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1641 if (!ret) {
1642 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1643 cs42l42->btn_det_init_dbnce = val;
1644 else {
1645 dev_err(dev,
1646 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1647 val);
1648 cs42l42->btn_det_init_dbnce =
1649 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1650 }
1651 } else {
1652 cs42l42->btn_det_init_dbnce =
1653 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1654 }
1655
1656 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1657 if (!ret) {
1658 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1659 cs42l42->btn_det_event_dbnce = val;
1660 else {
1661 dev_err(dev,
1662 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1663 cs42l42->btn_det_event_dbnce =
1664 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1665 }
1666 } else {
1667 cs42l42->btn_det_event_dbnce =
1668 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1669 }
1670
1671 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1672 thresholds, ARRAY_SIZE(thresholds));
1673 if (!ret) {
1674 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1675 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1676 cs42l42->bias_thresholds[i] = thresholds[i];
1677 else {
1678 dev_err(dev,
1679 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1680 thresholds[i]);
1681 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1682 }
1683 }
1684 } else {
1685 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1686 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1687 }
1688
1689 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
1690 if (!ret) {
1691 switch (val) {
1692 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
1693 cs42l42->hs_bias_ramp_rate = val;
1694 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
1695 break;
1696 case CS42L42_HSBIAS_RAMP_FAST:
1697 cs42l42->hs_bias_ramp_rate = val;
1698 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
1699 break;
1700 case CS42L42_HSBIAS_RAMP_SLOW:
1701 cs42l42->hs_bias_ramp_rate = val;
1702 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1703 break;
1704 case CS42L42_HSBIAS_RAMP_SLOWEST:
1705 cs42l42->hs_bias_ramp_rate = val;
1706 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
1707 break;
1708 default:
1709 dev_err(dev,
1710 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
1711 val);
1712 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1713 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1714 }
1715 } else {
1716 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
1717 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
1718 }
1719
1720 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
1721 CS42L42_HSBIAS_RAMP_MASK,
1722 (cs42l42->hs_bias_ramp_rate <<
1723 CS42L42_HSBIAS_RAMP_SHIFT));
1724
1725 return 0;
1726 }
1727
cs42l42_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)1728 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
1729 const struct i2c_device_id *id)
1730 {
1731 struct cs42l42_private *cs42l42;
1732 int ret, i;
1733 unsigned int devid = 0;
1734 unsigned int reg;
1735
1736 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
1737 GFP_KERNEL);
1738 if (!cs42l42)
1739 return -ENOMEM;
1740
1741 i2c_set_clientdata(i2c_client, cs42l42);
1742
1743 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
1744 if (IS_ERR(cs42l42->regmap)) {
1745 ret = PTR_ERR(cs42l42->regmap);
1746 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1747 return ret;
1748 }
1749
1750 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
1751 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
1752
1753 ret = devm_regulator_bulk_get(&i2c_client->dev,
1754 ARRAY_SIZE(cs42l42->supplies),
1755 cs42l42->supplies);
1756 if (ret != 0) {
1757 dev_err(&i2c_client->dev,
1758 "Failed to request supplies: %d\n", ret);
1759 return ret;
1760 }
1761
1762 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1763 cs42l42->supplies);
1764 if (ret != 0) {
1765 dev_err(&i2c_client->dev,
1766 "Failed to enable supplies: %d\n", ret);
1767 return ret;
1768 }
1769
1770 /* Reset the Device */
1771 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1772 "reset", GPIOD_OUT_LOW);
1773 if (IS_ERR(cs42l42->reset_gpio)) {
1774 ret = PTR_ERR(cs42l42->reset_gpio);
1775 goto err_disable;
1776 }
1777
1778 if (cs42l42->reset_gpio) {
1779 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
1780 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1781 }
1782 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1783
1784 /* Request IRQ */
1785 ret = devm_request_threaded_irq(&i2c_client->dev,
1786 i2c_client->irq,
1787 NULL, cs42l42_irq_thread,
1788 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1789 "cs42l42", cs42l42);
1790 if (ret == -EPROBE_DEFER)
1791 goto err_disable;
1792 else if (ret != 0)
1793 dev_err(&i2c_client->dev,
1794 "Failed to request IRQ: %d\n", ret);
1795
1796 /* initialize codec */
1797 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®);
1798 devid = (reg & 0xFF) << 12;
1799
1800 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®);
1801 devid |= (reg & 0xFF) << 4;
1802
1803 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®);
1804 devid |= (reg & 0xF0) >> 4;
1805
1806 if (devid != CS42L42_CHIP_ID) {
1807 ret = -ENODEV;
1808 dev_err(&i2c_client->dev,
1809 "CS42L42 Device ID (%X). Expected %X\n",
1810 devid, CS42L42_CHIP_ID);
1811 goto err_disable;
1812 }
1813
1814 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
1815 if (ret < 0) {
1816 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1817 goto err_disable;
1818 }
1819
1820 dev_info(&i2c_client->dev,
1821 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
1822
1823 /* Power up the codec */
1824 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
1825 CS42L42_ASP_DAO_PDN_MASK |
1826 CS42L42_ASP_DAI_PDN_MASK |
1827 CS42L42_MIXER_PDN_MASK |
1828 CS42L42_EQ_PDN_MASK |
1829 CS42L42_HP_PDN_MASK |
1830 CS42L42_ADC_PDN_MASK |
1831 CS42L42_PDN_ALL_MASK,
1832 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
1833 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
1834 (1 << CS42L42_MIXER_PDN_SHIFT) |
1835 (1 << CS42L42_EQ_PDN_SHIFT) |
1836 (1 << CS42L42_HP_PDN_SHIFT) |
1837 (1 << CS42L42_ADC_PDN_SHIFT) |
1838 (0 << CS42L42_PDN_ALL_SHIFT));
1839
1840 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
1841 if (ret != 0)
1842 goto err_disable;
1843
1844 /* Setup headset detection */
1845 cs42l42_setup_hs_type_detect(cs42l42);
1846
1847 /* Mask/Unmask Interrupts */
1848 cs42l42_set_interrupt_masks(cs42l42);
1849
1850 /* Register codec for machine driver */
1851 ret = devm_snd_soc_register_component(&i2c_client->dev,
1852 &soc_component_dev_cs42l42, &cs42l42_dai, 1);
1853 if (ret < 0)
1854 goto err_disable;
1855 return 0;
1856
1857 err_disable:
1858 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1859 cs42l42->supplies);
1860 return ret;
1861 }
1862
cs42l42_i2c_remove(struct i2c_client * i2c_client)1863 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
1864 {
1865 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
1866
1867 /* Hold down reset */
1868 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1869
1870 return 0;
1871 }
1872
1873 #ifdef CONFIG_PM
cs42l42_runtime_suspend(struct device * dev)1874 static int cs42l42_runtime_suspend(struct device *dev)
1875 {
1876 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1877
1878 regcache_cache_only(cs42l42->regmap, true);
1879 regcache_mark_dirty(cs42l42->regmap);
1880
1881 /* Hold down reset */
1882 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
1883
1884 /* remove power */
1885 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
1886 cs42l42->supplies);
1887
1888 return 0;
1889 }
1890
cs42l42_runtime_resume(struct device * dev)1891 static int cs42l42_runtime_resume(struct device *dev)
1892 {
1893 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
1894 int ret;
1895
1896 /* Enable power */
1897 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
1898 cs42l42->supplies);
1899 if (ret != 0) {
1900 dev_err(dev, "Failed to enable supplies: %d\n",
1901 ret);
1902 return ret;
1903 }
1904
1905 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
1906 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
1907
1908 regcache_cache_only(cs42l42->regmap, false);
1909 regcache_sync(cs42l42->regmap);
1910
1911 return 0;
1912 }
1913 #endif
1914
1915 static const struct dev_pm_ops cs42l42_runtime_pm = {
1916 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume,
1917 NULL)
1918 };
1919
1920 static const struct of_device_id cs42l42_of_match[] = {
1921 { .compatible = "cirrus,cs42l42", },
1922 {},
1923 };
1924 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
1925
1926
1927 static const struct i2c_device_id cs42l42_id[] = {
1928 {"cs42l42", 0},
1929 {}
1930 };
1931
1932 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
1933
1934 static struct i2c_driver cs42l42_i2c_driver = {
1935 .driver = {
1936 .name = "cs42l42",
1937 .pm = &cs42l42_runtime_pm,
1938 .of_match_table = cs42l42_of_match,
1939 },
1940 .id_table = cs42l42_id,
1941 .probe = cs42l42_i2c_probe,
1942 .remove = cs42l42_i2c_remove,
1943 };
1944
1945 module_i2c_driver(cs42l42_i2c_driver);
1946
1947 MODULE_DESCRIPTION("ASoC CS42L42 driver");
1948 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1949 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1950 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
1951 MODULE_LICENSE("GPL");
1952