1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Author: Timur Tabi <timur@freescale.com>
6 //
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
8 //
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
10 //
11 // The i.MX SSI core has some nasty limitations in AC97 mode. While most
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
14 // which slots we want to receive. The WM9712 with which this driver
15 // was developed with always sends GPIO status data in slot 12 which
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
18 // from 48000Hz not every frame has valid receive data, so the ratio
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
20 // able to handle this, hence this driver only works with 48000Hz sampling
21 // rate.
22 // Reading and writing AC97 registers is another challenge. The core
23 // provides us status bits when the read register is updated with *another*
24 // value. When we read the same register two times (and the register still
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
27
28 #include <linux/init.h>
29 #include <linux/io.h>
30 #include <linux/module.h>
31 #include <linux/interrupt.h>
32 #include <linux/clk.h>
33 #include <linux/ctype.h>
34 #include <linux/device.h>
35 #include <linux/delay.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/of.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/of_platform.h>
43
44 #include <sound/core.h>
45 #include <sound/pcm.h>
46 #include <sound/pcm_params.h>
47 #include <sound/initval.h>
48 #include <sound/soc.h>
49 #include <sound/dmaengine_pcm.h>
50
51 #include "fsl_ssi.h"
52 #include "imx-pcm.h"
53
54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
55 #define RX 0
56 #define TX 1
57
58 /**
59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
60 *
61 * The SSI has a limitation in that the samples must be in the same byte
62 * order as the host CPU. This is because when multiple bytes are written
63 * to the STX register, the bytes and bits must be written in the same
64 * order. The STX is a shift register, so all the bits need to be aligned
65 * (bit-endianness must match byte-endianness). Processors typically write
66 * the bits within a byte in the same order that the bytes of a word are
67 * written in. So if the host CPU is big-endian, then only big-endian
68 * samples will be written to STX properly.
69 */
70 #ifdef __BIG_ENDIAN
71 #define FSLSSI_I2S_FORMATS \
72 (SNDRV_PCM_FMTBIT_S8 | \
73 SNDRV_PCM_FMTBIT_S16_BE | \
74 SNDRV_PCM_FMTBIT_S18_3BE | \
75 SNDRV_PCM_FMTBIT_S20_3BE | \
76 SNDRV_PCM_FMTBIT_S24_3BE | \
77 SNDRV_PCM_FMTBIT_S24_BE)
78 #else
79 #define FSLSSI_I2S_FORMATS \
80 (SNDRV_PCM_FMTBIT_S8 | \
81 SNDRV_PCM_FMTBIT_S16_LE | \
82 SNDRV_PCM_FMTBIT_S18_3LE | \
83 SNDRV_PCM_FMTBIT_S20_3LE | \
84 SNDRV_PCM_FMTBIT_S24_3LE | \
85 SNDRV_PCM_FMTBIT_S24_LE)
86 #endif
87
88 /*
89 * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
90 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
91 * - Also have NB_NF to mark these two clocks will not be inverted
92 */
93 #define FSLSSI_AC97_DAIFMT \
94 (SND_SOC_DAIFMT_AC97 | \
95 SND_SOC_DAIFMT_CBM_CFS | \
96 SND_SOC_DAIFMT_NB_NF)
97
98 #define FSLSSI_SIER_DBG_RX_FLAGS \
99 (SSI_SIER_RFF0_EN | \
100 SSI_SIER_RLS_EN | \
101 SSI_SIER_RFS_EN | \
102 SSI_SIER_ROE0_EN | \
103 SSI_SIER_RFRC_EN)
104 #define FSLSSI_SIER_DBG_TX_FLAGS \
105 (SSI_SIER_TFE0_EN | \
106 SSI_SIER_TLS_EN | \
107 SSI_SIER_TFS_EN | \
108 SSI_SIER_TUE0_EN | \
109 SSI_SIER_TFRC_EN)
110
111 enum fsl_ssi_type {
112 FSL_SSI_MCP8610,
113 FSL_SSI_MX21,
114 FSL_SSI_MX35,
115 FSL_SSI_MX51,
116 };
117
118 struct fsl_ssi_regvals {
119 u32 sier;
120 u32 srcr;
121 u32 stcr;
122 u32 scr;
123 };
124
fsl_ssi_readable_reg(struct device * dev,unsigned int reg)125 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
126 {
127 switch (reg) {
128 case REG_SSI_SACCEN:
129 case REG_SSI_SACCDIS:
130 return false;
131 default:
132 return true;
133 }
134 }
135
fsl_ssi_volatile_reg(struct device * dev,unsigned int reg)136 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
137 {
138 switch (reg) {
139 case REG_SSI_STX0:
140 case REG_SSI_STX1:
141 case REG_SSI_SRX0:
142 case REG_SSI_SRX1:
143 case REG_SSI_SISR:
144 case REG_SSI_SFCSR:
145 case REG_SSI_SACNT:
146 case REG_SSI_SACADD:
147 case REG_SSI_SACDAT:
148 case REG_SSI_SATAG:
149 case REG_SSI_SACCST:
150 case REG_SSI_SOR:
151 return true;
152 default:
153 return false;
154 }
155 }
156
fsl_ssi_precious_reg(struct device * dev,unsigned int reg)157 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
158 {
159 switch (reg) {
160 case REG_SSI_SRX0:
161 case REG_SSI_SRX1:
162 case REG_SSI_SISR:
163 case REG_SSI_SACADD:
164 case REG_SSI_SACDAT:
165 case REG_SSI_SATAG:
166 return true;
167 default:
168 return false;
169 }
170 }
171
fsl_ssi_writeable_reg(struct device * dev,unsigned int reg)172 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
173 {
174 switch (reg) {
175 case REG_SSI_SRX0:
176 case REG_SSI_SRX1:
177 case REG_SSI_SACCST:
178 return false;
179 default:
180 return true;
181 }
182 }
183
184 static const struct regmap_config fsl_ssi_regconfig = {
185 .max_register = REG_SSI_SACCDIS,
186 .reg_bits = 32,
187 .val_bits = 32,
188 .reg_stride = 4,
189 .val_format_endian = REGMAP_ENDIAN_NATIVE,
190 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
191 .readable_reg = fsl_ssi_readable_reg,
192 .volatile_reg = fsl_ssi_volatile_reg,
193 .precious_reg = fsl_ssi_precious_reg,
194 .writeable_reg = fsl_ssi_writeable_reg,
195 .cache_type = REGCACHE_FLAT,
196 };
197
198 struct fsl_ssi_soc_data {
199 bool imx;
200 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
201 bool offline_config;
202 u32 sisr_write_mask;
203 };
204
205 /**
206 * struct fsl_ssi - per-SSI private data
207 * @regs: Pointer to the regmap registers
208 * @irq: IRQ of this SSI
209 * @cpu_dai_drv: CPU DAI driver for this device
210 * @dai_fmt: DAI configuration this device is currently used with
211 * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
212 * @i2s_net: I2S and Network mode configurations of SCR register
213 * (this is the initial settings based on the DAI format)
214 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
215 * @use_dma: DMA is used or FIQ with stream filter
216 * @use_dual_fifo: DMA with support for dual FIFO mode
217 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
218 * @fifo_depth: Depth of the SSI FIFOs
219 * @slot_width: Width of each DAI slot
220 * @slots: Number of slots
221 * @regvals: Specific RX/TX register settings
222 * @clk: Clock source to access register
223 * @baudclk: Clock source to generate bit and frame-sync clocks
224 * @baudclk_streams: Active streams that are using baudclk
225 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
226 * @regcache_sacnt: Cache sacnt register value during suspend and resume
227 * @dma_params_tx: DMA transmit parameters
228 * @dma_params_rx: DMA receive parameters
229 * @ssi_phys: physical address of the SSI registers
230 * @fiq_params: FIQ stream filtering parameters
231 * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
232 * to register a CODEC platform device for AC97
233 * @card_name: Platform_device name to register a sound card for PowerPC or
234 * to register a CODEC platform device for AC97
235 * @card_idx: The index of SSI to register a sound card for PowerPC or
236 * to register a CODEC platform device for AC97
237 * @dbg_stats: Debugging statistics
238 * @soc: SoC specific data
239 * @dev: Pointer to &pdev->dev
240 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
241 * @fifo_watermark or fewer words in TX fifo or
242 * @fifo_watermark or more empty words in RX fifo.
243 * @dma_maxburst: Max number of words to transfer in one go. So far,
244 * this is always the same as fifo_watermark.
245 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
246 */
247 struct fsl_ssi {
248 struct regmap *regs;
249 int irq;
250 struct snd_soc_dai_driver cpu_dai_drv;
251
252 unsigned int dai_fmt;
253 u8 streams;
254 u8 i2s_net;
255 bool synchronous;
256 bool use_dma;
257 bool use_dual_fifo;
258 bool has_ipg_clk_name;
259 unsigned int fifo_depth;
260 unsigned int slot_width;
261 unsigned int slots;
262 struct fsl_ssi_regvals regvals[2];
263
264 struct clk *clk;
265 struct clk *baudclk;
266 unsigned int baudclk_streams;
267
268 u32 regcache_sfcsr;
269 u32 regcache_sacnt;
270
271 struct snd_dmaengine_dai_dma_data dma_params_tx;
272 struct snd_dmaengine_dai_dma_data dma_params_rx;
273 dma_addr_t ssi_phys;
274
275 struct imx_pcm_fiq_params fiq_params;
276
277 struct platform_device *card_pdev;
278 char card_name[32];
279 u32 card_idx;
280
281 struct fsl_ssi_dbg dbg_stats;
282
283 const struct fsl_ssi_soc_data *soc;
284 struct device *dev;
285
286 u32 fifo_watermark;
287 u32 dma_maxburst;
288
289 struct mutex ac97_reg_lock;
290 };
291
292 /*
293 * SoC specific data
294 *
295 * Notes:
296 * 1) SSI in earlier SoCS has critical bits in control registers that
297 * cannot be changed after SSI starts running -- a software reset
298 * (set SSIEN to 0) is required to change their values. So adding
299 * an offline_config flag for these SoCs.
300 * 2) SDMA is available since imx35. However, imx35 does not support
301 * DMA bits changing when SSI is running, so set offline_config.
302 * 3) imx51 and later versions support register configurations when
303 * SSI is running (SSIEN); For these versions, DMA needs to be
304 * configured before SSI sends DMA request to avoid an undefined
305 * DMA request on the SDMA side.
306 */
307
308 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
309 .imx = false,
310 .offline_config = true,
311 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
312 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
313 SSI_SISR_TUE0 | SSI_SISR_TUE1,
314 };
315
316 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
317 .imx = true,
318 .imx21regs = true,
319 .offline_config = true,
320 .sisr_write_mask = 0,
321 };
322
323 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
324 .imx = true,
325 .offline_config = true,
326 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
327 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
328 SSI_SISR_TUE0 | SSI_SISR_TUE1,
329 };
330
331 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
332 .imx = true,
333 .offline_config = false,
334 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
335 SSI_SISR_TUE0 | SSI_SISR_TUE1,
336 };
337
338 static const struct of_device_id fsl_ssi_ids[] = {
339 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
340 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
341 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
342 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
343 {}
344 };
345 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
346
fsl_ssi_is_ac97(struct fsl_ssi * ssi)347 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
348 {
349 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
350 SND_SOC_DAIFMT_AC97;
351 }
352
fsl_ssi_is_i2s_master(struct fsl_ssi * ssi)353 static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi)
354 {
355 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
356 SND_SOC_DAIFMT_CBS_CFS;
357 }
358
fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi * ssi)359 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi)
360 {
361 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
362 SND_SOC_DAIFMT_CBM_CFS;
363 }
364
365 /**
366 * fsl_ssi_irq - Interrupt handler to gather states
367 * @irq: irq number
368 * @dev_id: context
369 */
fsl_ssi_isr(int irq,void * dev_id)370 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
371 {
372 struct fsl_ssi *ssi = dev_id;
373 struct regmap *regs = ssi->regs;
374 u32 sisr, sisr2;
375
376 regmap_read(regs, REG_SSI_SISR, &sisr);
377
378 sisr2 = sisr & ssi->soc->sisr_write_mask;
379 /* Clear the bits that we set */
380 if (sisr2)
381 regmap_write(regs, REG_SSI_SISR, sisr2);
382
383 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
384
385 return IRQ_HANDLED;
386 }
387
388 /**
389 * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
390 * cached values in regvals
391 * @ssi: SSI context
392 * @tx: direction
393 *
394 * Notes:
395 * 1) For offline_config SoCs, enable all necessary bits of both streams
396 * when 1st stream starts, even if the opposite stream will not start
397 * 2) It also clears FIFO before setting regvals; SOR is safe to set online
398 */
fsl_ssi_config_enable(struct fsl_ssi * ssi,bool tx)399 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
400 {
401 struct fsl_ssi_regvals *vals = ssi->regvals;
402 int dir = tx ? TX : RX;
403 u32 sier, srcr, stcr;
404
405 /* Clear dirty data in the FIFO; It also prevents channel slipping */
406 regmap_update_bits(ssi->regs, REG_SSI_SOR,
407 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
408
409 /*
410 * On offline_config SoCs, SxCR and SIER are already configured when
411 * the previous stream started. So skip all SxCR and SIER settings
412 * to prevent online reconfigurations, then jump to set SCR directly
413 */
414 if (ssi->soc->offline_config && ssi->streams)
415 goto enable_scr;
416
417 if (ssi->soc->offline_config) {
418 /*
419 * Online reconfiguration not supported, so enable all bits for
420 * both streams at once to avoid necessity of reconfigurations
421 */
422 srcr = vals[RX].srcr | vals[TX].srcr;
423 stcr = vals[RX].stcr | vals[TX].stcr;
424 sier = vals[RX].sier | vals[TX].sier;
425 } else {
426 /* Otherwise, only set bits for the current stream */
427 srcr = vals[dir].srcr;
428 stcr = vals[dir].stcr;
429 sier = vals[dir].sier;
430 }
431
432 /* Configure SRCR, STCR and SIER at once */
433 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
434 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
435 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
436
437 enable_scr:
438 /*
439 * Start DMA before setting TE to avoid FIFO underrun
440 * which may cause a channel slip or a channel swap
441 *
442 * TODO: FIQ cases might also need this upon testing
443 */
444 if (ssi->use_dma && tx) {
445 int try = 100;
446 u32 sfcsr;
447
448 /* Enable SSI first to send TX DMA request */
449 regmap_update_bits(ssi->regs, REG_SSI_SCR,
450 SSI_SCR_SSIEN, SSI_SCR_SSIEN);
451
452 /* Busy wait until TX FIFO not empty -- DMA working */
453 do {
454 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
455 if (SSI_SFCSR_TFCNT0(sfcsr))
456 break;
457 } while (--try);
458
459 /* FIFO still empty -- something might be wrong */
460 if (!SSI_SFCSR_TFCNT0(sfcsr))
461 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
462 }
463 /* Enable all remaining bits in SCR */
464 regmap_update_bits(ssi->regs, REG_SSI_SCR,
465 vals[dir].scr, vals[dir].scr);
466
467 /* Log the enabled stream to the mask */
468 ssi->streams |= BIT(dir);
469 }
470
471 /*
472 * Exclude bits that are used by the opposite stream
473 *
474 * When both streams are active, disabling some bits for the current stream
475 * might break the other stream if these bits are used by it.
476 *
477 * @vals : regvals of the current stream
478 * @avals: regvals of the opposite stream
479 * @aactive: active state of the opposite stream
480 *
481 * 1) XOR vals and avals to get the differences if the other stream is active;
482 * Otherwise, return current vals if the other stream is not active
483 * 2) AND the result of 1) with the current vals
484 */
485 #define _ssi_xor_shared_bits(vals, avals, aactive) \
486 ((vals) ^ ((avals) * (aactive)))
487
488 #define ssi_excl_shared_bits(vals, avals, aactive) \
489 ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
490
491 /**
492 * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
493 * with cached values in regvals
494 * @ssi: SSI context
495 * @tx: direction
496 *
497 * Notes:
498 * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
499 * bits of both streams at once when the last stream is abort to end
500 * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
501 */
fsl_ssi_config_disable(struct fsl_ssi * ssi,bool tx)502 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
503 {
504 struct fsl_ssi_regvals *vals, *avals;
505 u32 sier, srcr, stcr, scr;
506 int adir = tx ? RX : TX;
507 int dir = tx ? TX : RX;
508 bool aactive;
509
510 /* Check if the opposite stream is active */
511 aactive = ssi->streams & BIT(adir);
512
513 vals = &ssi->regvals[dir];
514
515 /* Get regvals of the opposite stream to keep opposite stream safe */
516 avals = &ssi->regvals[adir];
517
518 /*
519 * To keep the other stream safe, exclude shared bits between
520 * both streams, and get safe bits to disable current stream
521 */
522 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
523
524 /* Disable safe bits of SCR register for the current stream */
525 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
526
527 /* Log the disabled stream to the mask */
528 ssi->streams &= ~BIT(dir);
529
530 /*
531 * On offline_config SoCs, if the other stream is active, skip
532 * SxCR and SIER settings to prevent online reconfigurations
533 */
534 if (ssi->soc->offline_config && aactive)
535 goto fifo_clear;
536
537 if (ssi->soc->offline_config) {
538 /* Now there is only current stream active, disable all bits */
539 srcr = vals->srcr | avals->srcr;
540 stcr = vals->stcr | avals->stcr;
541 sier = vals->sier | avals->sier;
542 } else {
543 /*
544 * To keep the other stream safe, exclude shared bits between
545 * both streams, and get safe bits to disable current stream
546 */
547 sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
548 srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
549 stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
550 }
551
552 /* Clear configurations of SRCR, STCR and SIER at once */
553 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
554 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
555 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
556
557 fifo_clear:
558 /* Clear remaining data in the FIFO */
559 regmap_update_bits(ssi->regs, REG_SSI_SOR,
560 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
561 }
562
fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi * ssi)563 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
564 {
565 struct regmap *regs = ssi->regs;
566
567 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
568 if (!ssi->soc->imx21regs) {
569 /* Disable all channel slots */
570 regmap_write(regs, REG_SSI_SACCDIS, 0xff);
571 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
572 regmap_write(regs, REG_SSI_SACCEN, 0x300);
573 }
574 }
575
576 /**
577 * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
578 * SCR to later set them safely
579 * @ssi: SSI context
580 */
fsl_ssi_setup_regvals(struct fsl_ssi * ssi)581 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
582 {
583 struct fsl_ssi_regvals *vals = ssi->regvals;
584
585 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
586 vals[RX].srcr = SSI_SRCR_RFEN0;
587 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
588 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
589 vals[TX].stcr = SSI_STCR_TFEN0;
590 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
591
592 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
593 if (fsl_ssi_is_ac97(ssi))
594 vals[RX].scr = vals[TX].scr = 0;
595
596 if (ssi->use_dual_fifo) {
597 vals[RX].srcr |= SSI_SRCR_RFEN1;
598 vals[TX].stcr |= SSI_STCR_TFEN1;
599 }
600
601 if (ssi->use_dma) {
602 vals[RX].sier |= SSI_SIER_RDMAE;
603 vals[TX].sier |= SSI_SIER_TDMAE;
604 } else {
605 vals[RX].sier |= SSI_SIER_RIE;
606 vals[TX].sier |= SSI_SIER_TIE;
607 }
608 }
609
fsl_ssi_setup_ac97(struct fsl_ssi * ssi)610 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
611 {
612 struct regmap *regs = ssi->regs;
613
614 /* Setup the clock control register */
615 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
616 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
617
618 /* Enable AC97 mode and startup the SSI */
619 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
620
621 /* AC97 has to communicate with codec before starting a stream */
622 regmap_update_bits(regs, REG_SSI_SCR,
623 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
624 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
625
626 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
627 }
628
fsl_ssi_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)629 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
630 struct snd_soc_dai *dai)
631 {
632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
633 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
634 int ret;
635
636 ret = clk_prepare_enable(ssi->clk);
637 if (ret)
638 return ret;
639
640 /*
641 * When using dual fifo mode, it is safer to ensure an even period
642 * size. If appearing to an odd number while DMA always starts its
643 * task from fifo0, fifo1 would be neglected at the end of each
644 * period. But SSI would still access fifo1 with an invalid data.
645 */
646 if (ssi->use_dual_fifo)
647 snd_pcm_hw_constraint_step(substream->runtime, 0,
648 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
649
650 return 0;
651 }
652
fsl_ssi_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)653 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
654 struct snd_soc_dai *dai)
655 {
656 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
657 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
658
659 clk_disable_unprepare(ssi->clk);
660 }
661
662 /**
663 * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
664 * @substream: ASoC substream
665 * @dai: pointer to DAI
666 * @hw_params: pointers to hw_params
667 *
668 * Notes: This function can be only called when using SSI as DAI master
669 *
670 * Quick instruction for parameters:
671 * freq: Output BCLK frequency = samplerate * slots * slot_width
672 * (In 2-channel I2S Master mode, slot_width is fixed 32)
673 */
fsl_ssi_set_bclk(struct snd_pcm_substream * substream,struct snd_soc_dai * dai,struct snd_pcm_hw_params * hw_params)674 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
675 struct snd_soc_dai *dai,
676 struct snd_pcm_hw_params *hw_params)
677 {
678 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
679 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
680 struct regmap *regs = ssi->regs;
681 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
682 unsigned long clkrate, baudrate, tmprate;
683 unsigned int channels = params_channels(hw_params);
684 unsigned int slot_width = params_width(hw_params);
685 unsigned int slots = 2;
686 u64 sub, savesub = 100000;
687 unsigned int freq;
688 bool baudclk_is_used;
689 int ret;
690
691 /* Override slots and slot_width if being specifically set... */
692 if (ssi->slots)
693 slots = ssi->slots;
694 if (ssi->slot_width)
695 slot_width = ssi->slot_width;
696
697 /* ...but force 32 bits for stereo audio using I2S Master Mode */
698 if (channels == 2 &&
699 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
700 slot_width = 32;
701
702 /* Generate bit clock based on the slot number and slot width */
703 freq = slots * slot_width * params_rate(hw_params);
704
705 /* Don't apply it to any non-baudclk circumstance */
706 if (IS_ERR(ssi->baudclk))
707 return -EINVAL;
708
709 /*
710 * Hardware limitation: The bclk rate must be
711 * never greater than 1/5 IPG clock rate
712 */
713 if (freq * 5 > clk_get_rate(ssi->clk)) {
714 dev_err(dai->dev, "bitclk > ipgclk / 5\n");
715 return -EINVAL;
716 }
717
718 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
719
720 /* It should be already enough to divide clock by setting pm alone */
721 psr = 0;
722 div2 = 0;
723
724 factor = (div2 + 1) * (7 * psr + 1) * 2;
725
726 for (i = 0; i < 255; i++) {
727 tmprate = freq * factor * (i + 1);
728
729 if (baudclk_is_used)
730 clkrate = clk_get_rate(ssi->baudclk);
731 else
732 clkrate = clk_round_rate(ssi->baudclk, tmprate);
733
734 clkrate /= factor;
735 afreq = clkrate / (i + 1);
736
737 if (freq == afreq)
738 sub = 0;
739 else if (freq / afreq == 1)
740 sub = freq - afreq;
741 else if (afreq / freq == 1)
742 sub = afreq - freq;
743 else
744 continue;
745
746 /* Calculate the fraction */
747 sub *= 100000;
748 do_div(sub, freq);
749
750 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
751 baudrate = tmprate;
752 savesub = sub;
753 pm = i;
754 }
755
756 /* We are lucky */
757 if (savesub == 0)
758 break;
759 }
760
761 /* No proper pm found if it is still remaining the initial value */
762 if (pm == 999) {
763 dev_err(dai->dev, "failed to handle the required sysclk\n");
764 return -EINVAL;
765 }
766
767 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
768 (psr ? SSI_SxCCR_PSR : 0);
769 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
770
771 /* STCCR is used for RX in synchronous mode */
772 tx2 = tx || ssi->synchronous;
773 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
774
775 if (!baudclk_is_used) {
776 ret = clk_set_rate(ssi->baudclk, baudrate);
777 if (ret) {
778 dev_err(dai->dev, "failed to set baudclk rate\n");
779 return -EINVAL;
780 }
781 }
782
783 return 0;
784 }
785
786 /**
787 * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
788 * @substream: ASoC substream
789 * @hw_params: pointers to hw_params
790 * @dai: pointer to DAI
791 *
792 * Notes:
793 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
794 * disabled on offline_config SoCs. Even for online configurable SoCs
795 * running in synchronous mode (both TX and RX use STCCR), it is not
796 * safe to re-configure them when both two streams start running.
797 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
798 * fsl_ssi_set_bclk() if SSI is the DAI clock master.
799 */
fsl_ssi_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params,struct snd_soc_dai * dai)800 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
801 struct snd_pcm_hw_params *hw_params,
802 struct snd_soc_dai *dai)
803 {
804 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
805 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
806 struct regmap *regs = ssi->regs;
807 unsigned int channels = params_channels(hw_params);
808 unsigned int sample_size = params_width(hw_params);
809 u32 wl = SSI_SxCCR_WL(sample_size);
810 int ret;
811
812 if (fsl_ssi_is_i2s_master(ssi)) {
813 ret = fsl_ssi_set_bclk(substream, dai, hw_params);
814 if (ret)
815 return ret;
816
817 /* Do not enable the clock if it is already enabled */
818 if (!(ssi->baudclk_streams & BIT(substream->stream))) {
819 ret = clk_prepare_enable(ssi->baudclk);
820 if (ret)
821 return ret;
822
823 ssi->baudclk_streams |= BIT(substream->stream);
824 }
825 }
826
827 /*
828 * SSI is properly configured if it is enabled and running in
829 * the synchronous mode; Note that AC97 mode is an exception
830 * that should set separate configurations for STCCR and SRCCR
831 * despite running in the synchronous mode.
832 */
833 if (ssi->streams && ssi->synchronous)
834 return 0;
835
836 if (!fsl_ssi_is_ac97(ssi)) {
837 /*
838 * Keep the ssi->i2s_net intact while having a local variable
839 * to override settings for special use cases. Otherwise, the
840 * ssi->i2s_net will lose the settings for regular use cases.
841 */
842 u8 i2s_net = ssi->i2s_net;
843
844 /* Normal + Network mode to send 16-bit data in 32-bit frames */
845 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
846 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
847
848 /* Use Normal mode to send mono data at 1st slot of 2 slots */
849 if (channels == 1)
850 i2s_net = SSI_SCR_I2S_MODE_NORMAL;
851
852 regmap_update_bits(regs, REG_SSI_SCR,
853 SSI_SCR_I2S_NET_MASK, i2s_net);
854 }
855
856 /* In synchronous mode, the SSI uses STCCR for capture */
857 tx2 = tx || ssi->synchronous;
858 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
859
860 return 0;
861 }
862
fsl_ssi_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)863 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
864 struct snd_soc_dai *dai)
865 {
866 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
867 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
868
869 if (fsl_ssi_is_i2s_master(ssi) &&
870 ssi->baudclk_streams & BIT(substream->stream)) {
871 clk_disable_unprepare(ssi->baudclk);
872 ssi->baudclk_streams &= ~BIT(substream->stream);
873 }
874
875 return 0;
876 }
877
_fsl_ssi_set_dai_fmt(struct fsl_ssi * ssi,unsigned int fmt)878 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
879 {
880 u32 strcr = 0, scr = 0, stcr, srcr, mask;
881 unsigned int slots;
882
883 ssi->dai_fmt = fmt;
884
885 /* Synchronize frame sync clock for TE to avoid data slipping */
886 scr |= SSI_SCR_SYNC_TX_FS;
887
888 /* Set to default shifting settings: LSB_ALIGNED */
889 strcr |= SSI_STCR_TXBIT0;
890
891 /* Use Network mode as default */
892 ssi->i2s_net = SSI_SCR_NET;
893 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
894 case SND_SOC_DAIFMT_I2S:
895 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
896 case SND_SOC_DAIFMT_CBS_CFS:
897 if (IS_ERR(ssi->baudclk)) {
898 dev_err(ssi->dev,
899 "missing baudclk for master mode\n");
900 return -EINVAL;
901 }
902 fallthrough;
903 case SND_SOC_DAIFMT_CBM_CFS:
904 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
905 break;
906 case SND_SOC_DAIFMT_CBM_CFM:
907 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
908 break;
909 default:
910 return -EINVAL;
911 }
912
913 slots = ssi->slots ? : 2;
914 regmap_update_bits(ssi->regs, REG_SSI_STCCR,
915 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
916 regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
917 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
918
919 /* Data on rising edge of bclk, frame low, 1clk before data */
920 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
921 break;
922 case SND_SOC_DAIFMT_LEFT_J:
923 /* Data on rising edge of bclk, frame high */
924 strcr |= SSI_STCR_TSCKP;
925 break;
926 case SND_SOC_DAIFMT_DSP_A:
927 /* Data on rising edge of bclk, frame high, 1clk before data */
928 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
929 break;
930 case SND_SOC_DAIFMT_DSP_B:
931 /* Data on rising edge of bclk, frame high */
932 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
933 break;
934 case SND_SOC_DAIFMT_AC97:
935 /* Data on falling edge of bclk, frame high, 1clk before data */
936 strcr |= SSI_STCR_TEFS;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 scr |= ssi->i2s_net;
943
944 /* DAI clock inversion */
945 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
946 case SND_SOC_DAIFMT_NB_NF:
947 /* Nothing to do for both normal cases */
948 break;
949 case SND_SOC_DAIFMT_IB_NF:
950 /* Invert bit clock */
951 strcr ^= SSI_STCR_TSCKP;
952 break;
953 case SND_SOC_DAIFMT_NB_IF:
954 /* Invert frame clock */
955 strcr ^= SSI_STCR_TFSI;
956 break;
957 case SND_SOC_DAIFMT_IB_IF:
958 /* Invert both clocks */
959 strcr ^= SSI_STCR_TSCKP;
960 strcr ^= SSI_STCR_TFSI;
961 break;
962 default:
963 return -EINVAL;
964 }
965
966 /* DAI clock master masks */
967 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
968 case SND_SOC_DAIFMT_CBS_CFS:
969 /* Output bit and frame sync clocks */
970 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
971 scr |= SSI_SCR_SYS_CLK_EN;
972 break;
973 case SND_SOC_DAIFMT_CBM_CFM:
974 /* Input bit or frame sync clocks */
975 break;
976 case SND_SOC_DAIFMT_CBM_CFS:
977 /* Input bit clock but output frame sync clock */
978 strcr |= SSI_STCR_TFDIR;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 stcr = strcr;
985 srcr = strcr;
986
987 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
988 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
989 srcr &= ~SSI_SRCR_RXDIR;
990 scr |= SSI_SCR_SYN;
991 }
992
993 mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
994 SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
995
996 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
997 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
998
999 mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
1000 SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
1001 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1002
1003 return 0;
1004 }
1005
1006 /**
1007 * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
1008 * @dai: pointer to DAI
1009 * @fmt: format mask
1010 */
fsl_ssi_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1011 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1012 {
1013 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1014
1015 /* AC97 configured DAIFMT earlier in the probe() */
1016 if (fsl_ssi_is_ac97(ssi))
1017 return 0;
1018
1019 return _fsl_ssi_set_dai_fmt(ssi, fmt);
1020 }
1021
1022 /**
1023 * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
1024 * @dai: pointer to DAI
1025 * @tx_mask: mask for TX
1026 * @rx_mask: mask for RX
1027 * @slots: number of slots
1028 * @slot_width: number of bits per slot
1029 */
fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai * dai,u32 tx_mask,u32 rx_mask,int slots,int slot_width)1030 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
1031 u32 rx_mask, int slots, int slot_width)
1032 {
1033 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1034 struct regmap *regs = ssi->regs;
1035 u32 val;
1036
1037 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
1038 if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
1039 dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
1040 return -EINVAL;
1041 }
1042
1043 /* The slot number should be >= 2 if using Network mode or I2S mode */
1044 if (ssi->i2s_net && slots < 2) {
1045 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
1046 return -EINVAL;
1047 }
1048
1049 regmap_update_bits(regs, REG_SSI_STCCR,
1050 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1051 regmap_update_bits(regs, REG_SSI_SRCCR,
1052 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1053
1054 /* Save the SCR register value */
1055 regmap_read(regs, REG_SSI_SCR, &val);
1056 /* Temporarily enable SSI to allow SxMSKs to be configurable */
1057 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
1058
1059 regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1060 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1061
1062 /* Restore the value of SSIEN bit */
1063 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1064
1065 ssi->slot_width = slot_width;
1066 ssi->slots = slots;
1067
1068 return 0;
1069 }
1070
1071 /**
1072 * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
1073 * @substream: ASoC substream
1074 * @cmd: trigger command
1075 * @dai: pointer to DAI
1076 *
1077 * The DMA channel is in external master start and pause mode, which
1078 * means the SSI completely controls the flow of data.
1079 */
fsl_ssi_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1080 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1081 struct snd_soc_dai *dai)
1082 {
1083 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1084 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
1085 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
1086
1087 switch (cmd) {
1088 case SNDRV_PCM_TRIGGER_START:
1089 case SNDRV_PCM_TRIGGER_RESUME:
1090 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1091 /*
1092 * SACCST might be modified via AC Link by a CODEC if it sends
1093 * extra bits in their SLOTREQ requests, which'll accidentally
1094 * send valid data to slots other than normal playback slots.
1095 *
1096 * To be safe, configure SACCST right before TX starts.
1097 */
1098 if (tx && fsl_ssi_is_ac97(ssi))
1099 fsl_ssi_tx_ac97_saccst_setup(ssi);
1100 fsl_ssi_config_enable(ssi, tx);
1101 break;
1102
1103 case SNDRV_PCM_TRIGGER_STOP:
1104 case SNDRV_PCM_TRIGGER_SUSPEND:
1105 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1106 fsl_ssi_config_disable(ssi, tx);
1107 break;
1108
1109 default:
1110 return -EINVAL;
1111 }
1112
1113 return 0;
1114 }
1115
fsl_ssi_dai_probe(struct snd_soc_dai * dai)1116 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1117 {
1118 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1119
1120 if (ssi->soc->imx && ssi->use_dma)
1121 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1122 &ssi->dma_params_rx);
1123
1124 return 0;
1125 }
1126
1127 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1128 .startup = fsl_ssi_startup,
1129 .shutdown = fsl_ssi_shutdown,
1130 .hw_params = fsl_ssi_hw_params,
1131 .hw_free = fsl_ssi_hw_free,
1132 .set_fmt = fsl_ssi_set_dai_fmt,
1133 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1134 .trigger = fsl_ssi_trigger,
1135 };
1136
1137 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1138 .probe = fsl_ssi_dai_probe,
1139 .playback = {
1140 .stream_name = "CPU-Playback",
1141 .channels_min = 1,
1142 .channels_max = 32,
1143 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1144 .formats = FSLSSI_I2S_FORMATS,
1145 },
1146 .capture = {
1147 .stream_name = "CPU-Capture",
1148 .channels_min = 1,
1149 .channels_max = 32,
1150 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1151 .formats = FSLSSI_I2S_FORMATS,
1152 },
1153 .ops = &fsl_ssi_dai_ops,
1154 };
1155
1156 static const struct snd_soc_component_driver fsl_ssi_component = {
1157 .name = "fsl-ssi",
1158 };
1159
1160 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1161 .symmetric_channels = 1,
1162 .probe = fsl_ssi_dai_probe,
1163 .playback = {
1164 .stream_name = "AC97 Playback",
1165 .channels_min = 2,
1166 .channels_max = 2,
1167 .rates = SNDRV_PCM_RATE_8000_48000,
1168 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
1169 },
1170 .capture = {
1171 .stream_name = "AC97 Capture",
1172 .channels_min = 2,
1173 .channels_max = 2,
1174 .rates = SNDRV_PCM_RATE_48000,
1175 /* 16-bit capture is broken (errata ERR003778) */
1176 .formats = SNDRV_PCM_FMTBIT_S20,
1177 },
1178 .ops = &fsl_ssi_dai_ops,
1179 };
1180
1181 static struct fsl_ssi *fsl_ac97_data;
1182
fsl_ssi_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)1183 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1184 unsigned short val)
1185 {
1186 struct regmap *regs = fsl_ac97_data->regs;
1187 unsigned int lreg;
1188 unsigned int lval;
1189 int ret;
1190
1191 if (reg > 0x7f)
1192 return;
1193
1194 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1195
1196 ret = clk_prepare_enable(fsl_ac97_data->clk);
1197 if (ret) {
1198 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1199 ret);
1200 goto ret_unlock;
1201 }
1202
1203 lreg = reg << 12;
1204 regmap_write(regs, REG_SSI_SACADD, lreg);
1205
1206 lval = val << 4;
1207 regmap_write(regs, REG_SSI_SACDAT, lval);
1208
1209 regmap_update_bits(regs, REG_SSI_SACNT,
1210 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
1211 udelay(100);
1212
1213 clk_disable_unprepare(fsl_ac97_data->clk);
1214
1215 ret_unlock:
1216 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1217 }
1218
fsl_ssi_ac97_read(struct snd_ac97 * ac97,unsigned short reg)1219 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1220 unsigned short reg)
1221 {
1222 struct regmap *regs = fsl_ac97_data->regs;
1223 unsigned short val = 0;
1224 u32 reg_val;
1225 unsigned int lreg;
1226 int ret;
1227
1228 mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1229
1230 ret = clk_prepare_enable(fsl_ac97_data->clk);
1231 if (ret) {
1232 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1233 goto ret_unlock;
1234 }
1235
1236 lreg = (reg & 0x7f) << 12;
1237 regmap_write(regs, REG_SSI_SACADD, lreg);
1238 regmap_update_bits(regs, REG_SSI_SACNT,
1239 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
1240
1241 udelay(100);
1242
1243 regmap_read(regs, REG_SSI_SACDAT, ®_val);
1244 val = (reg_val >> 4) & 0xffff;
1245
1246 clk_disable_unprepare(fsl_ac97_data->clk);
1247
1248 ret_unlock:
1249 mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1250 return val;
1251 }
1252
1253 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1254 .read = fsl_ssi_ac97_read,
1255 .write = fsl_ssi_ac97_write,
1256 };
1257
1258 /**
1259 * fsl_ssi_hw_init - Initialize SSI registers
1260 * @ssi: SSI context
1261 */
fsl_ssi_hw_init(struct fsl_ssi * ssi)1262 static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1263 {
1264 u32 wm = ssi->fifo_watermark;
1265
1266 /* Initialize regvals */
1267 fsl_ssi_setup_regvals(ssi);
1268
1269 /* Set watermarks */
1270 regmap_write(ssi->regs, REG_SSI_SFCSR,
1271 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1272 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1273
1274 /* Enable Dual FIFO mode */
1275 if (ssi->use_dual_fifo)
1276 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1277 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
1278
1279 /* AC97 should start earlier to communicate with CODECs */
1280 if (fsl_ssi_is_ac97(ssi)) {
1281 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1282 fsl_ssi_setup_ac97(ssi);
1283 }
1284
1285 return 0;
1286 }
1287
1288 /**
1289 * fsl_ssi_hw_clean - Clear SSI registers
1290 * @ssi: SSI context
1291 */
fsl_ssi_hw_clean(struct fsl_ssi * ssi)1292 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1293 {
1294 /* Disable registers for AC97 */
1295 if (fsl_ssi_is_ac97(ssi)) {
1296 /* Disable TE and RE bits first */
1297 regmap_update_bits(ssi->regs, REG_SSI_SCR,
1298 SSI_SCR_TE | SSI_SCR_RE, 0);
1299 /* Disable AC97 mode */
1300 regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1301 /* Unset WAIT bits */
1302 regmap_write(ssi->regs, REG_SSI_SOR, 0);
1303 /* Disable SSI -- software reset */
1304 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1305 }
1306 }
1307
1308 /*
1309 * Make every character in a string lower-case
1310 */
make_lowercase(char * s)1311 static void make_lowercase(char *s)
1312 {
1313 if (!s)
1314 return;
1315 for (; *s; s++)
1316 *s = tolower(*s);
1317 }
1318
fsl_ssi_imx_probe(struct platform_device * pdev,struct fsl_ssi * ssi,void __iomem * iomem)1319 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1320 struct fsl_ssi *ssi, void __iomem *iomem)
1321 {
1322 struct device *dev = &pdev->dev;
1323 int ret;
1324
1325 /* Backward compatible for a DT without ipg clock name assigned */
1326 if (ssi->has_ipg_clk_name)
1327 ssi->clk = devm_clk_get(dev, "ipg");
1328 else
1329 ssi->clk = devm_clk_get(dev, NULL);
1330 if (IS_ERR(ssi->clk)) {
1331 ret = PTR_ERR(ssi->clk);
1332 dev_err(dev, "failed to get clock: %d\n", ret);
1333 return ret;
1334 }
1335
1336 /* Enable the clock since regmap will not handle it in this case */
1337 if (!ssi->has_ipg_clk_name) {
1338 ret = clk_prepare_enable(ssi->clk);
1339 if (ret) {
1340 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1341 return ret;
1342 }
1343 }
1344
1345 /* Do not error out for slave cases that live without a baud clock */
1346 ssi->baudclk = devm_clk_get(dev, "baud");
1347 if (IS_ERR(ssi->baudclk))
1348 dev_dbg(dev, "failed to get baud clock: %ld\n",
1349 PTR_ERR(ssi->baudclk));
1350
1351 ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1352 ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1353 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1354 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1355
1356 /* Use even numbers to avoid channel swap due to SDMA script design */
1357 if (ssi->use_dual_fifo) {
1358 ssi->dma_params_tx.maxburst &= ~0x1;
1359 ssi->dma_params_rx.maxburst &= ~0x1;
1360 }
1361
1362 if (!ssi->use_dma) {
1363 /*
1364 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
1365 * to get it working, as DMA is not possible in this situation.
1366 */
1367 ssi->fiq_params.irq = ssi->irq;
1368 ssi->fiq_params.base = iomem;
1369 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1370 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1371
1372 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1373 if (ret)
1374 goto error_pcm;
1375 } else {
1376 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1377 if (ret)
1378 goto error_pcm;
1379 }
1380
1381 return 0;
1382
1383 error_pcm:
1384 if (!ssi->has_ipg_clk_name)
1385 clk_disable_unprepare(ssi->clk);
1386
1387 return ret;
1388 }
1389
fsl_ssi_imx_clean(struct platform_device * pdev,struct fsl_ssi * ssi)1390 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1391 {
1392 if (!ssi->use_dma)
1393 imx_pcm_fiq_exit(pdev);
1394 if (!ssi->has_ipg_clk_name)
1395 clk_disable_unprepare(ssi->clk);
1396 }
1397
fsl_ssi_probe_from_dt(struct fsl_ssi * ssi)1398 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1399 {
1400 struct device *dev = ssi->dev;
1401 struct device_node *np = dev->of_node;
1402 const struct of_device_id *of_id;
1403 const char *p, *sprop;
1404 const __be32 *iprop;
1405 u32 dmas[4];
1406 int ret;
1407
1408 of_id = of_match_device(fsl_ssi_ids, dev);
1409 if (!of_id || !of_id->data)
1410 return -EINVAL;
1411
1412 ssi->soc = of_id->data;
1413
1414 ret = of_property_match_string(np, "clock-names", "ipg");
1415 /* Get error code if not found */
1416 ssi->has_ipg_clk_name = ret >= 0;
1417
1418 /* Check if being used in AC97 mode */
1419 sprop = of_get_property(np, "fsl,mode", NULL);
1420 if (sprop && !strcmp(sprop, "ac97-slave")) {
1421 ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1422
1423 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1424 if (ret) {
1425 dev_err(dev, "failed to get SSI index property\n");
1426 return -EINVAL;
1427 }
1428 strcpy(ssi->card_name, "ac97-codec");
1429 } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1430 /*
1431 * In synchronous mode, STCK and STFS ports are used by RX
1432 * as well. So the software should limit the sample rates,
1433 * sample bits and channels to be symmetric.
1434 *
1435 * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
1436 * in the SSI synchronous mode however it does not have to
1437 * limit symmetric sample rates and sample bits.
1438 */
1439 ssi->synchronous = true;
1440 }
1441
1442 /* Select DMA or FIQ */
1443 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1444
1445 /* Fetch FIFO depth; Set to 8 for older DT without this property */
1446 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1447 if (iprop)
1448 ssi->fifo_depth = be32_to_cpup(iprop);
1449 else
1450 ssi->fifo_depth = 8;
1451
1452 /* Use dual FIFO mode depending on the support from SDMA script */
1453 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1454 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1455 ssi->use_dual_fifo = true;
1456
1457 /*
1458 * Backward compatible for older bindings by manually triggering the
1459 * machine driver's probe(). Use /compatible property, including the
1460 * address of CPU DAI driver structure, as the name of machine driver
1461 *
1462 * If card_name is set by AC97 earlier, bypass here since it uses a
1463 * different name to register the device.
1464 */
1465 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1466 struct device_node *root = of_find_node_by_path("/");
1467
1468 sprop = of_get_property(root, "compatible", NULL);
1469 of_node_put(root);
1470 /* Strip "fsl," in the compatible name if applicable */
1471 p = strrchr(sprop, ',');
1472 if (p)
1473 sprop = p + 1;
1474 snprintf(ssi->card_name, sizeof(ssi->card_name),
1475 "snd-soc-%s", sprop);
1476 make_lowercase(ssi->card_name);
1477 ssi->card_idx = 0;
1478 }
1479
1480 return 0;
1481 }
1482
fsl_ssi_probe(struct platform_device * pdev)1483 static int fsl_ssi_probe(struct platform_device *pdev)
1484 {
1485 struct regmap_config regconfig = fsl_ssi_regconfig;
1486 struct device *dev = &pdev->dev;
1487 struct fsl_ssi *ssi;
1488 struct resource *res;
1489 void __iomem *iomem;
1490 int ret = 0;
1491
1492 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1493 if (!ssi)
1494 return -ENOMEM;
1495
1496 ssi->dev = dev;
1497
1498 /* Probe from DT */
1499 ret = fsl_ssi_probe_from_dt(ssi);
1500 if (ret)
1501 return ret;
1502
1503 if (fsl_ssi_is_ac97(ssi)) {
1504 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1505 sizeof(fsl_ssi_ac97_dai));
1506 fsl_ac97_data = ssi;
1507 } else {
1508 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1509 sizeof(fsl_ssi_dai_template));
1510 }
1511 ssi->cpu_dai_drv.name = dev_name(dev);
1512
1513 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1514 iomem = devm_ioremap_resource(dev, res);
1515 if (IS_ERR(iomem))
1516 return PTR_ERR(iomem);
1517 ssi->ssi_phys = res->start;
1518
1519 if (ssi->soc->imx21regs) {
1520 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
1521 regconfig.max_register = REG_SSI_SRMSK;
1522 regconfig.num_reg_defaults_raw =
1523 REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1524 }
1525
1526 if (ssi->has_ipg_clk_name)
1527 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1528 ®config);
1529 else
1530 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config);
1531 if (IS_ERR(ssi->regs)) {
1532 dev_err(dev, "failed to init register map\n");
1533 return PTR_ERR(ssi->regs);
1534 }
1535
1536 ssi->irq = platform_get_irq(pdev, 0);
1537 if (ssi->irq < 0)
1538 return ssi->irq;
1539
1540 /* Set software limitations for synchronous mode except AC97 */
1541 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1542 ssi->cpu_dai_drv.symmetric_rates = 1;
1543 ssi->cpu_dai_drv.symmetric_channels = 1;
1544 ssi->cpu_dai_drv.symmetric_samplebits = 1;
1545 }
1546
1547 /*
1548 * Configure TX and RX DMA watermarks -- when to send a DMA request
1549 *
1550 * Values should be tested to avoid FIFO under/over run. Set maxburst
1551 * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
1552 */
1553 switch (ssi->fifo_depth) {
1554 case 15:
1555 /*
1556 * Set to 8 as a balanced configuration -- When TX FIFO has 8
1557 * empty slots, send a DMA request to fill these 8 slots. The
1558 * remaining 7 slots should be able to allow DMA to finish the
1559 * transaction before TX FIFO underruns; Same applies to RX.
1560 *
1561 * Tested with cases running at 48kHz @ 16 bits x 16 channels
1562 */
1563 ssi->fifo_watermark = 8;
1564 ssi->dma_maxburst = 8;
1565 break;
1566 case 8:
1567 default:
1568 /* Safely use old watermark configurations for older chips */
1569 ssi->fifo_watermark = ssi->fifo_depth - 2;
1570 ssi->dma_maxburst = ssi->fifo_depth - 2;
1571 break;
1572 }
1573
1574 dev_set_drvdata(dev, ssi);
1575
1576 if (ssi->soc->imx) {
1577 ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1578 if (ret)
1579 return ret;
1580 }
1581
1582 if (fsl_ssi_is_ac97(ssi)) {
1583 mutex_init(&ssi->ac97_reg_lock);
1584 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1585 if (ret) {
1586 dev_err(dev, "failed to set AC'97 ops\n");
1587 goto error_ac97_ops;
1588 }
1589 }
1590
1591 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1592 &ssi->cpu_dai_drv, 1);
1593 if (ret) {
1594 dev_err(dev, "failed to register DAI: %d\n", ret);
1595 goto error_asoc_register;
1596 }
1597
1598 if (ssi->use_dma) {
1599 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1600 dev_name(dev), ssi);
1601 if (ret < 0) {
1602 dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1603 goto error_asoc_register;
1604 }
1605 }
1606
1607 fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1608
1609 /* Initially configures SSI registers */
1610 fsl_ssi_hw_init(ssi);
1611
1612 /* Register a platform device for older bindings or AC97 */
1613 if (ssi->card_name[0]) {
1614 struct device *parent = dev;
1615 /*
1616 * Do not set SSI dev as the parent of AC97 CODEC device since
1617 * it does not have a DT node. Otherwise ASoC core will assume
1618 * CODEC has the same DT node as the SSI, so it may bypass the
1619 * dai_probe() of SSI and then cause NULL DMA data pointers.
1620 */
1621 if (fsl_ssi_is_ac97(ssi))
1622 parent = NULL;
1623
1624 ssi->card_pdev = platform_device_register_data(parent,
1625 ssi->card_name, ssi->card_idx, NULL, 0);
1626 if (IS_ERR(ssi->card_pdev)) {
1627 ret = PTR_ERR(ssi->card_pdev);
1628 dev_err(dev, "failed to register %s: %d\n",
1629 ssi->card_name, ret);
1630 goto error_sound_card;
1631 }
1632 }
1633
1634 return 0;
1635
1636 error_sound_card:
1637 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1638 error_asoc_register:
1639 if (fsl_ssi_is_ac97(ssi))
1640 snd_soc_set_ac97_ops(NULL);
1641 error_ac97_ops:
1642 if (fsl_ssi_is_ac97(ssi))
1643 mutex_destroy(&ssi->ac97_reg_lock);
1644
1645 if (ssi->soc->imx)
1646 fsl_ssi_imx_clean(pdev, ssi);
1647
1648 return ret;
1649 }
1650
fsl_ssi_remove(struct platform_device * pdev)1651 static int fsl_ssi_remove(struct platform_device *pdev)
1652 {
1653 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1654
1655 fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1656
1657 if (ssi->card_pdev)
1658 platform_device_unregister(ssi->card_pdev);
1659
1660 /* Clean up SSI registers */
1661 fsl_ssi_hw_clean(ssi);
1662
1663 if (ssi->soc->imx)
1664 fsl_ssi_imx_clean(pdev, ssi);
1665
1666 if (fsl_ssi_is_ac97(ssi)) {
1667 snd_soc_set_ac97_ops(NULL);
1668 mutex_destroy(&ssi->ac97_reg_lock);
1669 }
1670
1671 return 0;
1672 }
1673
1674 #ifdef CONFIG_PM_SLEEP
fsl_ssi_suspend(struct device * dev)1675 static int fsl_ssi_suspend(struct device *dev)
1676 {
1677 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1678 struct regmap *regs = ssi->regs;
1679
1680 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1681 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1682
1683 regcache_cache_only(regs, true);
1684 regcache_mark_dirty(regs);
1685
1686 return 0;
1687 }
1688
fsl_ssi_resume(struct device * dev)1689 static int fsl_ssi_resume(struct device *dev)
1690 {
1691 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1692 struct regmap *regs = ssi->regs;
1693
1694 regcache_cache_only(regs, false);
1695
1696 regmap_update_bits(regs, REG_SSI_SFCSR,
1697 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1698 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1699 ssi->regcache_sfcsr);
1700 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1701
1702 return regcache_sync(regs);
1703 }
1704 #endif /* CONFIG_PM_SLEEP */
1705
1706 static const struct dev_pm_ops fsl_ssi_pm = {
1707 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1708 };
1709
1710 static struct platform_driver fsl_ssi_driver = {
1711 .driver = {
1712 .name = "fsl-ssi-dai",
1713 .of_match_table = fsl_ssi_ids,
1714 .pm = &fsl_ssi_pm,
1715 },
1716 .probe = fsl_ssi_probe,
1717 .remove = fsl_ssi_remove,
1718 };
1719
1720 module_platform_driver(fsl_ssi_driver);
1721
1722 MODULE_ALIAS("platform:fsl-ssi-dai");
1723 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1724 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1725 MODULE_LICENSE("GPL v2");
1726