1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * arch/arm/mach-prima2/include/mach/sirfsoc_usp.h 4 * 5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 6 */ 7 8 #ifndef _SIRF_USP_H 9 #define _SIRF_USP_H 10 11 /* USP Registers */ 12 #define USP_MODE1 0x00 13 #define USP_MODE2 0x04 14 #define USP_TX_FRAME_CTRL 0x08 15 #define USP_RX_FRAME_CTRL 0x0C 16 #define USP_TX_RX_ENABLE 0x10 17 #define USP_INT_ENABLE 0x14 18 #define USP_INT_STATUS 0x18 19 #define USP_PIN_IO_DATA 0x1C 20 #define USP_RISC_DSP_MODE 0x20 21 #define USP_AYSNC_PARAM_REG 0x24 22 #define USP_IRDA_X_MODE_DIV 0x28 23 #define USP_SM_CFG 0x2C 24 #define USP_TX_DMA_IO_CTRL 0x100 25 #define USP_TX_DMA_IO_LEN 0x104 26 #define USP_TX_FIFO_CTRL 0x108 27 #define USP_TX_FIFO_LEVEL_CHK 0x10C 28 #define USP_TX_FIFO_OP 0x110 29 #define USP_TX_FIFO_STATUS 0x114 30 #define USP_TX_FIFO_DATA 0x118 31 #define USP_RX_DMA_IO_CTRL 0x120 32 #define USP_RX_DMA_IO_LEN 0x124 33 #define USP_RX_FIFO_CTRL 0x128 34 #define USP_RX_FIFO_LEVEL_CHK 0x12C 35 #define USP_RX_FIFO_OP 0x130 36 #define USP_RX_FIFO_STATUS 0x134 37 #define USP_RX_FIFO_DATA 0x138 38 39 /* USP MODE register-1 */ 40 #define USP_SYNC_MODE 0x00000001 41 #define USP_CLOCK_MODE_SLAVE 0x00000002 42 #define USP_LOOP_BACK_EN 0x00000004 43 #define USP_HPSIR_EN 0x00000008 44 #define USP_ENDIAN_CTRL_LSBF 0x00000010 45 #define USP_EN 0x00000020 46 #define USP_RXD_ACT_EDGE_FALLING 0x00000040 47 #define USP_TXD_ACT_EDGE_FALLING 0x00000080 48 #define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100 49 #define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200 50 #define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400 51 #define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800 52 #define USP_SCLK_PIN_MODE_IO 0x00001000 53 #define USP_RFS_PIN_MODE_IO 0x00002000 54 #define USP_TFS_PIN_MODE_IO 0x00004000 55 #define USP_RXD_PIN_MODE_IO 0x00008000 56 #define USP_TXD_PIN_MODE_IO 0x00010000 57 #define USP_SCLK_IO_MODE_INPUT 0x00020000 58 #define USP_RFS_IO_MODE_INPUT 0x00040000 59 #define USP_TFS_IO_MODE_INPUT 0x00080000 60 #define USP_RXD_IO_MODE_INPUT 0x00100000 61 #define USP_TXD_IO_MODE_INPUT 0x00200000 62 #define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000 63 #define USP_IRDA_WIDTH_DIV_OFFSET 0 64 #define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000 65 #define USP_TX_UFLOW_REPEAT_ZERO 0x80000000 66 #define USP_TX_ENDIAN_MODE 0x00000020 67 #define USP_RX_ENDIAN_MODE 0x00000020 68 69 /* USP Mode Register-2 */ 70 #define USP_RXD_DELAY_LEN_MASK 0x000000FF 71 #define USP_RXD_DELAY_LEN_OFFSET 0 72 73 #define USP_TXD_DELAY_LEN_MASK 0x0000FF00 74 #define USP_TXD_DELAY_LEN_OFFSET 8 75 76 #define USP_ENA_CTRL_MODE 0x00010000 77 #define USP_FRAME_CTRL_MODE 0x00020000 78 #define USP_TFS_SOURCE_MODE 0x00040000 79 #define USP_TFS_MS_MODE 0x00080000 80 #define USP_CLK_DIVISOR_MASK 0x7FE00000 81 #define USP_CLK_DIVISOR_OFFSET 21 82 83 #define USP_TFS_CLK_SLAVE_MODE (1<<20) 84 #define USP_RFS_CLK_SLAVE_MODE (1<<19) 85 86 #define USP_IRDA_DATA_WIDTH 0x80000000 87 88 /* USP Transmit Frame Control Register */ 89 90 #define USP_TXC_DATA_LEN_MASK 0x000000FF 91 #define USP_TXC_DATA_LEN_OFFSET 0 92 93 #define USP_TXC_SYNC_LEN_MASK 0x0000FF00 94 #define USP_TXC_SYNC_LEN_OFFSET 8 95 96 #define USP_TXC_FRAME_LEN_MASK 0x00FF0000 97 #define USP_TXC_FRAME_LEN_OFFSET 16 98 99 #define USP_TXC_SHIFTER_LEN_MASK 0x1F000000 100 #define USP_TXC_SHIFTER_LEN_OFFSET 24 101 102 #define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000 103 104 #define USP_TXC_CLK_DIVISOR_MASK 0xC0000000 105 #define USP_TXC_CLK_DIVISOR_OFFSET 30 106 107 /* USP Receive Frame Control Register */ 108 109 #define USP_RXC_DATA_LEN_MASK 0x000000FF 110 #define USP_RXC_DATA_LEN_OFFSET 0 111 112 #define USP_RXC_FRAME_LEN_MASK 0x0000FF00 113 #define USP_RXC_FRAME_LEN_OFFSET 8 114 115 #define USP_RXC_SHIFTER_LEN_MASK 0x001F0000 116 #define USP_RXC_SHIFTER_LEN_OFFSET 16 117 118 #define USP_START_EDGE_MODE 0x00800000 119 #define USP_I2S_SYNC_CHG 0x00200000 120 121 #define USP_RXC_CLK_DIVISOR_MASK 0x0F000000 122 #define USP_RXC_CLK_DIVISOR_OFFSET 24 123 #define USP_SINGLE_SYNC_MODE 0x00400000 124 125 /* Tx - RX Enable Register */ 126 127 #define USP_RX_ENA 0x00000001 128 #define USP_TX_ENA 0x00000002 129 130 /* USP Interrupt Enable and status Register */ 131 #define USP_RX_DONE_INT 0x00000001 132 #define USP_TX_DONE_INT 0x00000002 133 #define USP_RX_OFLOW_INT 0x00000004 134 #define USP_TX_UFLOW_INT 0x00000008 135 #define USP_RX_IO_DMA_INT 0x00000010 136 #define USP_TX_IO_DMA_INT 0x00000020 137 #define USP_RXFIFO_FULL_INT 0x00000040 138 #define USP_TXFIFO_EMPTY_INT 0x00000080 139 #define USP_RXFIFO_THD_INT 0x00000100 140 #define USP_TXFIFO_THD_INT 0x00000200 141 #define USP_UART_FRM_ERR_INT 0x00000400 142 #define USP_RX_TIMEOUT_INT 0x00000800 143 #define USP_TX_ALLOUT_INT 0x00001000 144 #define USP_RXD_BREAK_INT 0x00008000 145 146 /* All possible TX interruots */ 147 #define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\ 148 USP_TX_IO_DMA_INT|\ 149 USP_TXFIFO_EMPTY_INT|\ 150 USP_TXFIFO_THD_INT) 151 /* All possible RX interruots */ 152 #define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\ 153 USP_RX_IO_DMA_INT|\ 154 USP_RXFIFO_FULL_INT|\ 155 USP_RXFIFO_THD_INT|\ 156 USP_RX_TIMEOUT_INT) 157 158 #define USP_INT_ALL 0x1FFF 159 160 /* USP Pin I/O Data Register */ 161 162 #define USP_RFS_PIN_VALUE_MASK 0x00000001 163 #define USP_TFS_PIN_VALUE_MASK 0x00000002 164 #define USP_RXD_PIN_VALUE_MASK 0x00000004 165 #define USP_TXD_PIN_VALUE_MASK 0x00000008 166 #define USP_SCLK_PIN_VALUE_MASK 0x00000010 167 168 /* USP RISC/DSP Mode Register */ 169 #define USP_RISC_DSP_SEL 0x00000001 170 171 /* USP ASYNC PARAMETER Register*/ 172 173 #define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF 174 #define USP_ASYNC_TIMEOUT_OFFSET 0 175 #define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \ 176 <<USP_ASYNC_TIMEOUT_OFFSET) 177 178 #define USP_ASYNC_DIV2_MASK 0x003F0000 179 #define USP_ASYNC_DIV2_OFFSET 16 180 181 /* USP TX DMA I/O MODE Register */ 182 #define USP_TX_MODE_IO 0x00000001 183 184 /* USP TX DMA I/O Length Register */ 185 #define USP_TX_DATA_LEN_MASK 0xFFFFFFFF 186 #define USP_TX_DATA_LEN_OFFSET 0 187 188 /* USP TX FIFO Control Register */ 189 #define USP_TX_FIFO_WIDTH_MASK 0x00000003 190 #define USP_TX_FIFO_WIDTH_OFFSET 0 191 192 #define USP_TX_FIFO_THD_MASK 0x000001FC 193 #define USP_TX_FIFO_THD_OFFSET 2 194 195 /* USP TX FIFO Level Check Register */ 196 #define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F 197 #define USP_TX_FIFO_SC_OFFSET 0 198 #define USP_TX_FIFO_LC_OFFSET 10 199 #define USP_TX_FIFO_HC_OFFSET 20 200 201 #define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 202 << USP_TX_FIFO_SC_OFFSET) 203 #define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 204 << USP_TX_FIFO_LC_OFFSET) 205 #define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \ 206 << USP_TX_FIFO_HC_OFFSET) 207 208 /* USP TX FIFO Operation Register */ 209 #define USP_TX_FIFO_RESET 0x00000001 210 #define USP_TX_FIFO_START 0x00000002 211 212 /* USP TX FIFO Status Register */ 213 #define USP_TX_FIFO_LEVEL_MASK 0x0000007F 214 #define USP_TX_FIFO_LEVEL_OFFSET 0 215 216 #define USP_TX_FIFO_FULL 0x00000080 217 #define USP_TX_FIFO_EMPTY 0x00000100 218 219 /* USP TX FIFO Data Register */ 220 #define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF 221 #define USP_TX_FIFO_DATA_OFFSET 0 222 223 /* USP RX DMA I/O MODE Register */ 224 #define USP_RX_MODE_IO 0x00000001 225 #define USP_RX_DMA_FLUSH 0x00000004 226 227 /* USP RX DMA I/O Length Register */ 228 #define USP_RX_DATA_LEN_MASK 0xFFFFFFFF 229 #define USP_RX_DATA_LEN_OFFSET 0 230 231 /* USP RX FIFO Control Register */ 232 #define USP_RX_FIFO_WIDTH_MASK 0x00000003 233 #define USP_RX_FIFO_WIDTH_OFFSET 0 234 235 #define USP_RX_FIFO_THD_MASK 0x000001FC 236 #define USP_RX_FIFO_THD_OFFSET 2 237 238 /* USP RX FIFO Level Check Register */ 239 240 #define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F 241 #define USP_RX_FIFO_SC_OFFSET 0 242 #define USP_RX_FIFO_LC_OFFSET 10 243 #define USP_RX_FIFO_HC_OFFSET 20 244 245 #define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 246 << USP_RX_FIFO_SC_OFFSET) 247 #define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 248 << USP_RX_FIFO_LC_OFFSET) 249 #define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \ 250 << USP_RX_FIFO_HC_OFFSET) 251 252 /* USP RX FIFO Operation Register */ 253 #define USP_RX_FIFO_RESET 0x00000001 254 #define USP_RX_FIFO_START 0x00000002 255 256 /* USP RX FIFO Status Register */ 257 258 #define USP_RX_FIFO_LEVEL_MASK 0x0000007F 259 #define USP_RX_FIFO_LEVEL_OFFSET 0 260 261 #define USP_RX_FIFO_FULL 0x00000080 262 #define USP_RX_FIFO_EMPTY 0x00000100 263 264 /* USP RX FIFO Data Register */ 265 266 #define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF 267 #define USP_RX_FIFO_DATA_OFFSET 0 268 269 /* 270 * When rx thd irq occur, sender just disable tx empty irq, 271 * Remaining data in tx fifo wil also be sent out. 272 */ 273 #define USP_FIFO_SIZE 128 274 #define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2) 275 #define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2) 276 277 /* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */ 278 #define USP_FIFO_WIDTH_BYTE 0x00 279 #define USP_FIFO_WIDTH_WORD 0x01 280 #define USP_FIFO_WIDTH_DWORD 0x02 281 282 #define USP_ASYNC_DIV2 16 283 284 #define USP_PLUGOUT_RETRY_CNT 2 285 286 #define USP_TX_RX_FIFO_WIDTH_DWORD 2 287 288 #define SIRF_USP_DIV_MCLK 0 289 290 #define SIRF_USP_I2S_TFS_SYNC 0 291 #define SIRF_USP_I2S_RFS_SYNC 1 292 #endif 293